cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability

[linux-stable] / drivers / cxl / cxl.h

diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 28888bb0c0885922ec3094459f26189614ee96bb..7c8674079f1a8e3f26b8aa4361c964ec3ad69cdf 100644 (file)
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -582,12 +582,17 @@ cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev)
        return xa_load(&port->dports, (unsigned long)dport_dev);
 }
 
+struct cxl_rcrb_info {
+       resource_size_t base;
+       u16 aer_cap;
+};
+
 /**
  * struct cxl_dport - CXL downstream port
  * @dport: PCI bridge or firmware device representing the downstream link
  * @port_id: unique hardware identifier for dport in decoder target list
  * @component_reg_phys: downstream port component registers
- * @rcrb: base address for the Root Complex Register Block
+ * @rcrb: Data about the Root Complex Register Block layout
  * @rch: Indicate whether this dport was enumerated in RCH or VH mode
  * @port: reference to cxl_port that contains this downstream port
  */
@@ -595,7 +600,7 @@ struct cxl_dport {
        struct device *dport;
        int port_id;
        resource_size_t component_reg_phys;
-       resource_size_t rcrb;
+       struct cxl_rcrb_info rcrb;
        bool rch;
        struct cxl_port *port;
 };