]> git.itanic.dy.fi Git - linux-stable/commit
cxl/dax: Create dax devices for CXL RAM regions
authorDan Williams <dan.j.williams@intel.com>
Fri, 10 Feb 2023 09:07:19 +0000 (01:07 -0800)
committerDan Williams <dan.j.williams@intel.com>
Sat, 11 Feb 2023 01:33:45 +0000 (17:33 -0800)
commit09d09e04d2fcf88c4620dd28097e0e2a8f720eac
tree21a7e381b6640bd12821f05fa9aa52f0dfb41cfd
parente9ee9fe3a9d4ae0e1e935fc2ec1218b66a043cae
cxl/dax: Create dax devices for CXL RAM regions

While platform firmware takes some responsibility for mapping the RAM
capacity of CXL devices present at boot, the OS is responsible for
mapping the remainder and hot-added devices. Platform firmware is also
responsible for identifying the platform general purpose memory pool,
typically DDR attached DRAM, and arranging for the remainder to be 'Soft
Reserved'. That reservation allows the CXL subsystem to route the memory
to core-mm via memory-hotplug (dax_kmem), or leave it for dedicated
access (device-dax).

The new 'struct cxl_dax_region' object allows for a CXL memory resource
(region) to be published, but also allow for udev and module policy to
act on that event. It also prevents cxl_core.ko from having a module
loading dependency on any drivers/dax/ modules.

Tested-by: Fan Ni <fan.ni@samsung.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/167602003896.1924368.10335442077318970468.stgit@dwillia2-xfh.jf.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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drivers/cxl/acpi.c
drivers/cxl/core/core.h
drivers/cxl/core/port.c
drivers/cxl/core/region.c
drivers/cxl/cxl.h
drivers/dax/Kconfig
drivers/dax/Makefile
drivers/dax/cxl.c [new file with mode: 0644]
drivers/dax/hmem/hmem.c