]> git.itanic.dy.fi Git - linux-stable/commit
cxl/memdev: Formalize endpoint port linkage
authorDan Williams <dan.j.williams@intel.com>
Thu, 15 Jun 2023 01:30:43 +0000 (18:30 -0700)
committerDan Williams <dan.j.williams@intel.com>
Sun, 25 Jun 2023 21:31:33 +0000 (14:31 -0700)
commit516b300c4ca86aa7953b75ce79b5c5eea5779b22
tree904fab8243e1b30d6aa89fba09207b67dd271208
parentf3c8a37a432e65dda1384929198dd12c1df3ea38
cxl/memdev: Formalize endpoint port linkage

Move the endpoint port that the cxl_mem driver establishes from drvdata
to a first class attribute. This is in preparation for device-memory
drivers reusing the CXL core for memory region management. Those drivers
need a type-safe method to retrieve their CXL port linkage. Leave
drvdata for private usage of the cxl_mem driver not external consumers
of a 'struct cxl_memdev' object.

Reviewed-by: Fan Ni <fan.ni@samsung.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/168679264292.3436160.3901392135863405807.stgit@dwillia2-xfh.jf.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
drivers/cxl/core/memdev.c
drivers/cxl/core/pmem.c
drivers/cxl/core/port.c
drivers/cxl/cxlmem.h