cxl/port: Quiet warning messages from the cxl_test environment

cxl/port: Quiet warning messages from the cxl_test environment

The cxl_test platform device CXL port hierarchy is useful for testing,
but throws warning messages of the form:

    cxl_mem mem2: at cxl_root_port.1 no parent for dport: platform
    cxl_mem mem3: at cxl_root_port.2 no parent for dport: platform
    cxl_mem mem4: at cxl_root_port.3 no parent for dport: platform
    cxl_mem mem5: at cxl_root_port.0 no parent for dport: platform
    cxl_mem mem6: at cxl_root_port.1 no parent for dport: platform
    cxl_mem mem7: at cxl_root_port.2 no parent for dport: platform
    cxl_mem mem8: at cxl_root_port.3 no parent for dport: platform
    cxl_mem mem9: at cxl_root_port.4 no parent for dport: platform
    cxl_mem mem10: at cxl_root_port.4 no parent for dport: platform

...and this message when running testing in QEMU:

    cxl_region region4: Bypassing cpu_cache_invalidate_memregion() for testing!

Noisy cxl_test warnings have caused other regressions to be missed. In
the interest of using cxl_test for early detection of dev_err() and
dev_warn() messages, silence platform device topology and
cache-invalidation messages.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>