]> git.itanic.dy.fi Git - linux-stable/commit
dt-bindings: memory: synopsys,ddrc-ecc: Detach Zynq DDRC controller support
authorSerge Semin <Sergey.Semin@baikalelectronics.ru>
Sat, 10 Sep 2022 19:42:32 +0000 (22:42 +0300)
committerKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Wed, 21 Sep 2022 18:30:47 +0000 (20:30 +0200)
commit845081313632b6a27dff576cf102b4aecb4654cf
treec4220986c0bc29f5c52a8a3cf023ab18a3151e85
parent9f8fb8032febf594914999c33493c682eaf138cb
dt-bindings: memory: synopsys,ddrc-ecc: Detach Zynq DDRC controller support

The Zynq A05 DDRC controller has nothing in common with DW uMCTL2 DDRC:
the CSRs layout is absolutely different and it doesn't support IRQs unlike
DW uMCTL2 DDR controller of all versions (v1.x, v2.x and v3.x). Thus there
is no any reason to have these controllers described in the same bindings.
Let's split the DT-schema up.

Note since the synopsys,ddrc-ecc.yaml schema describes the Synopsys DW
uMCTL2 DDR controller only, we need to accordingly fix the device
descriptions.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220910194237.10142-15-Sergey.Semin@baikalelectronics.ru
Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml
Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml [new file with mode: 0644]
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