]> git.itanic.dy.fi Git - linux-stable/commit
dt-bindings: PCI: dwc: Add phys/phy-names common properties
authorSerge Semin <Sergey.Semin@baikalelectronics.ru>
Sun, 13 Nov 2022 19:12:46 +0000 (22:12 +0300)
committerLorenzo Pieralisi <lpieralisi@kernel.org>
Wed, 23 Nov 2022 15:01:54 +0000 (16:01 +0100)
commit875596361910711f3e7ba6314075d867e4b74fd1
tree46c51547bd97adf30f9abc97cb211a6a1ec360fa
parentb9fe9985aee2cb62814671b883b9cbfa1c941ab3
dt-bindings: PCI: dwc: Add phys/phy-names common properties

It's normal to have the DW PCIe RP/EP DT-nodes equipped with the explicit
PHY phandle references. There can be up to 16 PHYs attach in accordance
with the maximum number of supported PCIe lanes. Let's extend the common
DW PCIe controller schema with the 'phys' and 'phy-names' properties
definition. There two types PHY names are defined: preferred generic names
'^pcie[0-9]+$' and non-preferred vendor-specific names
'^pcie([0-9]+|-?phy[0-9]*)?$' so to match the names currently supported by
the DW PCIe platform drivers ("pcie": meson; "pciephy": qcom, imx6;
"pcie-phy": uniphier, rockchip, spear13xx; "pcie": intel-gw; "pcie-phy%d":
keystone, dra7xx; "pcie": histb, etc).

Link: https://lore.kernel.org/r/20221113191301.5526-6-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml