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(merge: 5a6fe61 6980daa)
Merge branch 'for-6.3/cxl-rr-emu' into cxl/next
authorDan Williams <dan.j.williams@intel.com>
Wed, 15 Feb 2023 00:06:10 +0000 (16:06 -0800)
committerDan Williams <dan.j.williams@intel.com>
Wed, 15 Feb 2023 00:06:10 +0000 (16:06 -0800)
commita5fcd228ca1db9810ba1ed461c90b6ee933b9daf
tree814f208a81af8e90bff8619e2eed5d167b400dd2tree | snapshot
parent5a6fe61facdb7f830895712b31fb39f544ffc165commit | diff
parent6980daaa3ed5959bf4fe2719d96b1da437026b58commit | diff
Merge branch 'for-6.3/cxl-rr-emu' into cxl/next

Pick up the CXL DVSEC range register emulation for v6.3, and resolve
conflicts with the cxl_port_probe() split (from for-6.3/cxl-ram-region)
and event handling (from for-6.3/cxl-events).
drivers/cxl/core/hdm.c diff1 | diff2 | blob | history
drivers/cxl/core/pci.c diff1 | diff2 | blob | history
drivers/cxl/cxl.h diff1 | diff2 | blob | history
drivers/cxl/cxlmem.h diff1 | diff2 | blob | history
drivers/cxl/cxlpci.h diff1 | diff2 | blob | history
drivers/cxl/port.c diff1 | diff2 | blob | history
tools/testing/cxl/Kbuild diff1 | diff2 | blob | history
tools/testing/cxl/test/cxl.c diff1 | diff2 | blob | history
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