1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_EXTRA_PHDRS
14 select ARCH_BINFMT_ELF_STATE
15 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
16 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
17 select ARCH_ENABLE_MEMORY_HOTPLUG
18 select ARCH_ENABLE_MEMORY_HOTREMOVE
19 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
20 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
21 select ARCH_HAS_CACHE_LINE_SIZE
22 select ARCH_HAS_CURRENT_STACK_POINTER
23 select ARCH_HAS_DEBUG_VIRTUAL
24 select ARCH_HAS_DEBUG_VM_PGTABLE
25 select ARCH_HAS_DMA_PREP_COHERENT
26 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
27 select ARCH_HAS_FAST_MULTIPLIER
28 select ARCH_HAS_FORTIFY_SOURCE
29 select ARCH_HAS_GCOV_PROFILE_ALL
30 select ARCH_HAS_GIGANTIC_PAGE
32 select ARCH_HAS_KEEPINITRD
33 select ARCH_HAS_MEMBARRIER_SYNC_CORE
34 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
35 select ARCH_HAS_PTE_DEVMAP
36 select ARCH_HAS_PTE_SPECIAL
37 select ARCH_HAS_SETUP_DMA_OPS
38 select ARCH_HAS_SET_DIRECT_MAP
39 select ARCH_HAS_SET_MEMORY
41 select ARCH_HAS_STRICT_KERNEL_RWX
42 select ARCH_HAS_STRICT_MODULE_RWX
43 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
44 select ARCH_HAS_SYNC_DMA_FOR_CPU
45 select ARCH_HAS_SYSCALL_WRAPPER
46 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
47 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
48 select ARCH_HAS_VM_GET_PAGE_PROT
49 select ARCH_HAS_ZONE_DMA_SET if EXPERT
50 select ARCH_HAVE_ELF_PROT
51 select ARCH_HAVE_NMI_SAFE_CMPXCHG
52 select ARCH_INLINE_READ_LOCK if !PREEMPTION
53 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
54 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
55 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
56 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
57 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
58 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
59 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
60 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
61 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
62 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
63 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
64 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
65 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
66 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
67 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
68 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
69 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
70 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
71 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
72 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
73 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
74 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
75 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
76 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
77 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
78 select ARCH_KEEP_MEMBLOCK
79 select ARCH_USE_CMPXCHG_LOCKREF
80 select ARCH_USE_GNU_PROPERTY
81 select ARCH_USE_MEMTEST
82 select ARCH_USE_QUEUED_RWLOCKS
83 select ARCH_USE_QUEUED_SPINLOCKS
84 select ARCH_USE_SYM_ANNOTATIONS
85 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
86 select ARCH_SUPPORTS_HUGETLBFS
87 select ARCH_SUPPORTS_MEMORY_FAILURE
88 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
89 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
90 select ARCH_SUPPORTS_LTO_CLANG_THIN
91 select ARCH_SUPPORTS_CFI_CLANG
92 select ARCH_SUPPORTS_ATOMIC_RMW
93 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
94 select ARCH_SUPPORTS_NUMA_BALANCING
95 select ARCH_SUPPORTS_PAGE_TABLE_CHECK
96 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
97 select ARCH_WANT_DEFAULT_BPF_JIT
98 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
99 select ARCH_WANT_FRAME_POINTERS
100 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
101 select ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP
102 select ARCH_WANT_LD_ORPHAN_WARN
103 select ARCH_WANTS_NO_INSTR
104 select ARCH_HAS_UBSAN_SANITIZE_ALL
106 select ARM_ARCH_TIMER
108 select AUDIT_ARCH_COMPAT_GENERIC
109 select ARM_GIC_V2M if PCI
111 select ARM_GIC_V3_ITS if PCI
113 select BUILDTIME_TABLE_SORT
114 select CLONE_BACKWARDS
116 select CPU_PM if (SUSPEND || CPU_IDLE)
118 select DCACHE_WORD_ACCESS
119 select DMA_DIRECT_REMAP
122 select GENERIC_ALLOCATOR
123 select GENERIC_ARCH_TOPOLOGY
124 select GENERIC_CLOCKEVENTS_BROADCAST
125 select GENERIC_CPU_AUTOPROBE
126 select GENERIC_CPU_VULNERABILITIES
127 select GENERIC_EARLY_IOREMAP
128 select GENERIC_IDLE_POLL_SETUP
129 select GENERIC_IRQ_IPI
130 select GENERIC_IRQ_PROBE
131 select GENERIC_IRQ_SHOW
132 select GENERIC_IRQ_SHOW_LEVEL
133 select GENERIC_LIB_DEVMEM_IS_ALLOWED
134 select GENERIC_PCI_IOMAP
135 select GENERIC_PTDUMP
136 select GENERIC_SCHED_CLOCK
137 select GENERIC_SMP_IDLE_THREAD
138 select GENERIC_TIME_VSYSCALL
139 select GENERIC_GETTIMEOFDAY
140 select GENERIC_VDSO_TIME_NS
141 select HARDIRQS_SW_RESEND
145 select HAVE_ACPI_APEI if (ACPI && EFI)
146 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
147 select HAVE_ARCH_AUDITSYSCALL
148 select HAVE_ARCH_BITREVERSE
149 select HAVE_ARCH_COMPILER_H
150 select HAVE_ARCH_HUGE_VMAP
151 select HAVE_ARCH_JUMP_LABEL
152 select HAVE_ARCH_JUMP_LABEL_RELATIVE
153 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
154 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
155 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
156 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
157 # Some instrumentation may be unsound, hence EXPERT
158 select HAVE_ARCH_KCSAN if EXPERT
159 select HAVE_ARCH_KFENCE
160 select HAVE_ARCH_KGDB
161 select HAVE_ARCH_MMAP_RND_BITS
162 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
163 select HAVE_ARCH_PREL32_RELOCATIONS
164 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
165 select HAVE_ARCH_SECCOMP_FILTER
166 select HAVE_ARCH_STACKLEAK
167 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
168 select HAVE_ARCH_TRACEHOOK
169 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
170 select HAVE_ARCH_VMAP_STACK
171 select HAVE_ARM_SMCCC
172 select HAVE_ASM_MODVERSIONS
174 select HAVE_C_RECORDMCOUNT
175 select HAVE_CMPXCHG_DOUBLE
176 select HAVE_CMPXCHG_LOCAL
177 select HAVE_CONTEXT_TRACKING
178 select HAVE_DEBUG_KMEMLEAK
179 select HAVE_DMA_CONTIGUOUS
180 select HAVE_DYNAMIC_FTRACE
181 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
182 if DYNAMIC_FTRACE_WITH_REGS
183 select HAVE_EFFICIENT_UNALIGNED_ACCESS
185 select HAVE_FTRACE_MCOUNT_RECORD
186 select HAVE_FUNCTION_TRACER
187 select HAVE_FUNCTION_ERROR_INJECTION
188 select HAVE_FUNCTION_GRAPH_TRACER
189 select HAVE_GCC_PLUGINS
190 select HAVE_HW_BREAKPOINT if PERF_EVENTS
191 select HAVE_IRQ_TIME_ACCOUNTING
194 select HAVE_PATA_PLATFORM
195 select HAVE_PERF_EVENTS
196 select HAVE_PERF_REGS
197 select HAVE_PERF_USER_STACK_DUMP
198 select HAVE_PREEMPT_DYNAMIC_KEY
199 select HAVE_REGS_AND_STACK_ACCESS_API
200 select HAVE_POSIX_CPU_TIMERS_TASK_WORK
201 select HAVE_FUNCTION_ARG_ACCESS_API
202 select MMU_GATHER_RCU_TABLE_FREE
204 select HAVE_STACKPROTECTOR
205 select HAVE_SYSCALL_TRACEPOINTS
207 select HAVE_KRETPROBES
208 select HAVE_GENERIC_VDSO
209 select IOMMU_DMA if IOMMU_SUPPORT
211 select IRQ_FORCED_THREADING
212 select KASAN_VMALLOC if KASAN
213 select MODULES_USE_ELF_RELA
214 select NEED_DMA_MAP_STATE
215 select NEED_SG_DMA_LENGTH
217 select OF_EARLY_FLATTREE
218 select PCI_DOMAINS_GENERIC if PCI
219 select PCI_ECAM if (ACPI && PCI)
220 select PCI_SYSCALL if PCI
225 select SYSCTL_EXCEPTION_TRACE
226 select THREAD_INFO_IN_TASK
227 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
228 select TRACE_IRQFLAGS_SUPPORT
229 select TRACE_IRQFLAGS_NMI_SUPPORT
231 ARM 64-bit (AArch64) Linux support.
233 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS
235 # https://github.com/ClangBuiltLinux/linux/issues/1507
236 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600))
237 select HAVE_DYNAMIC_FTRACE_WITH_REGS
239 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS
241 depends on $(cc-option,-fpatchable-function-entry=2)
242 select HAVE_DYNAMIC_FTRACE_WITH_REGS
250 config ARM64_PAGE_SHIFT
252 default 16 if ARM64_64K_PAGES
253 default 14 if ARM64_16K_PAGES
256 config ARM64_CONT_PTE_SHIFT
258 default 5 if ARM64_64K_PAGES
259 default 7 if ARM64_16K_PAGES
262 config ARM64_CONT_PMD_SHIFT
264 default 5 if ARM64_64K_PAGES
265 default 5 if ARM64_16K_PAGES
268 config ARCH_MMAP_RND_BITS_MIN
269 default 14 if ARM64_64K_PAGES
270 default 16 if ARM64_16K_PAGES
273 # max bits determined by the following formula:
274 # VA_BITS - PAGE_SHIFT - 3
275 config ARCH_MMAP_RND_BITS_MAX
276 default 19 if ARM64_VA_BITS=36
277 default 24 if ARM64_VA_BITS=39
278 default 27 if ARM64_VA_BITS=42
279 default 30 if ARM64_VA_BITS=47
280 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
281 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
282 default 33 if ARM64_VA_BITS=48
283 default 14 if ARM64_64K_PAGES
284 default 16 if ARM64_16K_PAGES
287 config ARCH_MMAP_RND_COMPAT_BITS_MIN
288 default 7 if ARM64_64K_PAGES
289 default 9 if ARM64_16K_PAGES
292 config ARCH_MMAP_RND_COMPAT_BITS_MAX
298 config STACKTRACE_SUPPORT
301 config ILLEGAL_POINTER_VALUE
303 default 0xdead000000000000
305 config LOCKDEP_SUPPORT
312 config GENERIC_BUG_RELATIVE_POINTERS
314 depends on GENERIC_BUG
316 config GENERIC_HWEIGHT
322 config GENERIC_CALIBRATE_DELAY
325 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
331 config KERNEL_MODE_NEON
334 config FIX_EARLYCON_MEM
337 config PGTABLE_LEVELS
339 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
340 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
341 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
342 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
343 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
344 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
346 config ARCH_SUPPORTS_UPROBES
349 config ARCH_PROC_KCORE_TEXT
352 config BROKEN_GAS_INST
353 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
355 config KASAN_SHADOW_OFFSET
357 depends on KASAN_GENERIC || KASAN_SW_TAGS
358 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
359 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
360 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
361 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
362 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
363 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
364 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
365 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
366 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
367 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
368 default 0xffffffffffffffff
370 source "arch/arm64/Kconfig.platforms"
372 menu "Kernel Features"
374 menu "ARM errata workarounds via the alternatives framework"
376 config ARM64_WORKAROUND_CLEAN_CACHE
379 config ARM64_ERRATUM_826319
380 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
382 select ARM64_WORKAROUND_CLEAN_CACHE
384 This option adds an alternative code sequence to work around ARM
385 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
386 AXI master interface and an L2 cache.
388 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
389 and is unable to accept a certain write via this interface, it will
390 not progress on read data presented on the read data channel and the
393 The workaround promotes data cache clean instructions to
394 data cache clean-and-invalidate.
395 Please note that this does not necessarily enable the workaround,
396 as it depends on the alternative framework, which will only patch
397 the kernel if an affected CPU is detected.
401 config ARM64_ERRATUM_827319
402 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
404 select ARM64_WORKAROUND_CLEAN_CACHE
406 This option adds an alternative code sequence to work around ARM
407 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
408 master interface and an L2 cache.
410 Under certain conditions this erratum can cause a clean line eviction
411 to occur at the same time as another transaction to the same address
412 on the AMBA 5 CHI interface, which can cause data corruption if the
413 interconnect reorders the two transactions.
415 The workaround promotes data cache clean instructions to
416 data cache clean-and-invalidate.
417 Please note that this does not necessarily enable the workaround,
418 as it depends on the alternative framework, which will only patch
419 the kernel if an affected CPU is detected.
423 config ARM64_ERRATUM_824069
424 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
426 select ARM64_WORKAROUND_CLEAN_CACHE
428 This option adds an alternative code sequence to work around ARM
429 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
430 to a coherent interconnect.
432 If a Cortex-A53 processor is executing a store or prefetch for
433 write instruction at the same time as a processor in another
434 cluster is executing a cache maintenance operation to the same
435 address, then this erratum might cause a clean cache line to be
436 incorrectly marked as dirty.
438 The workaround promotes data cache clean instructions to
439 data cache clean-and-invalidate.
440 Please note that this option does not necessarily enable the
441 workaround, as it depends on the alternative framework, which will
442 only patch the kernel if an affected CPU is detected.
446 config ARM64_ERRATUM_819472
447 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
449 select ARM64_WORKAROUND_CLEAN_CACHE
451 This option adds an alternative code sequence to work around ARM
452 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
453 present when it is connected to a coherent interconnect.
455 If the processor is executing a load and store exclusive sequence at
456 the same time as a processor in another cluster is executing a cache
457 maintenance operation to the same address, then this erratum might
458 cause data corruption.
460 The workaround promotes data cache clean instructions to
461 data cache clean-and-invalidate.
462 Please note that this does not necessarily enable the workaround,
463 as it depends on the alternative framework, which will only patch
464 the kernel if an affected CPU is detected.
468 config ARM64_ERRATUM_832075
469 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
472 This option adds an alternative code sequence to work around ARM
473 erratum 832075 on Cortex-A57 parts up to r1p2.
475 Affected Cortex-A57 parts might deadlock when exclusive load/store
476 instructions to Write-Back memory are mixed with Device loads.
478 The workaround is to promote device loads to use Load-Acquire
480 Please note that this does not necessarily enable the workaround,
481 as it depends on the alternative framework, which will only patch
482 the kernel if an affected CPU is detected.
486 config ARM64_ERRATUM_834220
487 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
491 This option adds an alternative code sequence to work around ARM
492 erratum 834220 on Cortex-A57 parts up to r1p2.
494 Affected Cortex-A57 parts might report a Stage 2 translation
495 fault as the result of a Stage 1 fault for load crossing a
496 page boundary when there is a permission or device memory
497 alignment fault at Stage 1 and a translation fault at Stage 2.
499 The workaround is to verify that the Stage 1 translation
500 doesn't generate a fault before handling the Stage 2 fault.
501 Please note that this does not necessarily enable the workaround,
502 as it depends on the alternative framework, which will only patch
503 the kernel if an affected CPU is detected.
507 config ARM64_ERRATUM_1742098
508 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
512 This option removes the AES hwcap for aarch32 user-space to
513 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
515 Affected parts may corrupt the AES state if an interrupt is
516 taken between a pair of AES instructions. These instructions
517 are only present if the cryptography extensions are present.
518 All software should have a fallback implementation for CPUs
519 that don't implement the cryptography extensions.
523 config ARM64_ERRATUM_845719
524 bool "Cortex-A53: 845719: a load might read incorrect data"
528 This option adds an alternative code sequence to work around ARM
529 erratum 845719 on Cortex-A53 parts up to r0p4.
531 When running a compat (AArch32) userspace on an affected Cortex-A53
532 part, a load at EL0 from a virtual address that matches the bottom 32
533 bits of the virtual address used by a recent load at (AArch64) EL1
534 might return incorrect data.
536 The workaround is to write the contextidr_el1 register on exception
537 return to a 32-bit task.
538 Please note that this does not necessarily enable the workaround,
539 as it depends on the alternative framework, which will only patch
540 the kernel if an affected CPU is detected.
544 config ARM64_ERRATUM_843419
545 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
547 select ARM64_MODULE_PLTS if MODULES
549 This option links the kernel with '--fix-cortex-a53-843419' and
550 enables PLT support to replace certain ADRP instructions, which can
551 cause subsequent memory accesses to use an incorrect address on
552 Cortex-A53 parts up to r0p4.
556 config ARM64_LD_HAS_FIX_ERRATUM_843419
557 def_bool $(ld-option,--fix-cortex-a53-843419)
559 config ARM64_ERRATUM_1024718
560 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
563 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
565 Affected Cortex-A55 cores (all revisions) could cause incorrect
566 update of the hardware dirty bit when the DBM/AP bits are updated
567 without a break-before-make. The workaround is to disable the usage
568 of hardware DBM locally on the affected cores. CPUs not affected by
569 this erratum will continue to use the feature.
573 config ARM64_ERRATUM_1418040
574 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
578 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
579 errata 1188873 and 1418040.
581 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
582 cause register corruption when accessing the timer registers
583 from AArch32 userspace.
587 config ARM64_WORKAROUND_SPECULATIVE_AT
590 config ARM64_ERRATUM_1165522
591 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
593 select ARM64_WORKAROUND_SPECULATIVE_AT
595 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
597 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
598 corrupted TLBs by speculating an AT instruction during a guest
603 config ARM64_ERRATUM_1319367
604 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
606 select ARM64_WORKAROUND_SPECULATIVE_AT
608 This option adds work arounds for ARM Cortex-A57 erratum 1319537
609 and A72 erratum 1319367
611 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
612 speculating an AT instruction during a guest context switch.
616 config ARM64_ERRATUM_1530923
617 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
619 select ARM64_WORKAROUND_SPECULATIVE_AT
621 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
623 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
624 corrupted TLBs by speculating an AT instruction during a guest
629 config ARM64_WORKAROUND_REPEAT_TLBI
632 config ARM64_ERRATUM_1286807
633 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
635 select ARM64_WORKAROUND_REPEAT_TLBI
637 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
639 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
640 address for a cacheable mapping of a location is being
641 accessed by a core while another core is remapping the virtual
642 address to a new physical page using the recommended
643 break-before-make sequence, then under very rare circumstances
644 TLBI+DSB completes before a read using the translation being
645 invalidated has been observed by other observers. The
646 workaround repeats the TLBI+DSB operation.
648 config ARM64_ERRATUM_1463225
649 bool "Cortex-A76: Software Step might prevent interrupt recognition"
652 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
654 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
655 of a system call instruction (SVC) can prevent recognition of
656 subsequent interrupts when software stepping is disabled in the
657 exception handler of the system call and either kernel debugging
658 is enabled or VHE is in use.
660 Work around the erratum by triggering a dummy step exception
661 when handling a system call from a task that is being stepped
662 in a VHE configuration of the kernel.
666 config ARM64_ERRATUM_1542419
667 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
670 This option adds a workaround for ARM Neoverse-N1 erratum
673 Affected Neoverse-N1 cores could execute a stale instruction when
674 modified by another CPU. The workaround depends on a firmware
677 Workaround the issue by hiding the DIC feature from EL0. This
678 forces user-space to perform cache maintenance.
682 config ARM64_ERRATUM_1508412
683 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
686 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
688 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
689 of a store-exclusive or read of PAR_EL1 and a load with device or
690 non-cacheable memory attributes. The workaround depends on a firmware
693 KVM guests must also have the workaround implemented or they can
696 Work around the issue by inserting DMB SY barriers around PAR_EL1
697 register reads and warning KVM users. The DMB barrier is sufficient
698 to prevent a speculative PAR_EL1 read.
702 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
705 config ARM64_ERRATUM_2051678
706 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
709 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
710 Affected Cortex-A510 might not respect the ordering rules for
711 hardware update of the page table's dirty bit. The workaround
712 is to not enable the feature on affected CPUs.
716 config ARM64_ERRATUM_2077057
717 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
720 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
721 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
722 expected, but a Pointer Authentication trap is taken instead. The
723 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
724 EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
726 This can only happen when EL2 is stepping EL1.
728 When these conditions occur, the SPSR_EL2 value is unchanged from the
729 previous guest entry, and can be restored from the in-memory copy.
733 config ARM64_ERRATUM_2119858
734 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
736 depends on CORESIGHT_TRBE
737 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
739 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
741 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
742 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
743 the event of a WRAP event.
745 Work around the issue by always making sure we move the TRBPTR_EL1 by
746 256 bytes before enabling the buffer and filling the first 256 bytes of
747 the buffer with ETM ignore packets upon disabling.
751 config ARM64_ERRATUM_2139208
752 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
754 depends on CORESIGHT_TRBE
755 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
757 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
759 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
760 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
761 the event of a WRAP event.
763 Work around the issue by always making sure we move the TRBPTR_EL1 by
764 256 bytes before enabling the buffer and filling the first 256 bytes of
765 the buffer with ETM ignore packets upon disabling.
769 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
772 config ARM64_ERRATUM_2054223
773 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
775 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
777 Enable workaround for ARM Cortex-A710 erratum 2054223
779 Affected cores may fail to flush the trace data on a TSB instruction, when
780 the PE is in trace prohibited state. This will cause losing a few bytes
783 Workaround is to issue two TSB consecutively on affected cores.
787 config ARM64_ERRATUM_2067961
788 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
790 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
792 Enable workaround for ARM Neoverse-N2 erratum 2067961
794 Affected cores may fail to flush the trace data on a TSB instruction, when
795 the PE is in trace prohibited state. This will cause losing a few bytes
798 Workaround is to issue two TSB consecutively on affected cores.
802 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
805 config ARM64_ERRATUM_2253138
806 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
807 depends on CORESIGHT_TRBE
809 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
811 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
813 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
814 for TRBE. Under some conditions, the TRBE might generate a write to the next
815 virtually addressed page following the last page of the TRBE address space
816 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
818 Work around this in the driver by always making sure that there is a
819 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
823 config ARM64_ERRATUM_2224489
824 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
825 depends on CORESIGHT_TRBE
827 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
829 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
831 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
832 for TRBE. Under some conditions, the TRBE might generate a write to the next
833 virtually addressed page following the last page of the TRBE address space
834 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
836 Work around this in the driver by always making sure that there is a
837 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
841 config ARM64_ERRATUM_2441009
842 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
844 select ARM64_WORKAROUND_REPEAT_TLBI
846 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
848 Under very rare circumstances, affected Cortex-A510 CPUs
849 may not handle a race between a break-before-make sequence on one
850 CPU, and another CPU accessing the same page. This could allow a
851 store to a page that has been unmapped.
853 Work around this by adding the affected CPUs to the list that needs
854 TLB sequences to be done twice.
858 config ARM64_ERRATUM_2064142
859 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
860 depends on CORESIGHT_TRBE
863 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
865 Affected Cortex-A510 core might fail to write into system registers after the
866 TRBE has been disabled. Under some conditions after the TRBE has been disabled
867 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
868 and TRBTRG_EL1 will be ignored and will not be effected.
870 Work around this in the driver by executing TSB CSYNC and DSB after collection
871 is stopped and before performing a system register write to one of the affected
876 config ARM64_ERRATUM_2038923
877 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
878 depends on CORESIGHT_TRBE
881 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
883 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
884 prohibited within the CPU. As a result, the trace buffer or trace buffer state
885 might be corrupted. This happens after TRBE buffer has been enabled by setting
886 TRBLIMITR_EL1.E, followed by just a single context synchronization event before
887 execution changes from a context, in which trace is prohibited to one where it
888 isn't, or vice versa. In these mentioned conditions, the view of whether trace
889 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
890 the trace buffer state might be corrupted.
892 Work around this in the driver by preventing an inconsistent view of whether the
893 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
894 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
895 two ISB instructions if no ERET is to take place.
899 config ARM64_ERRATUM_1902691
900 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
901 depends on CORESIGHT_TRBE
904 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
906 Affected Cortex-A510 core might cause trace data corruption, when being written
907 into the memory. Effectively TRBE is broken and hence cannot be used to capture
910 Work around this problem in the driver by just preventing TRBE initialization on
911 affected cpus. The firmware must have disabled the access to TRBE for the kernel
912 on such implementations. This will cover the kernel for any firmware that doesn't
917 config ARM64_ERRATUM_2457168
918 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
919 depends on ARM64_AMU_EXTN
922 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
924 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
925 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
926 incorrectly giving a significantly higher output value.
928 Work around this problem by returning 0 when reading the affected counter in
929 key locations that results in disabling all users of this counter. This effect
930 is the same to firmware disabling affected counters.
934 config CAVIUM_ERRATUM_22375
935 bool "Cavium erratum 22375, 24313"
938 Enable workaround for errata 22375 and 24313.
940 This implements two gicv3-its errata workarounds for ThunderX. Both
941 with a small impact affecting only ITS table allocation.
943 erratum 22375: only alloc 8MB table size
944 erratum 24313: ignore memory access type
946 The fixes are in ITS initialization and basically ignore memory access
947 type and table size provided by the TYPER and BASER registers.
951 config CAVIUM_ERRATUM_23144
952 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
956 ITS SYNC command hang for cross node io and collections/cpu mapping.
960 config CAVIUM_ERRATUM_23154
961 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
964 The ThunderX GICv3 implementation requires a modified version for
965 reading the IAR status to ensure data synchronization
966 (access to icc_iar1_el1 is not sync'ed before and after).
968 It also suffers from erratum 38545 (also present on Marvell's
969 OcteonTX and OcteonTX2), resulting in deactivated interrupts being
970 spuriously presented to the CPU interface.
974 config CAVIUM_ERRATUM_27456
975 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
978 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
979 instructions may cause the icache to become corrupted if it
980 contains data for a non-current ASID. The fix is to
981 invalidate the icache when changing the mm context.
985 config CAVIUM_ERRATUM_30115
986 bool "Cavium erratum 30115: Guest may disable interrupts in host"
989 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
990 1.2, and T83 Pass 1.0, KVM guest execution may disable
991 interrupts in host. Trapping both GICv3 group-0 and group-1
992 accesses sidesteps the issue.
996 config CAVIUM_TX2_ERRATUM_219
997 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1000 On Cavium ThunderX2, a load, store or prefetch instruction between a
1001 TTBR update and the corresponding context synchronizing operation can
1002 cause a spurious Data Abort to be delivered to any hardware thread in
1005 Work around the issue by avoiding the problematic code sequence and
1006 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
1007 trap handler performs the corresponding register access, skips the
1008 instruction and ensures context synchronization by virtue of the
1013 config FUJITSU_ERRATUM_010001
1014 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1017 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1018 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1019 accesses may cause undefined fault (Data abort, DFSC=0b111111).
1020 This fault occurs under a specific hardware condition when a
1021 load/store instruction performs an address translation using:
1022 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1023 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1024 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1025 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1027 The workaround is to ensure these bits are clear in TCR_ELx.
1028 The workaround only affects the Fujitsu-A64FX.
1032 config HISILICON_ERRATUM_161600802
1033 bool "Hip07 161600802: Erroneous redistributor VLPI base"
1036 The HiSilicon Hip07 SoC uses the wrong redistributor base
1037 when issued ITS commands such as VMOVP and VMAPP, and requires
1038 a 128kB offset to be applied to the target address in this commands.
1042 config QCOM_FALKOR_ERRATUM_1003
1043 bool "Falkor E1003: Incorrect translation due to ASID change"
1046 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1047 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1048 in TTBR1_EL1, this situation only occurs in the entry trampoline and
1049 then only for entries in the walk cache, since the leaf translation
1050 is unchanged. Work around the erratum by invalidating the walk cache
1051 entries for the trampoline before entering the kernel proper.
1053 config QCOM_FALKOR_ERRATUM_1009
1054 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
1056 select ARM64_WORKAROUND_REPEAT_TLBI
1058 On Falkor v1, the CPU may prematurely complete a DSB following a
1059 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
1060 one more time to fix the issue.
1064 config QCOM_QDF2400_ERRATUM_0065
1065 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
1068 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1069 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
1070 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1074 config QCOM_FALKOR_ERRATUM_E1041
1075 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1078 Falkor CPU may speculatively fetch instructions from an improper
1079 memory location when MMU translation is changed from SCTLR_ELn[M]=1
1080 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1084 config NVIDIA_CARMEL_CNP_ERRATUM
1085 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1088 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1089 invalidate shared TLB entries installed by a different core, as it would
1090 on standard ARM cores.
1094 config SOCIONEXT_SYNQUACER_PREITS
1095 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1098 Socionext Synquacer SoCs implement a separate h/w block to generate
1099 MSI doorbell writes with non-zero values for the device ID.
1103 endmenu # "ARM errata workarounds via the alternatives framework"
1107 default ARM64_4K_PAGES
1109 Page size (translation granule) configuration.
1111 config ARM64_4K_PAGES
1114 This feature enables 4KB pages support.
1116 config ARM64_16K_PAGES
1119 The system will use 16KB pages support. AArch32 emulation
1120 requires applications compiled with 16K (or a multiple of 16K)
1123 config ARM64_64K_PAGES
1126 This feature enables 64KB pages support (4KB by default)
1127 allowing only two levels of page tables and faster TLB
1128 look-up. AArch32 emulation requires applications compiled
1129 with 64K aligned segments.
1134 prompt "Virtual address space size"
1135 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
1136 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
1137 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
1139 Allows choosing one of multiple possible virtual address
1140 space sizes. The level of translation table is determined by
1141 a combination of page size and virtual address space size.
1143 config ARM64_VA_BITS_36
1144 bool "36-bit" if EXPERT
1145 depends on ARM64_16K_PAGES
1147 config ARM64_VA_BITS_39
1149 depends on ARM64_4K_PAGES
1151 config ARM64_VA_BITS_42
1153 depends on ARM64_64K_PAGES
1155 config ARM64_VA_BITS_47
1157 depends on ARM64_16K_PAGES
1159 config ARM64_VA_BITS_48
1162 config ARM64_VA_BITS_52
1164 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1166 Enable 52-bit virtual addressing for userspace when explicitly
1167 requested via a hint to mmap(). The kernel will also use 52-bit
1168 virtual addresses for its own mappings (provided HW support for
1169 this feature is available, otherwise it reverts to 48-bit).
1171 NOTE: Enabling 52-bit virtual addressing in conjunction with
1172 ARMv8.3 Pointer Authentication will result in the PAC being
1173 reduced from 7 bits to 3 bits, which may have a significant
1174 impact on its susceptibility to brute-force attacks.
1176 If unsure, select 48-bit virtual addressing instead.
1180 config ARM64_FORCE_52BIT
1181 bool "Force 52-bit virtual addresses for userspace"
1182 depends on ARM64_VA_BITS_52 && EXPERT
1184 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1185 to maintain compatibility with older software by providing 48-bit VAs
1186 unless a hint is supplied to mmap.
1188 This configuration option disables the 48-bit compatibility logic, and
1189 forces all userspace addresses to be 52-bit on HW that supports it. One
1190 should only enable this configuration option for stress testing userspace
1191 memory management code. If unsure say N here.
1193 config ARM64_VA_BITS
1195 default 36 if ARM64_VA_BITS_36
1196 default 39 if ARM64_VA_BITS_39
1197 default 42 if ARM64_VA_BITS_42
1198 default 47 if ARM64_VA_BITS_47
1199 default 48 if ARM64_VA_BITS_48
1200 default 52 if ARM64_VA_BITS_52
1203 prompt "Physical address space size"
1204 default ARM64_PA_BITS_48
1206 Choose the maximum physical address range that the kernel will
1209 config ARM64_PA_BITS_48
1212 config ARM64_PA_BITS_52
1213 bool "52-bit (ARMv8.2)"
1214 depends on ARM64_64K_PAGES
1215 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1217 Enable support for a 52-bit physical address space, introduced as
1218 part of the ARMv8.2-LPA extension.
1220 With this enabled, the kernel will also continue to work on CPUs that
1221 do not support ARMv8.2-LPA, but with some added memory overhead (and
1222 minor performance overhead).
1226 config ARM64_PA_BITS
1228 default 48 if ARM64_PA_BITS_48
1229 default 52 if ARM64_PA_BITS_52
1233 default CPU_LITTLE_ENDIAN
1235 Select the endianness of data accesses performed by the CPU. Userspace
1236 applications will need to be compiled and linked for the endianness
1237 that is selected here.
1239 config CPU_BIG_ENDIAN
1240 bool "Build big-endian kernel"
1241 depends on !LD_IS_LLD || LLD_VERSION >= 130000
1243 Say Y if you plan on running a kernel with a big-endian userspace.
1245 config CPU_LITTLE_ENDIAN
1246 bool "Build little-endian kernel"
1248 Say Y if you plan on running a kernel with a little-endian userspace.
1249 This is usually the case for distributions targeting arm64.
1254 bool "Multi-core scheduler support"
1256 Multi-core scheduler support improves the CPU scheduler's decision
1257 making when dealing with multi-core CPU chips at a cost of slightly
1258 increased overhead in some places. If unsure say N here.
1260 config SCHED_CLUSTER
1261 bool "Cluster scheduler support"
1263 Cluster scheduler support improves the CPU scheduler's decision
1264 making when dealing with machines that have clusters of CPUs.
1265 Cluster usually means a couple of CPUs which are placed closely
1266 by sharing mid-level caches, last-level cache tags or internal
1270 bool "SMT scheduler support"
1272 Improves the CPU scheduler's decision making when dealing with
1273 MultiThreading at a cost of slightly increased overhead in some
1274 places. If unsure say N here.
1277 int "Maximum number of CPUs (2-4096)"
1282 bool "Support for hot-pluggable CPUs"
1283 select GENERIC_IRQ_MIGRATION
1285 Say Y here to experiment with turning CPUs off and on. CPUs
1286 can be controlled through /sys/devices/system/cpu.
1288 # Common NUMA Features
1290 bool "NUMA Memory Allocation and Scheduler Support"
1291 select GENERIC_ARCH_NUMA
1292 select ACPI_NUMA if ACPI
1294 select HAVE_SETUP_PER_CPU_AREA
1295 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1296 select NEED_PER_CPU_PAGE_FIRST_CHUNK
1297 select USE_PERCPU_NUMA_NODE_ID
1299 Enable NUMA (Non-Uniform Memory Access) support.
1301 The kernel will try to allocate memory used by a CPU on the
1302 local memory of the CPU and add some more
1303 NUMA awareness to the kernel.
1306 int "Maximum NUMA Nodes (as a power of 2)"
1311 Specify the maximum number of NUMA Nodes available on the target
1312 system. Increases memory reserved to accommodate various tables.
1314 source "kernel/Kconfig.hz"
1316 config ARCH_SPARSEMEM_ENABLE
1318 select SPARSEMEM_VMEMMAP_ENABLE
1319 select SPARSEMEM_VMEMMAP
1321 config HW_PERF_EVENTS
1325 # Supported by clang >= 7.0 or GCC >= 12.0.0
1326 config CC_HAVE_SHADOW_CALL_STACK
1327 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1330 bool "Enable paravirtualization code"
1332 This changes the kernel so it can modify itself when it is run
1333 under a hypervisor, potentially improving performance significantly
1334 over full virtualization.
1336 config PARAVIRT_TIME_ACCOUNTING
1337 bool "Paravirtual steal time accounting"
1340 Select this option to enable fine granularity task steal time
1341 accounting. Time spent executing other tasks in parallel with
1342 the current vCPU is discounted from the vCPU power. To account for
1343 that, there can be a small performance impact.
1345 If in doubt, say N here.
1348 depends on PM_SLEEP_SMP
1350 bool "kexec system call"
1352 kexec is a system call that implements the ability to shutdown your
1353 current kernel, and to start another kernel. It is like a reboot
1354 but it is independent of the system firmware. And like a reboot
1355 you can start any kernel with it, not just Linux.
1358 bool "kexec file based system call"
1360 select HAVE_IMA_KEXEC if IMA
1362 This is new version of kexec system call. This system call is
1363 file based and takes file descriptors as system call argument
1364 for kernel and initramfs as opposed to list of segments as
1365 accepted by previous system call.
1368 bool "Verify kernel signature during kexec_file_load() syscall"
1369 depends on KEXEC_FILE
1371 Select this option to verify a signature with loaded kernel
1372 image. If configured, any attempt of loading a image without
1373 valid signature will fail.
1375 In addition to that option, you need to enable signature
1376 verification for the corresponding kernel image type being
1377 loaded in order for this to work.
1379 config KEXEC_IMAGE_VERIFY_SIG
1380 bool "Enable Image signature verification support"
1382 depends on KEXEC_SIG
1383 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1385 Enable Image signature verification support.
1387 comment "Support for PE file signature verification disabled"
1388 depends on KEXEC_SIG
1389 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1392 bool "Build kdump crash kernel"
1394 Generate crash dump after being started by kexec. This should
1395 be normally only set in special crash dump kernels which are
1396 loaded in the main kernel with kexec-tools into a specially
1397 reserved region and then later executed after a crash by
1400 For more details see Documentation/admin-guide/kdump/kdump.rst
1404 depends on HIBERNATION || KEXEC_CORE
1411 bool "Xen guest support on ARM64"
1412 depends on ARM64 && OF
1416 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1418 config FORCE_MAX_ZONEORDER
1420 default "14" if ARM64_64K_PAGES
1421 default "12" if ARM64_16K_PAGES
1424 The kernel memory allocator divides physically contiguous memory
1425 blocks into "zones", where each zone is a power of two number of
1426 pages. This option selects the largest power of two that the kernel
1427 keeps in the memory allocator. If you need to allocate very large
1428 blocks of physically contiguous memory, then you may need to
1429 increase this value.
1431 This config option is actually maximum order plus one. For example,
1432 a value of 11 means that the largest free memory block is 2^10 pages.
1434 We make sure that we can allocate upto a HugePage size for each configuration.
1436 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1438 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1439 4M allocations matching the default size used by generic code.
1441 config UNMAP_KERNEL_AT_EL0
1442 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1445 Speculation attacks against some high-performance processors can
1446 be used to bypass MMU permission checks and leak kernel data to
1447 userspace. This can be defended against by unmapping the kernel
1448 when running in userspace, mapping it back in on exception entry
1449 via a trampoline page in the vector table.
1453 config MITIGATE_SPECTRE_BRANCH_HISTORY
1454 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1457 Speculation attacks against some high-performance processors can
1458 make use of branch history to influence future speculation.
1459 When taking an exception from user-space, a sequence of branches
1460 or a firmware call overwrites the branch history.
1462 config RODATA_FULL_DEFAULT_ENABLED
1463 bool "Apply r/o permissions of VM areas also to their linear aliases"
1466 Apply read-only attributes of VM areas to the linear alias of
1467 the backing pages as well. This prevents code or read-only data
1468 from being modified (inadvertently or intentionally) via another
1469 mapping of the same memory page. This additional enhancement can
1470 be turned off at runtime by passing rodata=[off|on] (and turned on
1471 with rodata=full if this option is set to 'n')
1473 This requires the linear region to be mapped down to pages,
1474 which may adversely affect performance in some cases.
1476 config ARM64_SW_TTBR0_PAN
1477 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1479 Enabling this option prevents the kernel from accessing
1480 user-space memory directly by pointing TTBR0_EL1 to a reserved
1481 zeroed area and reserved ASID. The user access routines
1482 restore the valid TTBR0_EL1 temporarily.
1484 config ARM64_TAGGED_ADDR_ABI
1485 bool "Enable the tagged user addresses syscall ABI"
1488 When this option is enabled, user applications can opt in to a
1489 relaxed ABI via prctl() allowing tagged addresses to be passed
1490 to system calls as pointer arguments. For details, see
1491 Documentation/arm64/tagged-address-abi.rst.
1494 bool "Kernel support for 32-bit EL0"
1495 depends on ARM64_4K_PAGES || EXPERT
1497 select OLD_SIGSUSPEND3
1498 select COMPAT_OLD_SIGACTION
1500 This option enables support for a 32-bit EL0 running under a 64-bit
1501 kernel at EL1. AArch32-specific components such as system calls,
1502 the user helper functions, VFP support and the ptrace interface are
1503 handled appropriately by the kernel.
1505 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1506 that you will only be able to execute AArch32 binaries that were compiled
1507 with page size aligned segments.
1509 If you want to execute 32-bit userspace applications, say Y.
1513 config KUSER_HELPERS
1514 bool "Enable kuser helpers page for 32-bit applications"
1517 Warning: disabling this option may break 32-bit user programs.
1519 Provide kuser helpers to compat tasks. The kernel provides
1520 helper code to userspace in read only form at a fixed location
1521 to allow userspace to be independent of the CPU type fitted to
1522 the system. This permits binaries to be run on ARMv4 through
1523 to ARMv8 without modification.
1525 See Documentation/arm/kernel_user_helpers.rst for details.
1527 However, the fixed address nature of these helpers can be used
1528 by ROP (return orientated programming) authors when creating
1531 If all of the binaries and libraries which run on your platform
1532 are built specifically for your platform, and make no use of
1533 these helpers, then you can turn this option off to hinder
1534 such exploits. However, in that case, if a binary or library
1535 relying on those helpers is run, it will not function correctly.
1537 Say N here only if you are absolutely certain that you do not
1538 need these helpers; otherwise, the safe option is to say Y.
1541 bool "Enable vDSO for 32-bit applications"
1542 depends on !CPU_BIG_ENDIAN
1543 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1544 select GENERIC_COMPAT_VDSO
1547 Place in the process address space of 32-bit applications an
1548 ELF shared object providing fast implementations of gettimeofday
1551 You must have a 32-bit build of glibc 2.22 or later for programs
1552 to seamlessly take advantage of this.
1554 config THUMB2_COMPAT_VDSO
1555 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1556 depends on COMPAT_VDSO
1559 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1560 otherwise with '-marm'.
1562 menuconfig ARMV8_DEPRECATED
1563 bool "Emulate deprecated/obsolete ARMv8 instructions"
1566 Legacy software support may require certain instructions
1567 that have been deprecated or obsoleted in the architecture.
1569 Enable this config to enable selective emulation of these
1576 config SWP_EMULATION
1577 bool "Emulate SWP/SWPB instructions"
1579 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1580 they are always undefined. Say Y here to enable software
1581 emulation of these instructions for userspace using LDXR/STXR.
1582 This feature can be controlled at runtime with the abi.swp
1583 sysctl which is disabled by default.
1585 In some older versions of glibc [<=2.8] SWP is used during futex
1586 trylock() operations with the assumption that the code will not
1587 be preempted. This invalid assumption may be more likely to fail
1588 with SWP emulation enabled, leading to deadlock of the user
1591 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1592 on an external transaction monitoring block called a global
1593 monitor to maintain update atomicity. If your system does not
1594 implement a global monitor, this option can cause programs that
1595 perform SWP operations to uncached memory to deadlock.
1599 config CP15_BARRIER_EMULATION
1600 bool "Emulate CP15 Barrier instructions"
1602 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1603 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1604 strongly recommended to use the ISB, DSB, and DMB
1605 instructions instead.
1607 Say Y here to enable software emulation of these
1608 instructions for AArch32 userspace code. When this option is
1609 enabled, CP15 barrier usage is traced which can help
1610 identify software that needs updating. This feature can be
1611 controlled at runtime with the abi.cp15_barrier sysctl.
1615 config SETEND_EMULATION
1616 bool "Emulate SETEND instruction"
1618 The SETEND instruction alters the data-endianness of the
1619 AArch32 EL0, and is deprecated in ARMv8.
1621 Say Y here to enable software emulation of the instruction
1622 for AArch32 userspace code. This feature can be controlled
1623 at runtime with the abi.setend sysctl.
1625 Note: All the cpus on the system must have mixed endian support at EL0
1626 for this feature to be enabled. If a new CPU - which doesn't support mixed
1627 endian - is hotplugged in after this feature has been enabled, there could
1628 be unexpected results in the applications.
1631 endif # ARMV8_DEPRECATED
1635 menu "ARMv8.1 architectural features"
1637 config ARM64_HW_AFDBM
1638 bool "Support for hardware updates of the Access and Dirty page flags"
1641 The ARMv8.1 architecture extensions introduce support for
1642 hardware updates of the access and dirty information in page
1643 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1644 capable processors, accesses to pages with PTE_AF cleared will
1645 set this bit instead of raising an access flag fault.
1646 Similarly, writes to read-only pages with the DBM bit set will
1647 clear the read-only bit (AP[2]) instead of raising a
1650 Kernels built with this configuration option enabled continue
1651 to work on pre-ARMv8.1 hardware and the performance impact is
1652 minimal. If unsure, say Y.
1655 bool "Enable support for Privileged Access Never (PAN)"
1658 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1659 prevents the kernel or hypervisor from accessing user-space (EL0)
1662 Choosing this option will cause any unprotected (not using
1663 copy_to_user et al) memory access to fail with a permission fault.
1665 The feature is detected at runtime, and will remain as a 'nop'
1666 instruction if the cpu does not implement the feature.
1669 def_bool $(as-instr,.arch_extension rcpc)
1671 config AS_HAS_LSE_ATOMICS
1672 def_bool $(as-instr,.arch_extension lse)
1674 config ARM64_LSE_ATOMICS
1676 default ARM64_USE_LSE_ATOMICS
1677 depends on AS_HAS_LSE_ATOMICS
1679 config ARM64_USE_LSE_ATOMICS
1680 bool "Atomic instructions"
1681 depends on JUMP_LABEL
1684 As part of the Large System Extensions, ARMv8.1 introduces new
1685 atomic instructions that are designed specifically to scale in
1688 Say Y here to make use of these instructions for the in-kernel
1689 atomic routines. This incurs a small overhead on CPUs that do
1690 not support these instructions and requires the kernel to be
1691 built with binutils >= 2.25 in order for the new instructions
1694 endmenu # "ARMv8.1 architectural features"
1696 menu "ARMv8.2 architectural features"
1698 config AS_HAS_ARMV8_2
1699 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1702 def_bool $(as-instr,.arch armv8.2-a+sha3)
1705 bool "Enable support for persistent memory"
1706 select ARCH_HAS_PMEM_API
1707 select ARCH_HAS_UACCESS_FLUSHCACHE
1709 Say Y to enable support for the persistent memory API based on the
1710 ARMv8.2 DCPoP feature.
1712 The feature is detected at runtime, and the kernel will use DC CVAC
1713 operations if DC CVAP is not supported (following the behaviour of
1714 DC CVAP itself if the system does not define a point of persistence).
1716 config ARM64_RAS_EXTN
1717 bool "Enable support for RAS CPU Extensions"
1720 CPUs that support the Reliability, Availability and Serviceability
1721 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1722 errors, classify them and report them to software.
1724 On CPUs with these extensions system software can use additional
1725 barriers to determine if faults are pending and read the
1726 classification from a new set of registers.
1728 Selecting this feature will allow the kernel to use these barriers
1729 and access the new registers if the system supports the extension.
1730 Platform RAS features may additionally depend on firmware support.
1733 bool "Enable support for Common Not Private (CNP) translations"
1735 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1737 Common Not Private (CNP) allows translation table entries to
1738 be shared between different PEs in the same inner shareable
1739 domain, so the hardware can use this fact to optimise the
1740 caching of such entries in the TLB.
1742 Selecting this option allows the CNP feature to be detected
1743 at runtime, and does not affect PEs that do not implement
1746 endmenu # "ARMv8.2 architectural features"
1748 menu "ARMv8.3 architectural features"
1750 config ARM64_PTR_AUTH
1751 bool "Enable support for pointer authentication"
1754 Pointer authentication (part of the ARMv8.3 Extensions) provides
1755 instructions for signing and authenticating pointers against secret
1756 keys, which can be used to mitigate Return Oriented Programming (ROP)
1759 This option enables these instructions at EL0 (i.e. for userspace).
1760 Choosing this option will cause the kernel to initialise secret keys
1761 for each process at exec() time, with these keys being
1762 context-switched along with the process.
1764 The feature is detected at runtime. If the feature is not present in
1765 hardware it will not be advertised to userspace/KVM guest nor will it
1768 If the feature is present on the boot CPU but not on a late CPU, then
1769 the late CPU will be parked. Also, if the boot CPU does not have
1770 address auth and the late CPU has then the late CPU will still boot
1771 but with the feature disabled. On such a system, this option should
1774 config ARM64_PTR_AUTH_KERNEL
1775 bool "Use pointer authentication for kernel"
1777 depends on ARM64_PTR_AUTH
1778 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1779 # Modern compilers insert a .note.gnu.property section note for PAC
1780 # which is only understood by binutils starting with version 2.33.1.
1781 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1782 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1783 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1785 If the compiler supports the -mbranch-protection or
1786 -msign-return-address flag (e.g. GCC 7 or later), then this option
1787 will cause the kernel itself to be compiled with return address
1788 protection. In this case, and if the target hardware is known to
1789 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1790 disabled with minimal loss of protection.
1792 This feature works with FUNCTION_GRAPH_TRACER option only if
1793 DYNAMIC_FTRACE_WITH_REGS is enabled.
1795 config CC_HAS_BRANCH_PROT_PAC_RET
1796 # GCC 9 or later, clang 8 or later
1797 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1799 config CC_HAS_SIGN_RETURN_ADDRESS
1801 def_bool $(cc-option,-msign-return-address=all)
1804 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1806 config AS_HAS_CFI_NEGATE_RA_STATE
1807 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1809 endmenu # "ARMv8.3 architectural features"
1811 menu "ARMv8.4 architectural features"
1813 config ARM64_AMU_EXTN
1814 bool "Enable support for the Activity Monitors Unit CPU extension"
1817 The activity monitors extension is an optional extension introduced
1818 by the ARMv8.4 CPU architecture. This enables support for version 1
1819 of the activity monitors architecture, AMUv1.
1821 To enable the use of this extension on CPUs that implement it, say Y.
1823 Note that for architectural reasons, firmware _must_ implement AMU
1824 support when running on CPUs that present the activity monitors
1825 extension. The required support is present in:
1826 * Version 1.5 and later of the ARM Trusted Firmware
1828 For kernels that have this configuration enabled but boot with broken
1829 firmware, you may need to say N here until the firmware is fixed.
1830 Otherwise you may experience firmware panics or lockups when
1831 accessing the counter registers. Even if you are not observing these
1832 symptoms, the values returned by the register reads might not
1833 correctly reflect reality. Most commonly, the value read will be 0,
1834 indicating that the counter is not enabled.
1836 config AS_HAS_ARMV8_4
1837 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1839 config ARM64_TLB_RANGE
1840 bool "Enable support for tlbi range feature"
1842 depends on AS_HAS_ARMV8_4
1844 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1845 range of input addresses.
1847 The feature introduces new assembly instructions, and they were
1848 support when binutils >= 2.30.
1850 endmenu # "ARMv8.4 architectural features"
1852 menu "ARMv8.5 architectural features"
1854 config AS_HAS_ARMV8_5
1855 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1858 bool "Branch Target Identification support"
1861 Branch Target Identification (part of the ARMv8.5 Extensions)
1862 provides a mechanism to limit the set of locations to which computed
1863 branch instructions such as BR or BLR can jump.
1865 To make use of BTI on CPUs that support it, say Y.
1867 BTI is intended to provide complementary protection to other control
1868 flow integrity protection mechanisms, such as the Pointer
1869 authentication mechanism provided as part of the ARMv8.3 Extensions.
1870 For this reason, it does not make sense to enable this option without
1871 also enabling support for pointer authentication. Thus, when
1872 enabling this option you should also select ARM64_PTR_AUTH=y.
1874 Userspace binaries must also be specifically compiled to make use of
1875 this mechanism. If you say N here or the hardware does not support
1876 BTI, such binaries can still run, but you get no additional
1877 enforcement of branch destinations.
1879 config ARM64_BTI_KERNEL
1880 bool "Use Branch Target Identification for kernel"
1882 depends on ARM64_BTI
1883 depends on ARM64_PTR_AUTH_KERNEL
1884 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1885 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1886 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1887 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1888 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1889 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1891 Build the kernel with Branch Target Identification annotations
1892 and enable enforcement of this for kernel code. When this option
1893 is enabled and the system supports BTI all kernel code including
1894 modular code must have BTI enabled.
1896 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1897 # GCC 9 or later, clang 8 or later
1898 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1901 bool "Enable support for E0PD"
1904 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1905 that EL0 accesses made via TTBR1 always fault in constant time,
1906 providing similar benefits to KASLR as those provided by KPTI, but
1907 with lower overhead and without disrupting legitimate access to
1908 kernel memory such as SPE.
1910 This option enables E0PD for TTBR1 where available.
1913 bool "Enable support for random number generation"
1916 Random number generation (part of the ARMv8.5 Extensions)
1917 provides a high bandwidth, cryptographically secure
1918 hardware random number generator.
1920 config ARM64_AS_HAS_MTE
1921 # Initial support for MTE went in binutils 2.32.0, checked with
1922 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1923 # as a late addition to the final architecture spec (LDGM/STGM)
1924 # is only supported in the newer 2.32.x and 2.33 binutils
1925 # versions, hence the extra "stgm" instruction check below.
1926 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1929 bool "Memory Tagging Extension support"
1931 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1932 depends on AS_HAS_ARMV8_5
1933 depends on AS_HAS_LSE_ATOMICS
1934 # Required for tag checking in the uaccess routines
1935 depends on ARM64_PAN
1936 select ARCH_HAS_SUBPAGE_FAULTS
1937 select ARCH_USES_HIGH_VMA_FLAGS
1939 Memory Tagging (part of the ARMv8.5 Extensions) provides
1940 architectural support for run-time, always-on detection of
1941 various classes of memory error to aid with software debugging
1942 to eliminate vulnerabilities arising from memory-unsafe
1945 This option enables the support for the Memory Tagging
1946 Extension at EL0 (i.e. for userspace).
1948 Selecting this option allows the feature to be detected at
1949 runtime. Any secondary CPU not implementing this feature will
1950 not be allowed a late bring-up.
1952 Userspace binaries that want to use this feature must
1953 explicitly opt in. The mechanism for the userspace is
1956 Documentation/arm64/memory-tagging-extension.rst.
1958 endmenu # "ARMv8.5 architectural features"
1960 menu "ARMv8.7 architectural features"
1963 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1965 depends on ARM64_PAN
1967 Enhanced Privileged Access Never (EPAN) allows Privileged
1968 Access Never to be used with Execute-only mappings.
1970 The feature is detected at runtime, and will remain disabled
1971 if the cpu does not implement the feature.
1972 endmenu # "ARMv8.7 architectural features"
1975 bool "ARM Scalable Vector Extension support"
1978 The Scalable Vector Extension (SVE) is an extension to the AArch64
1979 execution state which complements and extends the SIMD functionality
1980 of the base architecture to support much larger vectors and to enable
1981 additional vectorisation opportunities.
1983 To enable use of this extension on CPUs that implement it, say Y.
1985 On CPUs that support the SVE2 extensions, this option will enable
1988 Note that for architectural reasons, firmware _must_ implement SVE
1989 support when running on SVE capable hardware. The required support
1992 * version 1.5 and later of the ARM Trusted Firmware
1993 * the AArch64 boot wrapper since commit 5e1261e08abf
1994 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1996 For other firmware implementations, consult the firmware documentation
1999 If you need the kernel to boot on SVE-capable hardware with broken
2000 firmware, you may need to say N here until you get your firmware
2001 fixed. Otherwise, you may experience firmware panics or lockups when
2002 booting the kernel. If unsure and you are not observing these
2003 symptoms, you should assume that it is safe to say Y.
2006 bool "ARM Scalable Matrix Extension support"
2008 depends on ARM64_SVE
2010 The Scalable Matrix Extension (SME) is an extension to the AArch64
2011 execution state which utilises a substantial subset of the SVE
2012 instruction set, together with the addition of new architectural
2013 register state capable of holding two dimensional matrix tiles to
2014 enable various matrix operations.
2016 config ARM64_MODULE_PLTS
2017 bool "Use PLTs to allow module memory to spill over into vmalloc area"
2019 select HAVE_MOD_ARCH_SPECIFIC
2021 Allocate PLTs when loading modules so that jumps and calls whose
2022 targets are too far away for their relative offsets to be encoded
2023 in the instructions themselves can be bounced via veneers in the
2024 module's PLT. This allows modules to be allocated in the generic
2025 vmalloc area after the dedicated module memory area has been
2028 When running with address space randomization (KASLR), the module
2029 region itself may be too far away for ordinary relative jumps and
2030 calls, and so in that case, module PLTs are required and cannot be
2033 Specific errata workaround(s) might also force module PLTs to be
2034 enabled (ARM64_ERRATUM_843419).
2036 config ARM64_PSEUDO_NMI
2037 bool "Support for NMI-like interrupts"
2040 Adds support for mimicking Non-Maskable Interrupts through the use of
2041 GIC interrupt priority. This support requires version 3 or later of
2044 This high priority configuration for interrupts needs to be
2045 explicitly enabled by setting the kernel parameter
2046 "irqchip.gicv3_pseudo_nmi" to 1.
2051 config ARM64_DEBUG_PRIORITY_MASKING
2052 bool "Debug interrupt priority masking"
2054 This adds runtime checks to functions enabling/disabling
2055 interrupts when using priority masking. The additional checks verify
2056 the validity of ICC_PMR_EL1 when calling concerned functions.
2059 endif # ARM64_PSEUDO_NMI
2062 bool "Build a relocatable kernel image" if EXPERT
2063 select ARCH_HAS_RELR
2066 This builds the kernel as a Position Independent Executable (PIE),
2067 which retains all relocation metadata required to relocate the
2068 kernel binary at runtime to a different virtual address than the
2069 address it was linked at.
2070 Since AArch64 uses the RELA relocation format, this requires a
2071 relocation pass at runtime even if the kernel is loaded at the
2072 same address it was linked at.
2074 config RANDOMIZE_BASE
2075 bool "Randomize the address of the kernel image"
2076 select ARM64_MODULE_PLTS if MODULES
2079 Randomizes the virtual address at which the kernel image is
2080 loaded, as a security feature that deters exploit attempts
2081 relying on knowledge of the location of kernel internals.
2083 It is the bootloader's job to provide entropy, by passing a
2084 random u64 value in /chosen/kaslr-seed at kernel entry.
2086 When booting via the UEFI stub, it will invoke the firmware's
2087 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2088 to the kernel proper. In addition, it will randomise the physical
2089 location of the kernel Image as well.
2093 config RANDOMIZE_MODULE_REGION_FULL
2094 bool "Randomize the module region over a 2 GB range"
2095 depends on RANDOMIZE_BASE
2098 Randomizes the location of the module region inside a 2 GB window
2099 covering the core kernel. This way, it is less likely for modules
2100 to leak information about the location of core kernel data structures
2101 but it does imply that function calls between modules and the core
2102 kernel will need to be resolved via veneers in the module PLT.
2104 When this option is not set, the module region will be randomized over
2105 a limited range that contains the [_stext, _etext] interval of the
2106 core kernel, so branch relocations are almost always in range unless
2107 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
2108 particular case of region exhaustion, modules might be able to fall
2109 back to a larger 2GB area.
2111 config CC_HAVE_STACKPROTECTOR_SYSREG
2112 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2114 config STACKPROTECTOR_PER_TASK
2116 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2118 # The GPIO number here must be sorted by descending number. In case of
2119 # a multiplatform kernel, we just want the highest value required by the
2120 # selected platforms.
2123 default 2048 if ARCH_APPLE
2126 Maximum number of GPIOs in the system.
2128 If unsure, leave the default value.
2130 endmenu # "Kernel Features"
2134 config ARM64_ACPI_PARKING_PROTOCOL
2135 bool "Enable support for the ARM64 ACPI parking protocol"
2138 Enable support for the ARM64 ACPI parking protocol. If disabled
2139 the kernel will not allow booting through the ARM64 ACPI parking
2140 protocol even if the corresponding data is present in the ACPI
2144 string "Default kernel command string"
2147 Provide a set of default command-line options at build time by
2148 entering them here. As a minimum, you should specify the the
2149 root device (e.g. root=/dev/nfs).
2152 prompt "Kernel command line type" if CMDLINE != ""
2153 default CMDLINE_FROM_BOOTLOADER
2155 Choose how the kernel will handle the provided default kernel
2156 command line string.
2158 config CMDLINE_FROM_BOOTLOADER
2159 bool "Use bootloader kernel arguments if available"
2161 Uses the command-line options passed by the boot loader. If
2162 the boot loader doesn't provide any, the default kernel command
2163 string provided in CMDLINE will be used.
2165 config CMDLINE_FORCE
2166 bool "Always use the default kernel command string"
2168 Always use the default kernel command string, even if the boot
2169 loader passes other arguments to the kernel.
2170 This is useful if you cannot or don't want to change the
2171 command-line options your boot loader passes to the kernel.
2179 bool "UEFI runtime support"
2180 depends on OF && !CPU_BIG_ENDIAN
2181 depends on KERNEL_MODE_NEON
2182 select ARCH_SUPPORTS_ACPI
2185 select EFI_PARAMS_FROM_FDT
2186 select EFI_RUNTIME_WRAPPERS
2188 select EFI_GENERIC_STUB
2189 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2192 This option provides support for runtime services provided
2193 by UEFI firmware (such as non-volatile variables, realtime
2194 clock, and platform reset). A UEFI stub is also provided to
2195 allow the kernel to be booted as an EFI application. This
2196 is only useful on systems that have UEFI firmware.
2199 bool "Enable support for SMBIOS (DMI) tables"
2203 This enables SMBIOS/DMI feature for systems.
2205 This option is only useful on systems that have UEFI firmware.
2206 However, even with this option, the resultant kernel should
2207 continue to boot on existing non-UEFI platforms.
2209 endmenu # "Boot options"
2211 menu "Power management options"
2213 source "kernel/power/Kconfig"
2215 config ARCH_HIBERNATION_POSSIBLE
2219 config ARCH_HIBERNATION_HEADER
2221 depends on HIBERNATION
2223 config ARCH_SUSPEND_POSSIBLE
2226 endmenu # "Power management options"
2228 menu "CPU Power Management"
2230 source "drivers/cpuidle/Kconfig"
2232 source "drivers/cpufreq/Kconfig"
2234 endmenu # "CPU Power Management"
2236 source "drivers/acpi/Kconfig"
2238 source "arch/arm64/kvm/Kconfig"
2241 source "arch/arm64/crypto/Kconfig"