git.itanic.dy.fi Git - linux-stable/blob - arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  * Copyright 2019-2020 Variscite Ltd.
   5  * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
   6  */
   7
   8 #include "imx8mn.dtsi"
   9
  10 / {
  11         model = "Variscite VAR-SOM-MX8MN module";
  12         compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
  13
  14         chosen {
  15                 stdout-path = &uart4;
  16         };
  17
  18         memory@40000000 {
  19                 device_type = "memory";
  20                 reg = <0x0 0x40000000 0 0x40000000>;
  21         };
  22
  23         reg_eth_phy: regulator-eth-phy {
  24                 compatible = "regulator-fixed";
  25                 pinctrl-names = "default";
  26                 pinctrl-0 = <&pinctrl_reg_eth_phy>;
  27                 regulator-name = "eth_phy_pwr";
  28                 regulator-min-microvolt = <3300000>;
  29                 regulator-max-microvolt = <3300000>;
  30                 gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
  31                 enable-active-high;
  32         };
  33 };
  34
  35 &A53_0 {
  36         cpu-supply = <&buck2_reg>;
  37 };
  38
  39 &A53_1 {
  40         cpu-supply = <&buck2_reg>;
  41 };
  42
  43 &A53_2 {
  44         cpu-supply = <&buck2_reg>;
  45 };
  46
  47 &A53_3 {
  48         cpu-supply = <&buck2_reg>;
  49 };
  50
  51 &ecspi1 {
  52         pinctrl-names = "default";
  53         pinctrl-0 = <&pinctrl_ecspi1>;
  54         cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
  55                    <&gpio1  0 GPIO_ACTIVE_LOW>;
  56         /delete-property/ dmas;
  57         /delete-property/ dma-names;
  58         status = "okay";
  59
  60         /* Resistive touch controller */
  61         touchscreen@0 {
  62                 reg = <0>;
  63                 compatible = "ti,ads7846";
  64                 pinctrl-names = "default";
  65                 pinctrl-0 = <&pinctrl_restouch>;
  66                 interrupt-parent = <&gpio1>;
  67                 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
  68
  69                 spi-max-frequency = <1500000>;
  70                 pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
  71
  72                 ti,x-min = /bits/ 16 <125>;
  73                 touchscreen-size-x = <4008>;
  74                 ti,y-min = /bits/ 16 <282>;
  75                 touchscreen-size-y = <3864>;
  76                 ti,x-plate-ohms = /bits/ 16 <180>;
  77                 touchscreen-max-pressure = <255>;
  78                 touchscreen-average-samples = <10>;
  79                 ti,debounce-tol = /bits/ 16 <3>;
  80                 ti,debounce-rep = /bits/ 16 <1>;
  81                 ti,settle-delay-usec = /bits/ 16 <150>;
  82                 ti,keep-vref-on;
  83                 wakeup-source;
  84         };
  85 };
  86
  87 &fec1 {
  88         pinctrl-names = "default", "sleep";
  89         pinctrl-0 = <&pinctrl_fec1>;
  90         pinctrl-1 = <&pinctrl_fec1_sleep>;
  91         phy-mode = "rgmii";
  92         phy-handle = <&ethphy>;
  93         phy-supply = <&reg_eth_phy>;
  94         fsl,magic-packet;
  95         status = "okay";
  96
  97         mdio {
  98                 #address-cells = <1>;
  99                 #size-cells = <0>;
 100
 101                 ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */
 102                         compatible = "ethernet-phy-ieee802.3-c22";
 103                         reg = <4>;
 104                         reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
 105                         reset-assert-us = <10000>;
 106                         /*
 107                          * Deassert delay:
 108                          * ADIN1300 requires 5ms.
 109                          * AR8033   requires 1ms.
 110                          */
 111                         reset-deassert-us = <20000>;
 112                 };
 113         };
 114 };
 115
 116 &i2c1 {
 117         clock-frequency = <400000>;
 118         pinctrl-names = "default";
 119         pinctrl-0 = <&pinctrl_i2c1>;
 120         status = "okay";
 121
 122         pmic@4b {
 123                 compatible = "rohm,bd71847";
 124                 reg = <0x4b>;
 125                 pinctrl-names = "default";
 126                 pinctrl-0 = <&pinctrl_pmic>;
 127                 interrupt-parent = <&gpio2>;
 128                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
 129                 rohm,reset-snvs-powered;
 130
 131                 regulators {
 132                         buck1_reg: BUCK1 {
 133                                 regulator-name = "buck1";
 134                                 regulator-min-microvolt = <700000>;
 135                                 regulator-max-microvolt = <1300000>;
 136                                 regulator-boot-on;
 137                                 regulator-always-on;
 138                                 regulator-ramp-delay = <1250>;
 139                         };
 140
 141                         buck2_reg: BUCK2 {
 142                                 regulator-name = "buck2";
 143                                 regulator-min-microvolt = <700000>;
 144                                 regulator-max-microvolt = <1300000>;
 145                                 regulator-boot-on;
 146                                 regulator-always-on;
 147                                 regulator-ramp-delay = <1250>;
 148                                 rohm,dvs-run-voltage = <1000000>;
 149                                 rohm,dvs-idle-voltage = <900000>;
 150                         };
 151
 152                         buck3_reg: BUCK3 {
 153                                 regulator-name = "buck3";
 154                                 regulator-min-microvolt = <700000>;
 155                                 regulator-max-microvolt = <1350000>;
 156                                 regulator-boot-on;
 157                                 regulator-always-on;
 158                         };
 159
 160                         buck4_reg: BUCK4 {
 161                                 regulator-name = "buck4";
 162                                 regulator-min-microvolt = <2600000>;
 163                                 regulator-max-microvolt = <3300000>;
 164                                 regulator-boot-on;
 165                                 regulator-always-on;
 166                         };
 167
 168                         buck5_reg: BUCK5 {
 169                                 regulator-name = "buck5";
 170                                 regulator-min-microvolt = <1605000>;
 171                                 regulator-max-microvolt = <1995000>;
 172                                 regulator-boot-on;
 173                                 regulator-always-on;
 174                         };
 175
 176                         buck6_reg: BUCK6 {
 177                                 regulator-name = "buck6";
 178                                 regulator-min-microvolt = <800000>;
 179                                 regulator-max-microvolt = <1400000>;
 180                                 regulator-boot-on;
 181                                 regulator-always-on;
 182                         };
 183
 184                         ldo1_reg: LDO1 {
 185                                 regulator-name = "ldo1";
 186                                 regulator-min-microvolt = <1600000>;
 187                                 regulator-max-microvolt = <1900000>;
 188                                 regulator-boot-on;
 189                                 regulator-always-on;
 190                         };
 191
 192                         ldo2_reg: LDO2 {
 193                                 regulator-name = "ldo2";
 194                                 regulator-min-microvolt = <800000>;
 195                                 regulator-max-microvolt = <900000>;
 196                                 regulator-boot-on;
 197                                 regulator-always-on;
 198                         };
 199
 200                         ldo3_reg: LDO3 {
 201                                 regulator-name = "ldo3";
 202                                 regulator-min-microvolt = <1800000>;
 203                                 regulator-max-microvolt = <3300000>;
 204                                 regulator-boot-on;
 205                                 regulator-always-on;
 206                         };
 207
 208                         ldo4_reg: LDO4 {
 209                                 regulator-name = "ldo4";
 210                                 regulator-min-microvolt = <900000>;
 211                                 regulator-max-microvolt = <1800000>;
 212                                 regulator-always-on;
 213                         };
 214
 215                         ldo5_reg: LDO5 {
 216                                 regulator-name = "ldo5";
 217                                 regulator-min-microvolt = <1800000>;
 218                                 regulator-max-microvolt = <1800000>;
 219                                 regulator-always-on;
 220                         };
 221
 222                         ldo6_reg: LDO6 {
 223                                 regulator-name = "ldo6";
 224                                 regulator-min-microvolt = <900000>;
 225                                 regulator-max-microvolt = <1800000>;
 226                                 regulator-boot-on;
 227                                 regulator-always-on;
 228                         };
 229                 };
 230         };
 231 };
 232
 233 &i2c3 {
 234         clock-frequency = <400000>;
 235         pinctrl-names = "default";
 236         pinctrl-0 = <&pinctrl_i2c3>;
 237         status = "okay";
 238
 239         /* TODO: configure audio, as of now just put a placeholder */
 240         wm8904: codec@1a {
 241                 compatible = "wlf,wm8904";
 242                 reg = <0x1a>;
 243                 status = "disabled";
 244         };
 245 };
 246
 247 &snvs_pwrkey {
 248         status = "okay";
 249 };
 250
 251 /* Bluetooth */
 252 &uart2 {
 253         pinctrl-names = "default";
 254         pinctrl-0 = <&pinctrl_uart2>;
 255         assigned-clocks = <&clk IMX8MN_CLK_UART2>;
 256         assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
 257         uart-has-rtscts;
 258         status = "okay";
 259 };
 260
 261 /* Console */
 262 &uart4 {
 263         pinctrl-names = "default";
 264         pinctrl-0 = <&pinctrl_uart4>;
 265         status = "okay";
 266 };
 267
 268 &usbotg1 {
 269         dr_mode = "otg";
 270         usb-role-switch;
 271         status = "okay";
 272 };
 273
 274 /* WIFI */
 275 &usdhc1 {
 276         #address-cells = <1>;
 277         #size-cells = <0>;
 278         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 279         pinctrl-0 = <&pinctrl_usdhc1>;
 280         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 281         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 282         bus-width = <4>;
 283         non-removable;
 284         keep-power-in-suspend;
 285         status = "okay";
 286
 287         brcmf: bcrmf@1 {
 288                 reg = <1>;
 289                 compatible = "brcm,bcm4329-fmac";
 290         };
 291 };
 292
 293 /* SD */
 294 &usdhc2 {
 295         assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
 296         assigned-clock-rates = <200000000>;
 297         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 298         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 299         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 300         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 301         cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
 302         bus-width = <4>;
 303         vmmc-supply = <&reg_usdhc2_vmmc>;
 304         status = "okay";
 305 };
 306
 307 /* eMMC */
 308 &usdhc3 {
 309         assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
 310         assigned-clock-rates = <400000000>;
 311         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 312         pinctrl-0 = <&pinctrl_usdhc3>;
 313         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 314         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 315         bus-width = <8>;
 316         non-removable;
 317         status = "okay";
 318 };
 319
 320 &wdog1 {
 321         pinctrl-names = "default";
 322         pinctrl-0 = <&pinctrl_wdog>;
 323         fsl,ext-reset-output;
 324         status = "okay";
 325 };
 326
 327 &iomuxc {
 328         pinctrl_ecspi1: ecspi1grp {
 329                 fsl,pins = <
 330                         MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK            0x13
 331                         MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI            0x13
 332                         MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO            0x13
 333                         MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14              0x13
 334                         MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0               0x13
 335                 >;
 336         };
 337
 338         pinctrl_fec1: fec1grp {
 339                 fsl,pins = <
 340                         MX8MN_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 341                         MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO               0x3
 342                         MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
 343                         MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
 344                         MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 345                         MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 346                         MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
 347                         MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
 348                         MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 349                         MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 350                         MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
 351                         MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
 352                         MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 353                         MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 354                         MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9               0x19
 355                 >;
 356         };
 357
 358         pinctrl_fec1_sleep: fec1sleepgrp {
 359                 fsl,pins = <
 360                         MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16                0x120
 361                         MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17               0x120
 362                         MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18                0x120
 363                         MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19                0x120
 364                         MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20                0x120
 365                         MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21                0x120
 366                         MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29                0x120
 367                         MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28                0x120
 368                         MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27                0x120
 369                         MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26                0x120
 370                         MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23                0x120
 371                         MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25                0x120
 372                         MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24             0x120
 373                         MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22             0x120
 374                         MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9               0x120
 375                 >;
 376         };
 377
 378         pinctrl_i2c1: i2c1grp {
 379                 fsl,pins = <
 380                         MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
 381                         MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
 382                 >;
 383         };
 384
 385         pinctrl_i2c3: i2c3grp {
 386                 fsl,pins = <
 387                         MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
 388                         MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
 389                 >;
 390         };
 391
 392         pinctrl_pmic: pmicirqgrp {
 393                 fsl,pins = <
 394                         MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8        0x141
 395                 >;
 396         };
 397
 398         pinctrl_reg_eth_phy: regethphygrp {
 399                 fsl,pins = <
 400                         MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9        0x41
 401                 >;
 402         };
 403
 404         pinctrl_restouch: restouchgrp {
 405                 fsl,pins = <
 406                         MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3       0x1c0
 407                 >;
 408         };
 409
 410         pinctrl_uart2: uart2grp {
 411                 fsl,pins = <
 412                         MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX     0x140
 413                         MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX      0x140
 414                         MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B   0x140
 415                         MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B   0x140
 416                 >;
 417         };
 418
 419         pinctrl_uart4: uart4grp {
 420                 fsl,pins = <
 421                         MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX     0x140
 422                         MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX     0x140
 423                 >;
 424         };
 425
 426         pinctrl_usdhc1: usdhc1grp {
 427                 fsl,pins = <
 428                         MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK         0x190
 429                         MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d0
 430                         MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d0
 431                         MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d0
 432                         MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d0
 433                         MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d0
 434                 >;
 435         };
 436
 437         pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
 438                 fsl,pins = <
 439                         MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK         0x194
 440                         MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d4
 441                         MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d4
 442                         MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d4
 443                         MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d4
 444                         MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d4
 445                 >;
 446         };
 447
 448         pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
 449                 fsl,pins = <
 450                         MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK         0x196
 451                         MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d6
 452                         MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d6
 453                         MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d6
 454                         MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d6
 455                         MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d6
 456                 >;
 457         };
 458
 459         pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 460                 fsl,pins = <
 461                         MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10      0x41
 462                 >;
 463         };
 464
 465         pinctrl_usdhc2: usdhc2grp {
 466                 fsl,pins = <
 467                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
 468                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
 469                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
 470                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
 471                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
 472                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
 473                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 474                 >;
 475         };
 476
 477         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 478                 fsl,pins = <
 479                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
 480                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
 481                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
 482                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
 483                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
 484                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
 485                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 486                 >;
 487         };
 488
 489         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 490                 fsl,pins = <
 491                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
 492                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
 493                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
 494                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
 495                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
 496                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
 497                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 498                 >;
 499         };
 500
 501         pinctrl_usdhc3: usdhc3grp {
 502                 fsl,pins = <
 503                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK       0x190
 504                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d0
 505                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d0
 506                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d0
 507                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d0
 508                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d0
 509                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d0
 510                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d0
 511                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d0
 512                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d0
 513                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x190
 514                 >;
 515         };
 516
 517         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 518                 fsl,pins = <
 519                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK       0x194
 520                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d4
 521                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d4
 522                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d4
 523                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d4
 524                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d4
 525                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d4
 526                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d4
 527                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d4
 528                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d4
 529                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x194
 530                 >;
 531         };
 532
 533         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 534                 fsl,pins = <
 535                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK       0x196
 536                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d6
 537                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d6
 538                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d6
 539                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d6
 540                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d6
 541                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d6
 542                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d6
 543                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d6
 544                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d6
 545                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x196
 546                 >;
 547         };
 548
 549         pinctrl_wdog: wdoggrp {
 550                 fsl,pins = <
 551                         MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B    0x166
 552                 >;
 553         };
 554 };