1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright(c) 2020-2021 Intel Corporation. */
5 #include <uapi/linux/cxl_mem.h>
6 #include <linux/cdev.h>
7 #include <linux/uuid.h>
8 #include <linux/rcuwait.h>
11 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */
12 #define CXLMDEV_STATUS_OFFSET 0x0
13 #define CXLMDEV_DEV_FATAL BIT(0)
14 #define CXLMDEV_FW_HALT BIT(1)
15 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2)
16 #define CXLMDEV_MS_NOT_READY 0
17 #define CXLMDEV_MS_READY 1
18 #define CXLMDEV_MS_ERROR 2
19 #define CXLMDEV_MS_DISABLED 3
20 #define CXLMDEV_READY(status) \
21 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \
23 #define CXLMDEV_MBOX_IF_READY BIT(4)
24 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5)
25 #define CXLMDEV_RESET_NEEDED_NOT 0
26 #define CXLMDEV_RESET_NEEDED_COLD 1
27 #define CXLMDEV_RESET_NEEDED_WARM 2
28 #define CXLMDEV_RESET_NEEDED_HOT 3
29 #define CXLMDEV_RESET_NEEDED_CXL 4
30 #define CXLMDEV_RESET_NEEDED(status) \
31 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \
32 CXLMDEV_RESET_NEEDED_NOT)
35 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device
36 * @dev: driver core device object
37 * @cdev: char dev core object for ioctl operations
38 * @cxlds: The device state backing this device
39 * @detach_work: active memdev lost a port in its ancestry
40 * @cxl_nvb: coordinate removal of @cxl_nvd if present
41 * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem
42 * @endpoint: connection to the CXL port topology for this memory device
43 * @id: id number of this memdev instance.
44 * @depth: endpoint port depth
49 struct cxl_dev_state *cxlds;
50 struct work_struct detach_work;
51 struct cxl_nvdimm_bridge *cxl_nvb;
52 struct cxl_nvdimm *cxl_nvd;
53 struct cxl_port *endpoint;
58 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev)
60 return container_of(dev, struct cxl_memdev, dev);
63 static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled)
65 return to_cxl_port(cxled->cxld.dev.parent);
68 static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd)
70 return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent);
73 static inline struct cxl_memdev *
74 cxled_to_memdev(struct cxl_endpoint_decoder *cxled)
76 struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent);
78 return to_cxl_memdev(port->uport_dev);
81 bool is_cxl_memdev(const struct device *dev);
82 static inline bool is_cxl_endpoint(struct cxl_port *port)
84 return is_cxl_memdev(port->uport_dev);
87 struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds);
88 struct cxl_memdev_state;
89 int cxl_memdev_setup_fw_upload(struct cxl_memdev_state *mds);
90 int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled,
91 resource_size_t base, resource_size_t len,
92 resource_size_t skipped);
94 static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port,
95 struct cxl_memdev *cxlmd)
100 return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev);
104 * struct cxl_mbox_cmd - A command to be submitted to hardware.
105 * @opcode: (input) The command set and command submitted to hardware.
106 * @payload_in: (input) Pointer to the input payload.
107 * @payload_out: (output) Pointer to the output payload. Must be allocated by
109 * @size_in: (input) Number of bytes to load from @payload_in.
110 * @size_out: (input) Max number of bytes loaded into @payload_out.
111 * (output) Number of bytes generated by the device. For fixed size
112 * outputs commands this is always expected to be deterministic. For
113 * variable sized output commands, it tells the exact number of bytes
115 * @min_out: (input) internal command output payload size validation
116 * @poll_count: (input) Number of timeouts to attempt.
117 * @poll_interval_ms: (input) Time between mailbox background command polling
119 * @return_code: (output) Error code returned from hardware.
121 * This is the primary mechanism used to send commands to the hardware.
122 * All the fields except @payload_* correspond exactly to the fields described in
123 * Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and
124 * @payload_out are written to, and read from the Command Payload Registers
125 * defined in CXL 2.0 8.2.8.4.8.
127 struct cxl_mbox_cmd {
135 int poll_interval_ms;
140 * Per CXL 3.0 Section 8.2.8.4.5.1
142 #define CMD_CMD_RC_TABLE \
143 C(SUCCESS, 0, NULL), \
144 C(BACKGROUND, -ENXIO, "background cmd started successfully"), \
145 C(INPUT, -ENXIO, "cmd input was invalid"), \
146 C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \
147 C(INTERNAL, -ENXIO, "internal device error"), \
148 C(RETRY, -ENXIO, "temporary error, retry once"), \
149 C(BUSY, -ENXIO, "ongoing background operation"), \
150 C(MEDIADISABLED, -ENXIO, "media access is disabled"), \
151 C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \
152 C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \
153 C(FWAUTH, -ENXIO, "FW package authentication failed"), \
154 C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \
155 C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \
156 C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \
157 C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \
158 C(PADDR, -EFAULT, "physical address specified is invalid"), \
159 C(POISONLMT, -ENXIO, "poison injection limit has been reached"), \
160 C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \
161 C(ABORT, -ENXIO, "background cmd was aborted by device"), \
162 C(SECURITY, -ENXIO, "not valid in the current security state"), \
163 C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \
164 C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\
165 C(PAYLOADLEN, -ENXIO, "invalid payload length"), \
166 C(LOG, -ENXIO, "invalid or unsupported log page"), \
167 C(INTERRUPTED, -ENXIO, "asynchronous event occured"), \
168 C(FEATUREVERSION, -ENXIO, "unsupported feature version"), \
169 C(FEATURESELVALUE, -ENXIO, "unsupported feature selection value"), \
170 C(FEATURETRANSFERIP, -ENXIO, "feature transfer in progress"), \
171 C(FEATURETRANSFEROOO, -ENXIO, "feature transfer out of order"), \
172 C(RESOURCEEXHAUSTED, -ENXIO, "resources are exhausted"), \
173 C(EXTLIST, -ENXIO, "invalid Extent List"), \
176 #define C(a, b, c) CXL_MBOX_CMD_RC_##a
177 enum { CMD_CMD_RC_TABLE };
179 #define C(a, b, c) { b, c }
180 struct cxl_mbox_cmd_rc {
186 struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE };
189 static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd)
191 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc;
194 static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd)
196 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err;
200 * CXL 2.0 - Memory capacity multiplier
201 * See Section 8.2.9.5
203 * Volatile, Persistent, and Partition capacities are specified to be in
204 * multiples of 256MB - define a multiplier to convert to/from bytes.
206 #define CXL_CAPACITY_MULTIPLIER SZ_256M
209 * Event Interrupt Policy
211 * CXL rev 3.0 section 8.2.9.2.4; Table 8-52
213 enum cxl_event_int_mode {
215 CXL_INT_MSI_MSIX = 0x01,
218 struct cxl_event_interrupt_policy {
226 * struct cxl_event_state - Event log driver state
228 * @buf: Buffer to receive event data
229 * @log_lock: Serialize event_buf and log use
231 struct cxl_event_state {
232 struct cxl_get_event_payload *buf;
233 struct mutex log_lock;
236 /* Device enabled poison commands */
237 enum poison_cmd_enabled_bits {
238 CXL_POISON_ENABLED_LIST,
239 CXL_POISON_ENABLED_INJECT,
240 CXL_POISON_ENABLED_CLEAR,
241 CXL_POISON_ENABLED_SCAN_CAPS,
242 CXL_POISON_ENABLED_SCAN_MEDIA,
243 CXL_POISON_ENABLED_SCAN_RESULTS,
244 CXL_POISON_ENABLED_MAX
247 /* Device enabled security commands */
248 enum security_cmd_enabled_bits {
249 CXL_SEC_ENABLED_SANITIZE,
250 CXL_SEC_ENABLED_SECURE_ERASE,
251 CXL_SEC_ENABLED_GET_SECURITY_STATE,
252 CXL_SEC_ENABLED_SET_PASSPHRASE,
253 CXL_SEC_ENABLED_DISABLE_PASSPHRASE,
254 CXL_SEC_ENABLED_UNLOCK,
255 CXL_SEC_ENABLED_FREEZE_SECURITY,
256 CXL_SEC_ENABLED_PASSPHRASE_SECURE_ERASE,
261 * struct cxl_poison_state - Driver poison state info
263 * @max_errors: Maximum media error records held in device cache
264 * @enabled_cmds: All poison commands enabled in the CEL
265 * @list_out: The poison list payload returned by device
266 * @lock: Protect reads of the poison list
268 * Reads of the poison list are synchronized to ensure that a reader
269 * does not get an incomplete list because their request overlapped
270 * (was interrupted or preceded by) another read request of the same
271 * DPA range. CXL Spec 3.0 Section 8.2.9.8.4.1
273 struct cxl_poison_state {
275 DECLARE_BITMAP(enabled_cmds, CXL_POISON_ENABLED_MAX);
276 struct cxl_mbox_poison_out *list_out;
277 struct mutex lock; /* Protect reads of poison list */
282 * CXL rev 3.0 section 8.2.9.3.1; Table 8-56
284 struct cxl_mbox_get_fw_info {
289 char slot_1_revision[16];
290 char slot_2_revision[16];
291 char slot_3_revision[16];
292 char slot_4_revision[16];
295 #define CXL_FW_INFO_SLOT_INFO_CUR_MASK GENMASK(2, 0)
296 #define CXL_FW_INFO_SLOT_INFO_NEXT_MASK GENMASK(5, 3)
297 #define CXL_FW_INFO_SLOT_INFO_NEXT_SHIFT 3
298 #define CXL_FW_INFO_ACTIVATION_CAP_HAS_LIVE_ACTIVATE BIT(0)
301 * Transfer FW Input Payload
302 * CXL rev 3.0 section 8.2.9.3.2; Table 8-57
304 struct cxl_mbox_transfer_fw {
313 #define CXL_FW_TRANSFER_ACTION_FULL 0x0
314 #define CXL_FW_TRANSFER_ACTION_INITIATE 0x1
315 #define CXL_FW_TRANSFER_ACTION_CONTINUE 0x2
316 #define CXL_FW_TRANSFER_ACTION_END 0x3
317 #define CXL_FW_TRANSFER_ACTION_ABORT 0x4
320 * CXL rev 3.0 section 8.2.9.3.2 mandates 128-byte alignment for FW packages
321 * and for each part transferred in a Transfer FW command.
323 #define CXL_FW_TRANSFER_ALIGNMENT 128
326 * Activate FW Input Payload
327 * CXL rev 3.0 section 8.2.9.3.3; Table 8-58
329 struct cxl_mbox_activate_fw {
334 #define CXL_FW_ACTIVATE_ONLINE 0x0
335 #define CXL_FW_ACTIVATE_OFFLINE 0x1
338 #define CXL_FW_STATE_BITS 32
339 #define CXL_FW_CANCEL 0
342 * struct cxl_fw_state - Firmware upload / activation state
344 * @state: fw_uploader state bitmask
345 * @oneshot: whether the fw upload fits in a single transfer
346 * @num_slots: Number of FW slots available
347 * @cur_slot: Slot number currently active
348 * @next_slot: Slot number for the new firmware
350 struct cxl_fw_state {
351 DECLARE_BITMAP(state, CXL_FW_STATE_BITS);
359 * struct cxl_security_state - Device security state
361 * @state: state of last security operation
362 * @enabled_cmds: All security commands enabled in the CEL
363 * @poll_tmo_secs: polling timeout
364 * @poll_dwork: polling work item
365 * @sanitize_node: sanitation sysfs file to notify
367 struct cxl_security_state {
369 DECLARE_BITMAP(enabled_cmds, CXL_SEC_ENABLED_MAX);
371 struct delayed_work poll_dwork;
372 struct kernfs_node *sanitize_node;
376 * enum cxl_devtype - delineate type-2 from a generic type-3 device
377 * @CXL_DEVTYPE_DEVMEM - Vendor specific CXL Type-2 device implementing HDM-D or
378 * HDM-DB, no requirement that this device implements a
379 * mailbox, or other memory-device-standard manageability
381 * @CXL_DEVTYPE_CLASSMEM - Common class definition of a CXL Type-3 device with
382 * HDM-H and class-mandatory memory device registers
386 CXL_DEVTYPE_CLASSMEM,
390 * struct cxl_dev_state - The driver device state
392 * cxl_dev_state represents the CXL driver/device state. It provides an
393 * interface to mailbox commands as well as some cached data about the device.
394 * Currently only memory devices are represented.
396 * @dev: The device associated with this CXL state
397 * @cxlmd: The device representing the CXL.mem capabilities of @dev
398 * @regs: Parsed register blocks
399 * @cxl_dvsec: Offset to the PCIe device DVSEC
400 * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)
401 * @media_ready: Indicate whether the device media is usable
402 * @dpa_res: Overall DPA resource tree for the device
403 * @pmem_res: Active Persistent memory capacity configuration
404 * @ram_res: Active Volatile memory capacity configuration
405 * @component_reg_phys: register base of component registers
406 * @serial: PCIe Device Serial Number
407 * @type: Generic Memory Class device or Vendor Specific Memory device
409 struct cxl_dev_state {
411 struct cxl_memdev *cxlmd;
412 struct cxl_regs regs;
416 struct resource dpa_res;
417 struct resource pmem_res;
418 struct resource ram_res;
419 resource_size_t component_reg_phys;
421 enum cxl_devtype type;
425 * struct cxl_memdev_state - Generic Type-3 Memory Device Class driver data
427 * CXL 8.1.12.1 PCI Header - Class Code Register Memory Device defines
428 * common memory device functionality like the presence of a mailbox and
429 * the functionality related to that like Identify Memory Device and Get
431 * @cxlds: Core driver state common across Type-2 and Type-3 devices
432 * @payload_size: Size of space for payload
433 * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register)
434 * @lsa_size: Size of Label Storage Area
435 * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device)
436 * @mbox_mutex: Mutex to synchronize mailbox access.
437 * @firmware_version: Firmware version for the memory device.
438 * @enabled_cmds: Hardware commands found enabled in CEL.
439 * @exclusive_cmds: Commands that are kernel-internal only
440 * @total_bytes: sum of all possible capacities
441 * @volatile_only_bytes: hard volatile capacity
442 * @persistent_only_bytes: hard persistent capacity
443 * @partition_align_bytes: alignment size for partition-able capacity
444 * @active_volatile_bytes: sum of hard + soft volatile
445 * @active_persistent_bytes: sum of hard + soft persistent
446 * @next_volatile_bytes: volatile capacity change pending device reset
447 * @next_persistent_bytes: persistent capacity change pending device reset
448 * @event: event log driver state
449 * @poison: poison driver state info
450 * @security: security driver state info
451 * @fw: firmware upload / activation state
452 * @mbox_send: @dev specific transport for transmitting mailbox commands
454 * See CXL 3.0 8.2.9.8.2 Capacity Configuration and Label Storage for
455 * details on capacity parameters.
457 struct cxl_memdev_state {
458 struct cxl_dev_state cxlds;
461 struct mutex mbox_mutex; /* Protects device mailbox and firmware */
462 char firmware_version[0x10];
463 DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX);
464 DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX);
466 u64 volatile_only_bytes;
467 u64 persistent_only_bytes;
468 u64 partition_align_bytes;
469 u64 active_volatile_bytes;
470 u64 active_persistent_bytes;
471 u64 next_volatile_bytes;
472 u64 next_persistent_bytes;
473 struct cxl_event_state event;
474 struct cxl_poison_state poison;
475 struct cxl_security_state security;
476 struct cxl_fw_state fw;
478 struct rcuwait mbox_wait;
479 int (*mbox_send)(struct cxl_memdev_state *mds,
480 struct cxl_mbox_cmd *cmd);
483 static inline struct cxl_memdev_state *
484 to_cxl_memdev_state(struct cxl_dev_state *cxlds)
486 if (cxlds->type != CXL_DEVTYPE_CLASSMEM)
488 return container_of(cxlds, struct cxl_memdev_state, cxlds);
492 CXL_MBOX_OP_INVALID = 0x0000,
493 CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID,
494 CXL_MBOX_OP_GET_EVENT_RECORD = 0x0100,
495 CXL_MBOX_OP_CLEAR_EVENT_RECORD = 0x0101,
496 CXL_MBOX_OP_GET_EVT_INT_POLICY = 0x0102,
497 CXL_MBOX_OP_SET_EVT_INT_POLICY = 0x0103,
498 CXL_MBOX_OP_GET_FW_INFO = 0x0200,
499 CXL_MBOX_OP_TRANSFER_FW = 0x0201,
500 CXL_MBOX_OP_ACTIVATE_FW = 0x0202,
501 CXL_MBOX_OP_SET_TIMESTAMP = 0x0301,
502 CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400,
503 CXL_MBOX_OP_GET_LOG = 0x0401,
504 CXL_MBOX_OP_IDENTIFY = 0x4000,
505 CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100,
506 CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101,
507 CXL_MBOX_OP_GET_LSA = 0x4102,
508 CXL_MBOX_OP_SET_LSA = 0x4103,
509 CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200,
510 CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201,
511 CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202,
512 CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203,
513 CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204,
514 CXL_MBOX_OP_GET_POISON = 0x4300,
515 CXL_MBOX_OP_INJECT_POISON = 0x4301,
516 CXL_MBOX_OP_CLEAR_POISON = 0x4302,
517 CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303,
518 CXL_MBOX_OP_SCAN_MEDIA = 0x4304,
519 CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305,
520 CXL_MBOX_OP_SANITIZE = 0x4400,
521 CXL_MBOX_OP_SECURE_ERASE = 0x4401,
522 CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500,
523 CXL_MBOX_OP_SET_PASSPHRASE = 0x4501,
524 CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502,
525 CXL_MBOX_OP_UNLOCK = 0x4503,
526 CXL_MBOX_OP_FREEZE_SECURITY = 0x4504,
527 CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505,
528 CXL_MBOX_OP_MAX = 0x10000
531 #define DEFINE_CXL_CEL_UUID \
532 UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \
535 #define DEFINE_CXL_VENDOR_DEBUG_UUID \
536 UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \
539 struct cxl_mbox_get_supported_logs {
542 struct cxl_gsl_entry {
548 struct cxl_cel_entry {
553 struct cxl_mbox_get_log {
559 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */
560 struct cxl_mbox_identify {
561 char fw_revision[0x10];
562 __le64 total_capacity;
563 __le64 volatile_capacity;
564 __le64 persistent_capacity;
565 __le64 partition_align;
566 __le16 info_event_log_size;
567 __le16 warning_event_log_size;
568 __le16 failure_event_log_size;
569 __le16 fatal_event_log_size;
571 u8 poison_list_max_mer[3];
572 __le16 inject_poison_limit;
574 u8 qos_telemetry_caps;
578 * Common Event Record Format
579 * CXL rev 3.0 section 8.2.9.2.1; Table 8-42
581 struct cxl_event_record_hdr {
586 __le16 related_handle;
592 #define CXL_EVENT_RECORD_DATA_LENGTH 0x50
593 struct cxl_event_record_raw {
594 struct cxl_event_record_hdr hdr;
595 u8 data[CXL_EVENT_RECORD_DATA_LENGTH];
599 * Get Event Records output payload
600 * CXL rev 3.0 section 8.2.9.2.2; Table 8-50
602 #define CXL_GET_EVENT_FLAG_OVERFLOW BIT(0)
603 #define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1)
604 struct cxl_get_event_payload {
607 __le16 overflow_err_count;
608 __le64 first_overflow_timestamp;
609 __le64 last_overflow_timestamp;
612 struct cxl_event_record_raw records[];
616 * CXL rev 3.0 section 8.2.9.2.2; Table 8-49
618 enum cxl_event_log_type {
619 CXL_EVENT_TYPE_INFO = 0x00,
622 CXL_EVENT_TYPE_FATAL,
627 * Clear Event Records input payload
628 * CXL rev 3.0 section 8.2.9.2.3; Table 8-51
630 struct cxl_mbox_clear_event_payload {
631 u8 event_log; /* enum cxl_event_log_type */
637 #define CXL_CLEAR_EVENT_MAX_HANDLES U8_MAX
640 * General Media Event Record
641 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
643 #define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10
644 struct cxl_event_gen_media {
645 struct cxl_event_record_hdr hdr;
650 u8 validity_flags[2];
654 u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
659 * DRAM Event Record - DER
660 * CXL rev 3.0 section 8.2.9.2.1.2; Table 3-44
662 #define CXL_EVENT_DER_CORRECTION_MASK_SIZE 0x20
663 struct cxl_event_dram {
664 struct cxl_event_record_hdr hdr;
669 u8 validity_flags[2];
677 u8 correction_mask[CXL_EVENT_DER_CORRECTION_MASK_SIZE];
682 * Get Health Info Record
683 * CXL rev 3.0 section 8.2.9.8.3.1; Table 8-100
685 struct cxl_get_health_info {
691 u8 dirty_shutdown_cnt[4];
692 u8 cor_vol_err_cnt[4];
693 u8 cor_per_err_cnt[4];
697 * Memory Module Event Record
698 * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45
700 struct cxl_event_mem_module {
701 struct cxl_event_record_hdr hdr;
703 struct cxl_get_health_info info;
707 struct cxl_mbox_get_partition_info {
708 __le64 active_volatile_cap;
709 __le64 active_persistent_cap;
710 __le64 next_volatile_cap;
711 __le64 next_persistent_cap;
714 struct cxl_mbox_get_lsa {
719 struct cxl_mbox_set_lsa {
725 struct cxl_mbox_set_partition_info {
726 __le64 volatile_capacity;
730 #define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0)
732 /* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */
733 struct cxl_mbox_set_timestamp_in {
738 /* Get Poison List CXL 3.0 Spec 8.2.9.8.4.1 */
739 struct cxl_mbox_poison_in {
744 struct cxl_mbox_poison_out {
750 struct cxl_poison_record {
758 * Get Poison List address field encodes the starting
759 * address of poison, and the source of the poison.
761 #define CXL_POISON_START_MASK GENMASK_ULL(63, 6)
762 #define CXL_POISON_SOURCE_MASK GENMASK(2, 0)
764 /* Get Poison List record length is in units of 64 bytes */
765 #define CXL_POISON_LEN_MULT 64
767 /* Kernel defined maximum for a list of poison errors */
768 #define CXL_POISON_LIST_MAX 1024
770 /* Get Poison List: Payload out flags */
771 #define CXL_POISON_FLAG_MORE BIT(0)
772 #define CXL_POISON_FLAG_OVERFLOW BIT(1)
773 #define CXL_POISON_FLAG_SCANNING BIT(2)
775 /* Get Poison List: Poison Source */
776 #define CXL_POISON_SOURCE_UNKNOWN 0
777 #define CXL_POISON_SOURCE_EXTERNAL 1
778 #define CXL_POISON_SOURCE_INTERNAL 2
779 #define CXL_POISON_SOURCE_INJECTED 3
780 #define CXL_POISON_SOURCE_VENDOR 7
782 /* Inject & Clear Poison CXL 3.0 Spec 8.2.9.8.4.2/3 */
783 struct cxl_mbox_inject_poison {
787 /* Clear Poison CXL 3.0 Spec 8.2.9.8.4.3 */
788 struct cxl_mbox_clear_poison {
790 u8 write_data[CXL_POISON_LEN_MULT];
794 * struct cxl_mem_command - Driver representation of a memory device command
795 * @info: Command information as it exists for the UAPI
796 * @opcode: The actual bits used for the mailbox protocol
797 * @flags: Set of flags effecting driver behavior.
799 * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag
800 * will be enabled by the driver regardless of what hardware may have
803 * The cxl_mem_command is the driver's internal representation of commands that
804 * are supported by the driver. Some of these commands may not be supported by
805 * the hardware. The driver will use @info to validate the fields passed in by
806 * the user then submit the @opcode to the hardware.
808 * See struct cxl_command_info.
810 struct cxl_mem_command {
811 struct cxl_command_info info;
812 enum cxl_opcode opcode;
814 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0)
817 #define CXL_PMEM_SEC_STATE_USER_PASS_SET 0x01
818 #define CXL_PMEM_SEC_STATE_MASTER_PASS_SET 0x02
819 #define CXL_PMEM_SEC_STATE_LOCKED 0x04
820 #define CXL_PMEM_SEC_STATE_FROZEN 0x08
821 #define CXL_PMEM_SEC_STATE_USER_PLIMIT 0x10
822 #define CXL_PMEM_SEC_STATE_MASTER_PLIMIT 0x20
824 /* set passphrase input payload */
825 struct cxl_set_pass {
828 /* CXL field using NVDIMM define, same length */
829 u8 old_pass[NVDIMM_PASSPHRASE_LEN];
830 u8 new_pass[NVDIMM_PASSPHRASE_LEN];
833 /* disable passphrase input payload */
834 struct cxl_disable_pass {
837 u8 pass[NVDIMM_PASSPHRASE_LEN];
840 /* passphrase secure erase payload */
841 struct cxl_pass_erase {
844 u8 pass[NVDIMM_PASSPHRASE_LEN];
848 CXL_PMEM_SEC_PASS_MASTER = 0,
849 CXL_PMEM_SEC_PASS_USER,
852 int cxl_internal_send_cmd(struct cxl_memdev_state *mds,
853 struct cxl_mbox_cmd *cmd);
854 int cxl_dev_state_identify(struct cxl_memdev_state *mds);
855 int cxl_await_media_ready(struct cxl_dev_state *cxlds);
856 int cxl_enumerate_cmds(struct cxl_memdev_state *mds);
857 int cxl_mem_create_range_info(struct cxl_memdev_state *mds);
858 struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev);
859 void set_exclusive_cxl_commands(struct cxl_memdev_state *mds,
860 unsigned long *cmds);
861 void clear_exclusive_cxl_commands(struct cxl_memdev_state *mds,
862 unsigned long *cmds);
863 void cxl_mem_get_event_records(struct cxl_memdev_state *mds, u32 status);
864 int cxl_set_timestamp(struct cxl_memdev_state *mds);
865 int cxl_poison_state_init(struct cxl_memdev_state *mds);
866 int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len,
867 struct cxl_region *cxlr);
868 int cxl_trigger_poison_list(struct cxl_memdev *cxlmd);
869 int cxl_inject_poison(struct cxl_memdev *cxlmd, u64 dpa);
870 int cxl_clear_poison(struct cxl_memdev *cxlmd, u64 dpa);
872 #ifdef CONFIG_CXL_SUSPEND
873 void cxl_mem_active_inc(void);
874 void cxl_mem_active_dec(void);
876 static inline void cxl_mem_active_inc(void)
879 static inline void cxl_mem_active_dec(void)
884 int cxl_mem_sanitize(struct cxl_memdev_state *mds, u16 cmd);
887 struct cxl_component_regs regs;
888 unsigned int decoder_count;
889 unsigned int target_count;
890 unsigned int interleave_mask;
891 struct cxl_port *port;
895 struct dentry *cxl_debugfs_create_dir(const char *dir);
896 void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds);
897 #endif /* __CXL_MEM_H__ */