1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright(c) 2020-2021 Intel Corporation. */
5 #include <uapi/linux/cxl_mem.h>
6 #include <linux/cdev.h>
7 #include <linux/uuid.h>
10 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */
11 #define CXLMDEV_STATUS_OFFSET 0x0
12 #define CXLMDEV_DEV_FATAL BIT(0)
13 #define CXLMDEV_FW_HALT BIT(1)
14 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2)
15 #define CXLMDEV_MS_NOT_READY 0
16 #define CXLMDEV_MS_READY 1
17 #define CXLMDEV_MS_ERROR 2
18 #define CXLMDEV_MS_DISABLED 3
19 #define CXLMDEV_READY(status) \
20 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \
22 #define CXLMDEV_MBOX_IF_READY BIT(4)
23 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5)
24 #define CXLMDEV_RESET_NEEDED_NOT 0
25 #define CXLMDEV_RESET_NEEDED_COLD 1
26 #define CXLMDEV_RESET_NEEDED_WARM 2
27 #define CXLMDEV_RESET_NEEDED_HOT 3
28 #define CXLMDEV_RESET_NEEDED_CXL 4
29 #define CXLMDEV_RESET_NEEDED(status) \
30 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \
31 CXLMDEV_RESET_NEEDED_NOT)
34 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device
35 * @dev: driver core device object
36 * @cdev: char dev core object for ioctl operations
37 * @cxlds: The device state backing this device
38 * @detach_work: active memdev lost a port in its ancestry
39 * @cxl_nvb: coordinate removal of @cxl_nvd if present
40 * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem
41 * @id: id number of this memdev instance.
42 * @depth: endpoint port depth
47 struct cxl_dev_state *cxlds;
48 struct work_struct detach_work;
49 struct cxl_nvdimm_bridge *cxl_nvb;
50 struct cxl_nvdimm *cxl_nvd;
55 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev)
57 return container_of(dev, struct cxl_memdev, dev);
60 static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled)
62 return to_cxl_port(cxled->cxld.dev.parent);
65 static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd)
67 return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent);
70 static inline struct cxl_memdev *
71 cxled_to_memdev(struct cxl_endpoint_decoder *cxled)
73 struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent);
75 return to_cxl_memdev(port->uport);
78 bool is_cxl_memdev(struct device *dev);
79 static inline bool is_cxl_endpoint(struct cxl_port *port)
81 return is_cxl_memdev(port->uport);
84 struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds);
85 int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled,
86 resource_size_t base, resource_size_t len,
87 resource_size_t skipped);
89 static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port,
90 struct cxl_memdev *cxlmd)
95 return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev);
99 * struct cxl_mbox_cmd - A command to be submitted to hardware.
100 * @opcode: (input) The command set and command submitted to hardware.
101 * @payload_in: (input) Pointer to the input payload.
102 * @payload_out: (output) Pointer to the output payload. Must be allocated by
104 * @size_in: (input) Number of bytes to load from @payload_in.
105 * @size_out: (input) Max number of bytes loaded into @payload_out.
106 * (output) Number of bytes generated by the device. For fixed size
107 * outputs commands this is always expected to be deterministic. For
108 * variable sized output commands, it tells the exact number of bytes
110 * @min_out: (input) internal command output payload size validation
111 * @return_code: (output) Error code returned from hardware.
113 * This is the primary mechanism used to send commands to the hardware.
114 * All the fields except @payload_* correspond exactly to the fields described in
115 * Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and
116 * @payload_out are written to, and read from the Command Payload Registers
117 * defined in CXL 2.0 8.2.8.4.8.
119 struct cxl_mbox_cmd {
130 * Per CXL 2.0 Section 8.2.8.4.5.1
132 #define CMD_CMD_RC_TABLE \
133 C(SUCCESS, 0, NULL), \
134 C(BACKGROUND, -ENXIO, "background cmd started successfully"), \
135 C(INPUT, -ENXIO, "cmd input was invalid"), \
136 C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \
137 C(INTERNAL, -ENXIO, "internal device error"), \
138 C(RETRY, -ENXIO, "temporary error, retry once"), \
139 C(BUSY, -ENXIO, "ongoing background operation"), \
140 C(MEDIADISABLED, -ENXIO, "media access is disabled"), \
141 C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \
142 C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \
143 C(FWAUTH, -ENXIO, "FW package authentication failed"), \
144 C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \
145 C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \
146 C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \
147 C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \
148 C(PADDR, -ENXIO, "physical address specified is invalid"), \
149 C(POISONLMT, -ENXIO, "poison injection limit has been reached"), \
150 C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \
151 C(ABORT, -ENXIO, "background cmd was aborted by device"), \
152 C(SECURITY, -ENXIO, "not valid in the current security state"), \
153 C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \
154 C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\
155 C(PAYLOADLEN, -ENXIO, "invalid payload length")
158 #define C(a, b, c) CXL_MBOX_CMD_RC_##a
159 enum { CMD_CMD_RC_TABLE };
161 #define C(a, b, c) { b, c }
162 struct cxl_mbox_cmd_rc {
168 struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE };
171 static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd)
173 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc;
176 static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd)
178 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err;
182 * CXL 2.0 - Memory capacity multiplier
183 * See Section 8.2.9.5
185 * Volatile, Persistent, and Partition capacities are specified to be in
186 * multiples of 256MB - define a multiplier to convert to/from bytes.
188 #define CXL_CAPACITY_MULTIPLIER SZ_256M
191 * struct cxl_endpoint_dvsec_info - Cached DVSEC info
192 * @mem_enabled: cached value of mem_enabled in the DVSEC, PCIE_DEVICE
193 * @ranges: Number of active HDM ranges this device uses.
194 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE
196 struct cxl_endpoint_dvsec_info {
199 struct range dvsec_range[2];
203 * Event Interrupt Policy
205 * CXL rev 3.0 section 8.2.9.2.4; Table 8-52
207 enum cxl_event_int_mode {
209 CXL_INT_MSI_MSIX = 0x01,
212 struct cxl_event_interrupt_policy {
220 * struct cxl_event_state - Event log driver state
222 * @event_buf: Buffer to receive event data
223 * @event_log_lock: Serialize event_buf and log use
225 struct cxl_event_state {
226 struct cxl_get_event_payload *buf;
227 struct mutex log_lock;
231 * struct cxl_dev_state - The driver device state
233 * cxl_dev_state represents the CXL driver/device state. It provides an
234 * interface to mailbox commands as well as some cached data about the device.
235 * Currently only memory devices are represented.
237 * @dev: The device associated with this CXL state
238 * @cxlmd: The device representing the CXL.mem capabilities of @dev
239 * @regs: Parsed register blocks
240 * @cxl_dvsec: Offset to the PCIe device DVSEC
241 * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)
242 * @payload_size: Size of space for payload
243 * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register)
244 * @lsa_size: Size of Label Storage Area
245 * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device)
246 * @mbox_mutex: Mutex to synchronize mailbox access.
247 * @firmware_version: Firmware version for the memory device.
248 * @enabled_cmds: Hardware commands found enabled in CEL.
249 * @exclusive_cmds: Commands that are kernel-internal only
250 * @dpa_res: Overall DPA resource tree for the device
251 * @pmem_res: Active Persistent memory capacity configuration
252 * @ram_res: Active Volatile memory capacity configuration
253 * @total_bytes: sum of all possible capacities
254 * @volatile_only_bytes: hard volatile capacity
255 * @persistent_only_bytes: hard persistent capacity
256 * @partition_align_bytes: alignment size for partition-able capacity
257 * @active_volatile_bytes: sum of hard + soft volatile
258 * @active_persistent_bytes: sum of hard + soft persistent
259 * @next_volatile_bytes: volatile capacity change pending device reset
260 * @next_persistent_bytes: persistent capacity change pending device reset
261 * @component_reg_phys: register base of component registers
262 * @info: Cached DVSEC information about the device.
263 * @serial: PCIe Device Serial Number
264 * @doe_mbs: PCI DOE mailbox array
265 * @mbox_send: @dev specific transport for transmitting mailbox commands
267 * See section 8.2.9.5.2 Capacity Configuration and Label Storage for
268 * details on capacity parameters.
270 struct cxl_dev_state {
272 struct cxl_memdev *cxlmd;
274 struct cxl_regs regs;
280 struct mutex mbox_mutex; /* Protects device mailbox and firmware */
281 char firmware_version[0x10];
282 DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX);
283 DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX);
285 struct resource dpa_res;
286 struct resource pmem_res;
287 struct resource ram_res;
289 u64 volatile_only_bytes;
290 u64 persistent_only_bytes;
291 u64 partition_align_bytes;
293 u64 active_volatile_bytes;
294 u64 active_persistent_bytes;
295 u64 next_volatile_bytes;
296 u64 next_persistent_bytes;
298 resource_size_t component_reg_phys;
301 struct xarray doe_mbs;
303 struct cxl_event_state event;
305 int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd);
309 CXL_MBOX_OP_INVALID = 0x0000,
310 CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID,
311 CXL_MBOX_OP_GET_EVENT_RECORD = 0x0100,
312 CXL_MBOX_OP_CLEAR_EVENT_RECORD = 0x0101,
313 CXL_MBOX_OP_GET_EVT_INT_POLICY = 0x0102,
314 CXL_MBOX_OP_SET_EVT_INT_POLICY = 0x0103,
315 CXL_MBOX_OP_GET_FW_INFO = 0x0200,
316 CXL_MBOX_OP_ACTIVATE_FW = 0x0202,
317 CXL_MBOX_OP_SET_TIMESTAMP = 0x0301,
318 CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400,
319 CXL_MBOX_OP_GET_LOG = 0x0401,
320 CXL_MBOX_OP_IDENTIFY = 0x4000,
321 CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100,
322 CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101,
323 CXL_MBOX_OP_GET_LSA = 0x4102,
324 CXL_MBOX_OP_SET_LSA = 0x4103,
325 CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200,
326 CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201,
327 CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202,
328 CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203,
329 CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204,
330 CXL_MBOX_OP_GET_POISON = 0x4300,
331 CXL_MBOX_OP_INJECT_POISON = 0x4301,
332 CXL_MBOX_OP_CLEAR_POISON = 0x4302,
333 CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303,
334 CXL_MBOX_OP_SCAN_MEDIA = 0x4304,
335 CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305,
336 CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500,
337 CXL_MBOX_OP_SET_PASSPHRASE = 0x4501,
338 CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502,
339 CXL_MBOX_OP_UNLOCK = 0x4503,
340 CXL_MBOX_OP_FREEZE_SECURITY = 0x4504,
341 CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505,
342 CXL_MBOX_OP_MAX = 0x10000
345 #define DEFINE_CXL_CEL_UUID \
346 UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \
349 #define DEFINE_CXL_VENDOR_DEBUG_UUID \
350 UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \
353 struct cxl_mbox_get_supported_logs {
356 struct cxl_gsl_entry {
362 struct cxl_cel_entry {
367 struct cxl_mbox_get_log {
373 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */
374 struct cxl_mbox_identify {
375 char fw_revision[0x10];
376 __le64 total_capacity;
377 __le64 volatile_capacity;
378 __le64 persistent_capacity;
379 __le64 partition_align;
380 __le16 info_event_log_size;
381 __le16 warning_event_log_size;
382 __le16 failure_event_log_size;
383 __le16 fatal_event_log_size;
385 u8 poison_list_max_mer[3];
386 __le16 inject_poison_limit;
388 u8 qos_telemetry_caps;
392 * Common Event Record Format
393 * CXL rev 3.0 section 8.2.9.2.1; Table 8-42
395 struct cxl_event_record_hdr {
400 __le16 related_handle;
406 #define CXL_EVENT_RECORD_DATA_LENGTH 0x50
407 struct cxl_event_record_raw {
408 struct cxl_event_record_hdr hdr;
409 u8 data[CXL_EVENT_RECORD_DATA_LENGTH];
413 * Get Event Records output payload
414 * CXL rev 3.0 section 8.2.9.2.2; Table 8-50
416 #define CXL_GET_EVENT_FLAG_OVERFLOW BIT(0)
417 #define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1)
418 struct cxl_get_event_payload {
421 __le16 overflow_err_count;
422 __le64 first_overflow_timestamp;
423 __le64 last_overflow_timestamp;
426 struct cxl_event_record_raw records[];
430 * CXL rev 3.0 section 8.2.9.2.2; Table 8-49
432 enum cxl_event_log_type {
433 CXL_EVENT_TYPE_INFO = 0x00,
436 CXL_EVENT_TYPE_FATAL,
441 * Clear Event Records input payload
442 * CXL rev 3.0 section 8.2.9.2.3; Table 8-51
444 struct cxl_mbox_clear_event_payload {
445 u8 event_log; /* enum cxl_event_log_type */
451 #define CXL_CLEAR_EVENT_MAX_HANDLES U8_MAX
454 * General Media Event Record
455 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
457 #define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10
458 struct cxl_event_gen_media {
459 struct cxl_event_record_hdr hdr;
464 u8 validity_flags[2];
468 u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
473 * DRAM Event Record - DER
474 * CXL rev 3.0 section 8.2.9.2.1.2; Table 3-44
476 #define CXL_EVENT_DER_CORRECTION_MASK_SIZE 0x20
477 struct cxl_event_dram {
478 struct cxl_event_record_hdr hdr;
483 u8 validity_flags[2];
491 u8 correction_mask[CXL_EVENT_DER_CORRECTION_MASK_SIZE];
496 * Get Health Info Record
497 * CXL rev 3.0 section 8.2.9.8.3.1; Table 8-100
499 struct cxl_get_health_info {
505 u8 dirty_shutdown_cnt[4];
506 u8 cor_vol_err_cnt[4];
507 u8 cor_per_err_cnt[4];
511 * Memory Module Event Record
512 * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45
514 struct cxl_event_mem_module {
515 struct cxl_event_record_hdr hdr;
517 struct cxl_get_health_info info;
521 struct cxl_mbox_get_partition_info {
522 __le64 active_volatile_cap;
523 __le64 active_persistent_cap;
524 __le64 next_volatile_cap;
525 __le64 next_persistent_cap;
528 struct cxl_mbox_get_lsa {
533 struct cxl_mbox_set_lsa {
539 struct cxl_mbox_set_partition_info {
540 __le64 volatile_capacity;
544 #define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0)
546 /* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */
547 struct cxl_mbox_set_timestamp_in {
553 * struct cxl_mem_command - Driver representation of a memory device command
554 * @info: Command information as it exists for the UAPI
555 * @opcode: The actual bits used for the mailbox protocol
556 * @flags: Set of flags effecting driver behavior.
558 * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag
559 * will be enabled by the driver regardless of what hardware may have
562 * The cxl_mem_command is the driver's internal representation of commands that
563 * are supported by the driver. Some of these commands may not be supported by
564 * the hardware. The driver will use @info to validate the fields passed in by
565 * the user then submit the @opcode to the hardware.
567 * See struct cxl_command_info.
569 struct cxl_mem_command {
570 struct cxl_command_info info;
571 enum cxl_opcode opcode;
573 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0)
576 #define CXL_PMEM_SEC_STATE_USER_PASS_SET 0x01
577 #define CXL_PMEM_SEC_STATE_MASTER_PASS_SET 0x02
578 #define CXL_PMEM_SEC_STATE_LOCKED 0x04
579 #define CXL_PMEM_SEC_STATE_FROZEN 0x08
580 #define CXL_PMEM_SEC_STATE_USER_PLIMIT 0x10
581 #define CXL_PMEM_SEC_STATE_MASTER_PLIMIT 0x20
583 /* set passphrase input payload */
584 struct cxl_set_pass {
587 /* CXL field using NVDIMM define, same length */
588 u8 old_pass[NVDIMM_PASSPHRASE_LEN];
589 u8 new_pass[NVDIMM_PASSPHRASE_LEN];
592 /* disable passphrase input payload */
593 struct cxl_disable_pass {
596 u8 pass[NVDIMM_PASSPHRASE_LEN];
599 /* passphrase secure erase payload */
600 struct cxl_pass_erase {
603 u8 pass[NVDIMM_PASSPHRASE_LEN];
607 CXL_PMEM_SEC_PASS_MASTER = 0,
608 CXL_PMEM_SEC_PASS_USER,
611 int cxl_internal_send_cmd(struct cxl_dev_state *cxlds,
612 struct cxl_mbox_cmd *cmd);
613 int cxl_dev_state_identify(struct cxl_dev_state *cxlds);
614 int cxl_await_media_ready(struct cxl_dev_state *cxlds);
615 int cxl_enumerate_cmds(struct cxl_dev_state *cxlds);
616 int cxl_mem_create_range_info(struct cxl_dev_state *cxlds);
617 struct cxl_dev_state *cxl_dev_state_create(struct device *dev);
618 void set_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds);
619 void clear_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds);
620 void cxl_mem_get_event_records(struct cxl_dev_state *cxlds, u32 status);
621 int cxl_set_timestamp(struct cxl_dev_state *cxlds);
623 #ifdef CONFIG_CXL_SUSPEND
624 void cxl_mem_active_inc(void);
625 void cxl_mem_active_dec(void);
627 static inline void cxl_mem_active_inc(void)
630 static inline void cxl_mem_active_dec(void)
636 struct cxl_component_regs regs;
637 unsigned int decoder_count;
638 unsigned int target_count;
639 unsigned int interleave_mask;
640 struct cxl_port *port;
644 struct dentry *cxl_debugfs_create_dir(const char *dir);
645 void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds);
646 #endif /* __CXL_MEM_H__ */