1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
8 #include <linux/gpio/driver.h>
9 #include <linux/interrupt.h>
11 #include <linux/module.h>
12 #include <linux/of_irq.h>
13 #include <linux/platform_device.h>
14 #include <linux/spinlock.h>
16 #define MTK_BANK_CNT 3
17 #define MTK_BANK_WIDTH 32
19 #define GPIO_BANK_STRIDE 0x04
20 #define GPIO_REG_CTRL 0x00
21 #define GPIO_REG_POL 0x10
22 #define GPIO_REG_DATA 0x20
23 #define GPIO_REG_DSET 0x30
24 #define GPIO_REG_DCLR 0x40
25 #define GPIO_REG_REDGE 0x50
26 #define GPIO_REG_FEDGE 0x60
27 #define GPIO_REG_HLVL 0x70
28 #define GPIO_REG_LLVL 0x80
29 #define GPIO_REG_STAT 0x90
30 #define GPIO_REG_EDGE 0xA0
33 struct irq_chip irq_chip;
34 struct gpio_chip chip;
44 * struct mtk - state container for
45 * data of the platform driver. It is 3
46 * separate gpio-chip each one with its
48 * @dev: device instance
49 * @base: memory base address
50 * @gpio_irq: irq number from the device tree
51 * @gc_map: array of the gpio chips
57 struct mtk_gc gc_map[MTK_BANK_CNT];
60 static inline struct mtk_gc *
61 to_mediatek_gpio(struct gpio_chip *chip)
63 return container_of(chip, struct mtk_gc, chip);
67 mtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val)
69 struct gpio_chip *gc = &rg->chip;
70 struct mtk *mtk = gpiochip_get_data(gc);
72 offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
73 gc->write_reg(mtk->base + offset, val);
77 mtk_gpio_r32(struct mtk_gc *rg, u32 offset)
79 struct gpio_chip *gc = &rg->chip;
80 struct mtk *mtk = gpiochip_get_data(gc);
82 offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
83 return gc->read_reg(mtk->base + offset);
87 mediatek_gpio_irq_handler(int irq, void *data)
89 struct gpio_chip *gc = data;
90 struct mtk_gc *rg = to_mediatek_gpio(gc);
91 irqreturn_t ret = IRQ_NONE;
92 unsigned long pending;
95 pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
97 for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
98 generic_handle_domain_irq(gc->irq.domain, bit);
99 mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
107 mediatek_gpio_irq_unmask(struct irq_data *d)
109 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
110 struct mtk_gc *rg = to_mediatek_gpio(gc);
113 u32 rise, fall, high, low;
115 gpiochip_enable_irq(gc, d->hwirq);
117 spin_lock_irqsave(&rg->lock, flags);
118 rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
119 fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
120 high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
121 low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
122 mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(pin) & rg->rising));
123 mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(pin) & rg->falling));
124 mtk_gpio_w32(rg, GPIO_REG_HLVL, high | (BIT(pin) & rg->hlevel));
125 mtk_gpio_w32(rg, GPIO_REG_LLVL, low | (BIT(pin) & rg->llevel));
126 spin_unlock_irqrestore(&rg->lock, flags);
130 mediatek_gpio_irq_mask(struct irq_data *d)
132 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
133 struct mtk_gc *rg = to_mediatek_gpio(gc);
136 u32 rise, fall, high, low;
138 spin_lock_irqsave(&rg->lock, flags);
139 rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
140 fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
141 high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
142 low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
143 mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(pin));
144 mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin));
145 mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin));
146 mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin));
147 spin_unlock_irqrestore(&rg->lock, flags);
149 gpiochip_disable_irq(gc, d->hwirq);
153 mediatek_gpio_irq_type(struct irq_data *d, unsigned int type)
155 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
156 struct mtk_gc *rg = to_mediatek_gpio(gc);
160 if (type == IRQ_TYPE_PROBE) {
161 if ((rg->rising | rg->falling |
162 rg->hlevel | rg->llevel) & mask)
165 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
169 rg->falling &= ~mask;
173 switch (type & IRQ_TYPE_SENSE_MASK) {
174 case IRQ_TYPE_EDGE_BOTH:
178 case IRQ_TYPE_EDGE_RISING:
181 case IRQ_TYPE_EDGE_FALLING:
184 case IRQ_TYPE_LEVEL_HIGH:
187 case IRQ_TYPE_LEVEL_LOW:
196 mediatek_gpio_xlate(struct gpio_chip *chip,
197 const struct of_phandle_args *spec, u32 *flags)
199 int gpio = spec->args[0];
200 struct mtk_gc *rg = to_mediatek_gpio(chip);
202 if (rg->bank != gpio / MTK_BANK_WIDTH)
206 *flags = spec->args[1];
208 return gpio % MTK_BANK_WIDTH;
211 static const struct irq_chip mt7621_irq_chip = {
212 .name = "mt7621-gpio",
213 .irq_mask_ack = mediatek_gpio_irq_mask,
214 .irq_mask = mediatek_gpio_irq_mask,
215 .irq_unmask = mediatek_gpio_irq_unmask,
216 .irq_set_type = mediatek_gpio_irq_type,
217 .flags = IRQCHIP_IMMUTABLE,
218 GPIOCHIP_IRQ_RESOURCE_HELPERS,
222 mediatek_gpio_bank_probe(struct device *dev, int bank)
224 struct mtk *mtk = dev_get_drvdata(dev);
226 void __iomem *dat, *set, *ctrl, *diro;
229 rg = &mtk->gc_map[bank];
230 memset(rg, 0, sizeof(*rg));
232 spin_lock_init(&rg->lock);
235 dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE);
236 set = mtk->base + GPIO_REG_DSET + (rg->bank * GPIO_BANK_STRIDE);
237 ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE);
238 diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE);
240 ret = bgpio_init(&rg->chip, dev, 4, dat, set, ctrl, diro, NULL,
241 BGPIOF_NO_SET_ON_INPUT);
243 dev_err(dev, "bgpio_init() failed\n");
247 rg->chip.of_gpio_n_cells = 2;
248 rg->chip.of_xlate = mediatek_gpio_xlate;
249 rg->chip.label = devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d",
250 dev_name(dev), bank);
254 rg->chip.offset = bank * MTK_BANK_WIDTH;
257 struct gpio_irq_chip *girq;
260 * Directly request the irq here instead of passing
261 * a flow-handler because the irq is shared.
263 ret = devm_request_irq(dev, mtk->gpio_irq,
264 mediatek_gpio_irq_handler, IRQF_SHARED,
265 rg->chip.label, &rg->chip);
268 dev_err(dev, "Error requesting IRQ %d: %d\n",
273 girq = &rg->chip.irq;
274 gpio_irq_chip_set_chip(girq, &mt7621_irq_chip);
275 /* This will let us handle the parent IRQ in the driver */
276 girq->parent_handler = NULL;
277 girq->num_parents = 0;
278 girq->parents = NULL;
279 girq->default_type = IRQ_TYPE_NONE;
280 girq->handler = handle_simple_irq;
283 ret = devm_gpiochip_add_data(dev, &rg->chip, mtk);
285 dev_err(dev, "Could not register gpio %d, ret=%d\n",
286 rg->chip.ngpio, ret);
290 /* set polarity to low for all gpios */
291 mtk_gpio_w32(rg, GPIO_REG_POL, 0);
293 dev_info(dev, "registering %d gpios\n", rg->chip.ngpio);
299 mediatek_gpio_probe(struct platform_device *pdev)
301 struct device *dev = &pdev->dev;
302 struct device_node *np = dev->of_node;
307 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
311 mtk->base = devm_platform_ioremap_resource(pdev, 0);
312 if (IS_ERR(mtk->base))
313 return PTR_ERR(mtk->base);
315 mtk->gpio_irq = irq_of_parse_and_map(np, 0);
317 platform_set_drvdata(pdev, mtk);
319 for (i = 0; i < MTK_BANK_CNT; i++) {
320 ret = mediatek_gpio_bank_probe(dev, i);
328 static const struct of_device_id mediatek_gpio_match[] = {
329 { .compatible = "mediatek,mt7621-gpio" },
332 MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
334 static struct platform_driver mediatek_gpio_driver = {
335 .probe = mediatek_gpio_probe,
337 .name = "mt7621_gpio",
338 .of_match_table = mediatek_gpio_match,
342 builtin_platform_driver(mediatek_gpio_driver);