2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/debugfs.h>
25 #include <linux/list.h>
26 #include <linux/module.h>
27 #include <linux/uaccess.h>
28 #include <linux/reboot.h>
29 #include <linux/syscalls.h>
30 #include <linux/pm_runtime.h>
33 #include "amdgpu_ras.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_xgmi.h"
36 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
38 #ifdef CONFIG_X86_MCE_AMD
41 static bool notifier_registered;
43 static const char *RAS_FS_NAME = "ras";
45 const char *ras_error_string[] = {
49 "multi_uncorrectable",
53 const char *ras_block_string[] = {
73 const char *ras_mca_block_string[] = {
80 struct amdgpu_ras_block_list {
82 struct list_head node;
84 struct amdgpu_ras_block_object *ras_obj;
87 const char *get_ras_block_str(struct ras_common_if *ras_block)
92 if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT)
93 return "OUT OF RANGE";
95 if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)
96 return ras_mca_block_string[ras_block->sub_block_index];
98 return ras_block_string[ras_block->block];
101 #define ras_block_str(_BLOCK_) \
102 (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range")
104 #define ras_err_str(i) (ras_error_string[ffs(i)])
106 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
108 /* inject address is 52 bits */
109 #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52)
111 /* typical ECC bad page rate is 1 bad page per 100MB VRAM */
112 #define RAS_BAD_PAGE_COVER (100 * 1024 * 1024ULL)
114 enum amdgpu_ras_retire_page_reservation {
115 AMDGPU_RAS_RETIRE_PAGE_RESERVED,
116 AMDGPU_RAS_RETIRE_PAGE_PENDING,
117 AMDGPU_RAS_RETIRE_PAGE_FAULT,
120 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
122 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
124 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
126 #ifdef CONFIG_X86_MCE_AMD
127 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev);
128 struct mce_notifier_adev_list {
129 struct amdgpu_device *devs[MAX_GPU_INSTANCE];
132 static struct mce_notifier_adev_list mce_adev_list;
135 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
137 if (adev && amdgpu_ras_get_context(adev))
138 amdgpu_ras_get_context(adev)->error_query_ready = ready;
141 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
143 if (adev && amdgpu_ras_get_context(adev))
144 return amdgpu_ras_get_context(adev)->error_query_ready;
149 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
151 struct ras_err_data err_data = {0, 0, 0, NULL};
152 struct eeprom_table_record err_rec;
154 if ((address >= adev->gmc.mc_vram_size) ||
155 (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
157 "RAS WARN: input address 0x%llx is invalid.\n",
162 if (amdgpu_ras_check_bad_page(adev, address)) {
164 "RAS WARN: 0x%llx has already been marked as bad page!\n",
169 memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
170 err_data.err_addr = &err_rec;
171 amdgpu_umc_fill_error_record(&err_data, address,
172 (address >> AMDGPU_GPU_PAGE_SHIFT), 0, 0);
174 if (amdgpu_bad_page_threshold != 0) {
175 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
176 err_data.err_addr_cnt);
177 amdgpu_ras_save_bad_pages(adev);
180 dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
181 dev_warn(adev->dev, "Clear EEPROM:\n");
182 dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
187 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
188 size_t size, loff_t *pos)
190 struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
191 struct ras_query_if info = {
197 if (amdgpu_ras_query_error_status(obj->adev, &info))
200 /* Hardware counter will be reset automatically after the query on Vega20 and Arcturus */
201 if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
202 obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
203 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
204 dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
207 s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
209 "ce", info.ce_count);
214 s = min_t(u64, s, size);
217 if (copy_to_user(buf, &val[*pos], s))
225 static const struct file_operations amdgpu_ras_debugfs_ops = {
226 .owner = THIS_MODULE,
227 .read = amdgpu_ras_debugfs_read,
229 .llseek = default_llseek
232 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
236 for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
238 if (strcmp(name, ras_block_string[i]) == 0)
244 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
245 const char __user *buf, size_t size,
246 loff_t *pos, struct ras_debug_if *data)
248 ssize_t s = min_t(u64, 64, size);
261 memset(str, 0, sizeof(str));
262 memset(data, 0, sizeof(*data));
264 if (copy_from_user(str, buf, s))
267 if (sscanf(str, "disable %32s", block_name) == 1)
269 else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
271 else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
273 else if (strstr(str, "retire_page") != NULL)
275 else if (str[0] && str[1] && str[2] && str[3])
276 /* ascii string, but commands are not matched. */
281 if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
282 sscanf(str, "%*s %llu", &address) != 1)
286 data->inject.address = address;
291 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
294 data->head.block = block_id;
295 /* only ue and ce errors are supported */
296 if (!memcmp("ue", err, 2))
297 data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
298 else if (!memcmp("ce", err, 2))
299 data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
306 if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
307 &sub_block, &address, &value) != 3 &&
308 sscanf(str, "%*s %*s %*s %u %llu %llu",
309 &sub_block, &address, &value) != 3)
311 data->head.sub_block_index = sub_block;
312 data->inject.address = address;
313 data->inject.value = value;
316 if (size < sizeof(*data))
319 if (copy_from_user(data, buf, sizeof(*data)))
327 * DOC: AMDGPU RAS debugfs control interface
329 * The control interface accepts struct ras_debug_if which has two members.
331 * First member: ras_debug_if::head or ras_debug_if::inject.
333 * head is used to indicate which IP block will be under control.
335 * head has four members, they are block, type, sub_block_index, name.
336 * block: which IP will be under control.
337 * type: what kind of error will be enabled/disabled/injected.
338 * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
339 * name: the name of IP.
341 * inject has two more members than head, they are address, value.
342 * As their names indicate, inject operation will write the
343 * value to the address.
345 * The second member: struct ras_debug_if::op.
346 * It has three kinds of operations.
348 * - 0: disable RAS on the block. Take ::head as its data.
349 * - 1: enable RAS on the block. Take ::head as its data.
350 * - 2: inject errors on the block. Take ::inject as its data.
352 * How to use the interface?
356 * Copy the struct ras_debug_if in your code and initialize it.
357 * Write the struct to the control interface.
361 * .. code-block:: bash
363 * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
364 * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
365 * echo "inject <block> <error> <sub-block> <address> <value> > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
367 * Where N, is the card which you want to affect.
369 * "disable" requires only the block.
370 * "enable" requires the block and error type.
371 * "inject" requires the block, error type, address, and value.
373 * The block is one of: umc, sdma, gfx, etc.
374 * see ras_block_string[] for details
376 * The error type is one of: ue, ce, where,
377 * ue is multi-uncorrectable
378 * ce is single-correctable
380 * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
381 * The address and value are hexadecimal numbers, leading 0x is optional.
385 * .. code-block:: bash
387 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
388 * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
389 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
391 * How to check the result of the operation?
393 * To check disable/enable, see "ras" features at,
394 * /sys/class/drm/card[0/1/2...]/device/ras/features
396 * To check inject, see the corresponding error count at,
397 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
400 * Operations are only allowed on blocks which are supported.
401 * Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
402 * to see which blocks support RAS on a particular asic.
405 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
406 const char __user *buf,
407 size_t size, loff_t *pos)
409 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
410 struct ras_debug_if data;
413 if (!amdgpu_ras_get_error_query_ready(adev)) {
414 dev_warn(adev->dev, "RAS WARN: error injection "
415 "currently inaccessible\n");
419 ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
424 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
431 if (!amdgpu_ras_is_supported(adev, data.head.block))
436 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
439 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
442 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
443 (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
444 dev_warn(adev->dev, "RAS WARN: input address "
445 "0x%llx is invalid.",
446 data.inject.address);
451 /* umc ce/ue error injection for a bad page is not allowed */
452 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
453 amdgpu_ras_check_bad_page(adev, data.inject.address)) {
454 dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has "
455 "already been marked as bad!\n",
456 data.inject.address);
460 /* data.inject.address is offset instead of absolute gpu address */
461 ret = amdgpu_ras_error_inject(adev, &data.inject);
475 * DOC: AMDGPU RAS debugfs EEPROM table reset interface
477 * Some boards contain an EEPROM which is used to persistently store a list of
478 * bad pages which experiences ECC errors in vram. This interface provides
479 * a way to reset the EEPROM, e.g., after testing error injection.
483 * .. code-block:: bash
485 * echo 1 > ../ras/ras_eeprom_reset
487 * will reset EEPROM table to 0 entries.
490 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
491 const char __user *buf,
492 size_t size, loff_t *pos)
494 struct amdgpu_device *adev =
495 (struct amdgpu_device *)file_inode(f)->i_private;
498 ret = amdgpu_ras_eeprom_reset_table(
499 &(amdgpu_ras_get_context(adev)->eeprom_control));
502 /* Something was written to EEPROM.
504 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
511 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
512 .owner = THIS_MODULE,
514 .write = amdgpu_ras_debugfs_ctrl_write,
515 .llseek = default_llseek
518 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
519 .owner = THIS_MODULE,
521 .write = amdgpu_ras_debugfs_eeprom_write,
522 .llseek = default_llseek
526 * DOC: AMDGPU RAS sysfs Error Count Interface
528 * It allows the user to read the error count for each IP block on the gpu through
529 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
531 * It outputs the multiple lines which report the uncorrected (ue) and corrected
534 * The format of one line is below,
540 * .. code-block:: bash
546 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
547 struct device_attribute *attr, char *buf)
549 struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
550 struct ras_query_if info = {
554 if (!amdgpu_ras_get_error_query_ready(obj->adev))
555 return sysfs_emit(buf, "Query currently inaccessible\n");
557 if (amdgpu_ras_query_error_status(obj->adev, &info))
560 if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
561 obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
562 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
563 dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
566 return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
567 "ce", info.ce_count);
572 #define get_obj(obj) do { (obj)->use++; } while (0)
573 #define alive_obj(obj) ((obj)->use)
575 static inline void put_obj(struct ras_manager *obj)
577 if (obj && (--obj->use == 0))
578 list_del(&obj->node);
579 if (obj && (obj->use < 0))
580 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head));
583 /* make one obj and return it. */
584 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
585 struct ras_common_if *head)
587 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
588 struct ras_manager *obj;
590 if (!adev->ras_enabled || !con)
593 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
596 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
597 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
600 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
602 obj = &con->objs[head->block];
604 /* already exist. return obj? */
610 list_add(&obj->node, &con->head);
616 /* return an obj equal to head, or the first when head is NULL */
617 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
618 struct ras_common_if *head)
620 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
621 struct ras_manager *obj;
624 if (!adev->ras_enabled || !con)
628 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
631 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
632 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
635 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
637 obj = &con->objs[head->block];
642 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
653 /* feature ctl begin */
654 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
655 struct ras_common_if *head)
657 return adev->ras_hw_enabled & BIT(head->block);
660 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
661 struct ras_common_if *head)
663 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
665 return con->features & BIT(head->block);
669 * if obj is not created, then create one.
670 * set feature enable flag.
672 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
673 struct ras_common_if *head, int enable)
675 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
676 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
678 /* If hardware does not support ras, then do not create obj.
679 * But if hardware support ras, we can create the obj.
680 * Ras framework checks con->hw_supported to see if it need do
681 * corresponding initialization.
682 * IP checks con->support to see if it need disable ras.
684 if (!amdgpu_ras_is_feature_allowed(adev, head))
689 obj = amdgpu_ras_create_obj(adev, head);
693 /* In case we create obj somewhere else */
696 con->features |= BIT(head->block);
698 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
699 con->features &= ~BIT(head->block);
707 /* wrapper of psp_ras_enable_features */
708 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
709 struct ras_common_if *head, bool enable)
711 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
712 union ta_ras_cmd_input *info;
718 info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
723 info->disable_features = (struct ta_ras_disable_features_input) {
724 .block_id = amdgpu_ras_block_to_ta(head->block),
725 .error_type = amdgpu_ras_error_to_ta(head->type),
728 info->enable_features = (struct ta_ras_enable_features_input) {
729 .block_id = amdgpu_ras_block_to_ta(head->block),
730 .error_type = amdgpu_ras_error_to_ta(head->type),
734 /* Do not enable if it is not allowed. */
735 WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
737 /* Only enable ras feature operation handle on host side */
738 if (!amdgpu_sriov_vf(adev) &&
739 !amdgpu_ras_intr_triggered()) {
740 ret = psp_ras_enable_features(&adev->psp, info, enable);
742 dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n",
743 enable ? "enable":"disable",
744 get_ras_block_str(head),
745 amdgpu_ras_is_poison_mode_supported(adev), ret);
751 __amdgpu_ras_feature_enable(adev, head, enable);
758 /* Only used in device probe stage and called only once. */
759 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
760 struct ras_common_if *head, bool enable)
762 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
768 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
770 /* There is no harm to issue a ras TA cmd regardless of
771 * the currecnt ras state.
772 * If current state == target state, it will do nothing
773 * But sometimes it requests driver to reset and repost
774 * with error code -EAGAIN.
776 ret = amdgpu_ras_feature_enable(adev, head, 1);
777 /* With old ras TA, we might fail to enable ras.
778 * Log it and just setup the object.
779 * TODO need remove this WA in the future.
781 if (ret == -EINVAL) {
782 ret = __amdgpu_ras_feature_enable(adev, head, 1);
785 "RAS INFO: %s setup object\n",
786 get_ras_block_str(head));
789 /* setup the object then issue a ras TA disable cmd.*/
790 ret = __amdgpu_ras_feature_enable(adev, head, 1);
794 /* gfx block ras dsiable cmd must send to ras-ta */
795 if (head->block == AMDGPU_RAS_BLOCK__GFX)
796 con->features |= BIT(head->block);
798 ret = amdgpu_ras_feature_enable(adev, head, 0);
800 /* clean gfx block ras features flag */
801 if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
802 con->features &= ~BIT(head->block);
805 ret = amdgpu_ras_feature_enable(adev, head, enable);
810 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
813 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
814 struct ras_manager *obj, *tmp;
816 list_for_each_entry_safe(obj, tmp, &con->head, node) {
818 * aka just release the obj and corresponding flags
821 if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
824 if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
829 return con->features;
832 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
835 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
837 const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE;
839 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
840 struct ras_common_if head = {
842 .type = default_ras_type,
843 .sub_block_index = 0,
846 if (i == AMDGPU_RAS_BLOCK__MCA)
851 * bypass psp. vbios enable ras for us.
852 * so just create the obj
854 if (__amdgpu_ras_feature_enable(adev, &head, 1))
857 if (amdgpu_ras_feature_enable(adev, &head, 1))
862 for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
863 struct ras_common_if head = {
864 .block = AMDGPU_RAS_BLOCK__MCA,
865 .type = default_ras_type,
866 .sub_block_index = i,
871 * bypass psp. vbios enable ras for us.
872 * so just create the obj
874 if (__amdgpu_ras_feature_enable(adev, &head, 1))
877 if (amdgpu_ras_feature_enable(adev, &head, 1))
882 return con->features;
884 /* feature ctl end */
886 static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj,
887 enum amdgpu_ras_block block)
892 if (block_obj->ras_comm.block == block)
898 static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev,
899 enum amdgpu_ras_block block, uint32_t sub_block_index)
901 struct amdgpu_ras_block_list *node, *tmp;
902 struct amdgpu_ras_block_object *obj;
904 if (block >= AMDGPU_RAS_BLOCK__LAST)
907 if (!amdgpu_ras_is_supported(adev, block))
910 list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
911 if (!node->ras_obj) {
912 dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
917 if (obj->ras_block_match) {
918 if (obj->ras_block_match(obj, block, sub_block_index) == 0)
921 if (amdgpu_ras_block_match_default(obj, block) == 0)
929 static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data)
931 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
935 * choosing right query method according to
936 * whether smu support query error information
938 ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc));
939 if (ret == -EOPNOTSUPP) {
940 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
941 adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
942 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
944 /* umc query_ras_error_address is also responsible for clearing
947 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
948 adev->umc.ras->ras_block.hw_ops->query_ras_error_address)
949 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data);
952 adev->umc.ras->ecc_info_query_ras_error_count)
953 adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data);
956 adev->umc.ras->ecc_info_query_ras_error_address)
957 adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data);
961 /* query/inject/cure begin */
962 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
963 struct ras_query_if *info)
965 struct amdgpu_ras_block_object *block_obj = NULL;
966 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
967 struct ras_err_data err_data = {0, 0, 0, NULL};
972 if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {
973 amdgpu_ras_get_ecc_info(adev, &err_data);
975 block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);
976 if (!block_obj || !block_obj->hw_ops) {
977 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
978 get_ras_block_str(&info->head));
982 if (block_obj->hw_ops->query_ras_error_count)
983 block_obj->hw_ops->query_ras_error_count(adev, &err_data);
985 if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||
986 (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||
987 (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {
988 if (block_obj->hw_ops->query_ras_error_status)
989 block_obj->hw_ops->query_ras_error_status(adev);
993 obj->err_data.ue_count += err_data.ue_count;
994 obj->err_data.ce_count += err_data.ce_count;
996 info->ue_count = obj->err_data.ue_count;
997 info->ce_count = obj->err_data.ce_count;
999 if (err_data.ce_count) {
1000 if (adev->smuio.funcs &&
1001 adev->smuio.funcs->get_socket_id &&
1002 adev->smuio.funcs->get_die_id) {
1003 dev_info(adev->dev, "socket: %d, die: %d "
1004 "%ld correctable hardware errors "
1005 "detected in %s block, no user "
1006 "action is needed.\n",
1007 adev->smuio.funcs->get_socket_id(adev),
1008 adev->smuio.funcs->get_die_id(adev),
1009 obj->err_data.ce_count,
1010 get_ras_block_str(&info->head));
1012 dev_info(adev->dev, "%ld correctable hardware errors "
1013 "detected in %s block, no user "
1014 "action is needed.\n",
1015 obj->err_data.ce_count,
1016 get_ras_block_str(&info->head));
1019 if (err_data.ue_count) {
1020 if (adev->smuio.funcs &&
1021 adev->smuio.funcs->get_socket_id &&
1022 adev->smuio.funcs->get_die_id) {
1023 dev_info(adev->dev, "socket: %d, die: %d "
1024 "%ld uncorrectable hardware errors "
1025 "detected in %s block\n",
1026 adev->smuio.funcs->get_socket_id(adev),
1027 adev->smuio.funcs->get_die_id(adev),
1028 obj->err_data.ue_count,
1029 get_ras_block_str(&info->head));
1031 dev_info(adev->dev, "%ld uncorrectable hardware errors "
1032 "detected in %s block\n",
1033 obj->err_data.ue_count,
1034 get_ras_block_str(&info->head));
1041 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
1042 enum amdgpu_ras_block block)
1044 struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1046 if (!amdgpu_ras_is_supported(adev, block))
1049 if (!block_obj || !block_obj->hw_ops) {
1050 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1051 ras_block_str(block));
1055 if (block_obj->hw_ops->reset_ras_error_count)
1056 block_obj->hw_ops->reset_ras_error_count(adev);
1058 if ((block == AMDGPU_RAS_BLOCK__GFX) ||
1059 (block == AMDGPU_RAS_BLOCK__MMHUB)) {
1060 if (block_obj->hw_ops->reset_ras_error_status)
1061 block_obj->hw_ops->reset_ras_error_status(adev);
1067 /* wrapper of psp_ras_trigger_error */
1068 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
1069 struct ras_inject_if *info)
1071 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1072 struct ta_ras_trigger_error_input block_info = {
1073 .block_id = amdgpu_ras_block_to_ta(info->head.block),
1074 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
1075 .sub_block_index = info->head.sub_block_index,
1076 .address = info->address,
1077 .value = info->value,
1080 struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev,
1082 info->head.sub_block_index);
1087 if (!block_obj || !block_obj->hw_ops) {
1088 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1089 get_ras_block_str(&info->head));
1093 /* Calculate XGMI relative offset */
1094 if (adev->gmc.xgmi.num_physical_nodes > 1) {
1095 block_info.address =
1096 amdgpu_xgmi_get_relative_phy_addr(adev,
1097 block_info.address);
1100 if (info->head.block == AMDGPU_RAS_BLOCK__GFX) {
1101 if (block_obj->hw_ops->ras_error_inject)
1102 ret = block_obj->hw_ops->ras_error_inject(adev, info);
1104 /* If defined special ras_error_inject(e.g: xgmi), implement special ras_error_inject */
1105 if (block_obj->hw_ops->ras_error_inject)
1106 ret = block_obj->hw_ops->ras_error_inject(adev, &block_info);
1107 else /*If not defined .ras_error_inject, use default ras_error_inject*/
1108 ret = psp_ras_trigger_error(&adev->psp, &block_info);
1112 dev_err(adev->dev, "ras inject %s failed %d\n",
1113 get_ras_block_str(&info->head), ret);
1119 * amdgpu_ras_query_error_count -- Get error counts of all IPs
1120 * @adev: pointer to AMD GPU device
1121 * @ce_count: pointer to an integer to be set to the count of correctible errors.
1122 * @ue_count: pointer to an integer to be set to the count of uncorrectible
1125 * If set, @ce_count or @ue_count, count and return the corresponding
1126 * error counts in those integer pointers. Return 0 if the device
1127 * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
1129 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1130 unsigned long *ce_count,
1131 unsigned long *ue_count)
1133 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1134 struct ras_manager *obj;
1135 unsigned long ce, ue;
1137 if (!adev->ras_enabled || !con)
1140 /* Don't count since no reporting.
1142 if (!ce_count && !ue_count)
1147 list_for_each_entry(obj, &con->head, node) {
1148 struct ras_query_if info = {
1153 res = amdgpu_ras_query_error_status(adev, &info);
1157 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
1158 adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
1159 if (amdgpu_ras_reset_error_status(adev, info.head.block))
1160 dev_warn(adev->dev, "Failed to reset error counter and error status");
1163 ce += info.ce_count;
1164 ue += info.ue_count;
1175 /* query/inject/cure end */
1180 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1181 struct ras_badpage **bps, unsigned int *count);
1183 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1186 case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1188 case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1190 case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1197 * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1199 * It allows user to read the bad pages of vram on the gpu through
1200 * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1202 * It outputs multiple lines, and each line stands for one gpu page.
1204 * The format of one line is below,
1205 * gpu pfn : gpu page size : flags
1207 * gpu pfn and gpu page size are printed in hex format.
1208 * flags can be one of below character,
1210 * R: reserved, this gpu page is reserved and not able to use.
1212 * P: pending for reserve, this gpu page is marked as bad, will be reserved
1213 * in next window of page_reserve.
1215 * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1219 * .. code-block:: bash
1221 * 0x00000001 : 0x00001000 : R
1222 * 0x00000002 : 0x00001000 : P
1226 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1227 struct kobject *kobj, struct bin_attribute *attr,
1228 char *buf, loff_t ppos, size_t count)
1230 struct amdgpu_ras *con =
1231 container_of(attr, struct amdgpu_ras, badpages_attr);
1232 struct amdgpu_device *adev = con->adev;
1233 const unsigned int element_size =
1234 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1235 unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1236 unsigned int end = div64_ul(ppos + count - 1, element_size);
1238 struct ras_badpage *bps = NULL;
1239 unsigned int bps_count = 0;
1241 memset(buf, 0, count);
1243 if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1246 for (; start < end && start < bps_count; start++)
1247 s += scnprintf(&buf[s], element_size + 1,
1248 "0x%08x : 0x%08x : %1s\n",
1251 amdgpu_ras_badpage_flags_str(bps[start].flags));
1258 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1259 struct device_attribute *attr, char *buf)
1261 struct amdgpu_ras *con =
1262 container_of(attr, struct amdgpu_ras, features_attr);
1264 return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
1267 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1269 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1271 sysfs_remove_file_from_group(&adev->dev->kobj,
1272 &con->badpages_attr.attr,
1276 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1278 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1279 struct attribute *attrs[] = {
1280 &con->features_attr.attr,
1283 struct attribute_group group = {
1284 .name = RAS_FS_NAME,
1288 sysfs_remove_group(&adev->dev->kobj, &group);
1293 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1294 struct ras_common_if *head)
1296 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1298 if (!obj || obj->attr_inuse)
1303 snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name),
1304 "%s_err_count", head->name);
1306 obj->sysfs_attr = (struct device_attribute){
1308 .name = obj->fs_data.sysfs_name,
1311 .show = amdgpu_ras_sysfs_read,
1313 sysfs_attr_init(&obj->sysfs_attr.attr);
1315 if (sysfs_add_file_to_group(&adev->dev->kobj,
1316 &obj->sysfs_attr.attr,
1322 obj->attr_inuse = 1;
1327 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1328 struct ras_common_if *head)
1330 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1332 if (!obj || !obj->attr_inuse)
1335 sysfs_remove_file_from_group(&adev->dev->kobj,
1336 &obj->sysfs_attr.attr,
1338 obj->attr_inuse = 0;
1344 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1346 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1347 struct ras_manager *obj, *tmp;
1349 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1350 amdgpu_ras_sysfs_remove(adev, &obj->head);
1353 if (amdgpu_bad_page_threshold != 0)
1354 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1356 amdgpu_ras_sysfs_remove_feature_node(adev);
1363 * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1365 * Normally when there is an uncorrectable error, the driver will reset
1366 * the GPU to recover. However, in the event of an unrecoverable error,
1367 * the driver provides an interface to reboot the system automatically
1370 * The following file in debugfs provides that interface:
1371 * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1375 * .. code-block:: bash
1377 * echo true > .../ras/auto_reboot
1381 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1383 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1384 struct drm_minor *minor = adev_to_drm(adev)->primary;
1387 dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1388 debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1389 &amdgpu_ras_debugfs_ctrl_ops);
1390 debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1391 &amdgpu_ras_debugfs_eeprom_ops);
1392 debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1393 &con->bad_page_cnt_threshold);
1394 debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
1395 debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
1396 debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
1397 &amdgpu_ras_debugfs_eeprom_size_ops);
1398 con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",
1400 &amdgpu_ras_debugfs_eeprom_table_ops);
1401 amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);
1404 * After one uncorrectable error happens, usually GPU recovery will
1405 * be scheduled. But due to the known problem in GPU recovery failing
1406 * to bring GPU back, below interface provides one direct way to
1407 * user to reboot system automatically in such case within
1408 * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1409 * will never be called.
1411 debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1414 * User could set this not to clean up hardware's error count register
1415 * of RAS IPs during ras recovery.
1417 debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1418 &con->disable_ras_err_cnt_harvest);
1422 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1423 struct ras_fs_if *head,
1426 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1433 memcpy(obj->fs_data.debugfs_name,
1435 sizeof(obj->fs_data.debugfs_name));
1437 debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1438 obj, &amdgpu_ras_debugfs_ops);
1441 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1443 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1445 struct ras_manager *obj;
1446 struct ras_fs_if fs_info;
1449 * it won't be called in resume path, no need to check
1450 * suspend and gpu reset status
1452 if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1455 dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1457 list_for_each_entry(obj, &con->head, node) {
1458 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1459 (obj->attr_inuse == 1)) {
1460 sprintf(fs_info.debugfs_name, "%s_err_inject",
1461 get_ras_block_str(&obj->head));
1462 fs_info.head = obj->head;
1463 amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1471 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1472 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1473 static DEVICE_ATTR(features, S_IRUGO,
1474 amdgpu_ras_sysfs_features_read, NULL);
1475 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1477 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1478 struct attribute_group group = {
1479 .name = RAS_FS_NAME,
1481 struct attribute *attrs[] = {
1482 &con->features_attr.attr,
1485 struct bin_attribute *bin_attrs[] = {
1491 /* add features entry */
1492 con->features_attr = dev_attr_features;
1493 group.attrs = attrs;
1494 sysfs_attr_init(attrs[0]);
1496 if (amdgpu_bad_page_threshold != 0) {
1497 /* add bad_page_features entry */
1498 bin_attr_gpu_vram_bad_pages.private = NULL;
1499 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1500 bin_attrs[0] = &con->badpages_attr;
1501 group.bin_attrs = bin_attrs;
1502 sysfs_bin_attr_init(bin_attrs[0]);
1505 r = sysfs_create_group(&adev->dev->kobj, &group);
1507 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1512 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1514 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1515 struct ras_manager *con_obj, *ip_obj, *tmp;
1517 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1518 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1519 ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1525 amdgpu_ras_sysfs_remove_all(adev);
1532 /* For the hardware that cannot enable bif ring for both ras_controller_irq
1533 * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
1534 * register to check whether the interrupt is triggered or not, and properly
1535 * ack the interrupt if it is there
1537 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev)
1539 /* Fatal error events are handled on host side */
1540 if (amdgpu_sriov_vf(adev) ||
1541 !amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF))
1544 if (adev->nbio.ras &&
1545 adev->nbio.ras->handle_ras_controller_intr_no_bifring)
1546 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev);
1548 if (adev->nbio.ras &&
1549 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring)
1550 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev);
1553 static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj,
1554 struct amdgpu_iv_entry *entry)
1556 bool poison_stat = false;
1557 struct amdgpu_device *adev = obj->adev;
1558 struct ras_err_data err_data = {0, 0, 0, NULL};
1559 struct amdgpu_ras_block_object *block_obj =
1560 amdgpu_ras_get_ras_block(adev, obj->head.block, 0);
1562 if (!block_obj || !block_obj->hw_ops)
1565 /* both query_poison_status and handle_poison_consumption are optional,
1566 * but at least one of them should be implemented if we need poison
1567 * consumption handler
1569 if (block_obj->hw_ops->query_poison_status) {
1570 poison_stat = block_obj->hw_ops->query_poison_status(adev);
1572 /* Not poison consumption interrupt, no need to handle it */
1573 dev_info(adev->dev, "No RAS poison status in %s poison IH.\n",
1574 block_obj->ras_comm.name);
1580 if (!adev->gmc.xgmi.connected_to_cpu)
1581 amdgpu_umc_poison_handler(adev, &err_data, false);
1583 if (block_obj->hw_ops->handle_poison_consumption)
1584 poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);
1586 /* gpu reset is fallback for failed and default cases */
1588 dev_info(adev->dev, "GPU reset for %s RAS poison consumption is issued!\n",
1589 block_obj->ras_comm.name);
1590 amdgpu_ras_reset_gpu(adev);
1594 static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj,
1595 struct amdgpu_iv_entry *entry)
1597 dev_info(obj->adev->dev,
1598 "Poison is created, no user action is needed.\n");
1601 static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj,
1602 struct amdgpu_iv_entry *entry)
1604 struct ras_ih_data *data = &obj->ih_data;
1605 struct ras_err_data err_data = {0, 0, 0, NULL};
1611 /* Let IP handle its data, maybe we need get the output
1612 * from the callback to update the error type/count, etc
1614 ret = data->cb(obj->adev, &err_data, entry);
1615 /* ue will trigger an interrupt, and in that case
1616 * we need do a reset to recovery the whole system.
1617 * But leave IP do that recovery, here we just dispatch
1620 if (ret == AMDGPU_RAS_SUCCESS) {
1621 /* these counts could be left as 0 if
1622 * some blocks do not count error number
1624 obj->err_data.ue_count += err_data.ue_count;
1625 obj->err_data.ce_count += err_data.ce_count;
1629 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1631 struct ras_ih_data *data = &obj->ih_data;
1632 struct amdgpu_iv_entry entry;
1634 while (data->rptr != data->wptr) {
1636 memcpy(&entry, &data->ring[data->rptr],
1637 data->element_size);
1640 data->rptr = (data->aligned_element_size +
1641 data->rptr) % data->ring_size;
1643 if (amdgpu_ras_is_poison_mode_supported(obj->adev)) {
1644 if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1645 amdgpu_ras_interrupt_poison_creation_handler(obj, &entry);
1647 amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry);
1649 if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1650 amdgpu_ras_interrupt_umc_handler(obj, &entry);
1652 dev_warn(obj->adev->dev,
1653 "No RAS interrupt handler for non-UMC block with poison disabled.\n");
1658 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1660 struct ras_ih_data *data =
1661 container_of(work, struct ras_ih_data, ih_work);
1662 struct ras_manager *obj =
1663 container_of(data, struct ras_manager, ih_data);
1665 amdgpu_ras_interrupt_handler(obj);
1668 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1669 struct ras_dispatch_if *info)
1671 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1672 struct ras_ih_data *data = &obj->ih_data;
1677 if (data->inuse == 0)
1680 /* Might be overflow... */
1681 memcpy(&data->ring[data->wptr], info->entry,
1682 data->element_size);
1685 data->wptr = (data->aligned_element_size +
1686 data->wptr) % data->ring_size;
1688 schedule_work(&data->ih_work);
1693 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1694 struct ras_common_if *head)
1696 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1697 struct ras_ih_data *data;
1702 data = &obj->ih_data;
1703 if (data->inuse == 0)
1706 cancel_work_sync(&data->ih_work);
1709 memset(data, 0, sizeof(*data));
1715 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1716 struct ras_common_if *head)
1718 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1719 struct ras_ih_data *data;
1720 struct amdgpu_ras_block_object *ras_obj;
1723 /* in case we registe the IH before enable ras feature */
1724 obj = amdgpu_ras_create_obj(adev, head);
1730 ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm);
1732 data = &obj->ih_data;
1733 /* add the callback.etc */
1734 *data = (struct ras_ih_data) {
1736 .cb = ras_obj->ras_cb,
1737 .element_size = sizeof(struct amdgpu_iv_entry),
1742 INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1744 data->aligned_element_size = ALIGN(data->element_size, 8);
1745 /* the ring can store 64 iv entries. */
1746 data->ring_size = 64 * data->aligned_element_size;
1747 data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1759 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1761 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1762 struct ras_manager *obj, *tmp;
1764 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1765 amdgpu_ras_interrupt_remove_handler(adev, &obj->head);
1772 /* traversal all IPs except NBIO to query error counter */
1773 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1775 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1776 struct ras_manager *obj;
1778 if (!adev->ras_enabled || !con)
1781 list_for_each_entry(obj, &con->head, node) {
1782 struct ras_query_if info = {
1787 * PCIE_BIF IP has one different isr by ras controller
1788 * interrupt, the specific ras counter query will be
1789 * done in that isr. So skip such block from common
1790 * sync flood interrupt isr calling.
1792 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1796 * this is a workaround for aldebaran, skip send msg to
1797 * smu to get ecc_info table due to smu handle get ecc
1798 * info table failed temporarily.
1799 * should be removed until smu fix handle ecc_info table.
1801 if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) &&
1802 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)))
1805 amdgpu_ras_query_error_status(adev, &info);
1807 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
1808 adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4) &&
1809 adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 0)) {
1810 if (amdgpu_ras_reset_error_status(adev, info.head.block))
1811 dev_warn(adev->dev, "Failed to reset error counter and error status");
1816 /* Parse RdRspStatus and WrRspStatus */
1817 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1818 struct ras_query_if *info)
1820 struct amdgpu_ras_block_object *block_obj;
1822 * Only two block need to query read/write
1823 * RspStatus at current state
1825 if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) &&
1826 (info->head.block != AMDGPU_RAS_BLOCK__MMHUB))
1829 block_obj = amdgpu_ras_get_ras_block(adev,
1831 info->head.sub_block_index);
1833 if (!block_obj || !block_obj->hw_ops) {
1834 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1835 get_ras_block_str(&info->head));
1839 if (block_obj->hw_ops->query_ras_error_status)
1840 block_obj->hw_ops->query_ras_error_status(adev);
1844 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1846 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1847 struct ras_manager *obj;
1849 if (!adev->ras_enabled || !con)
1852 list_for_each_entry(obj, &con->head, node) {
1853 struct ras_query_if info = {
1857 amdgpu_ras_error_status_query(adev, &info);
1861 /* recovery begin */
1863 /* return 0 on success.
1864 * caller need free bps.
1866 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1867 struct ras_badpage **bps, unsigned int *count)
1869 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1870 struct ras_err_handler_data *data;
1872 int ret = 0, status;
1874 if (!con || !con->eh_data || !bps || !count)
1877 mutex_lock(&con->recovery_lock);
1878 data = con->eh_data;
1879 if (!data || data->count == 0) {
1885 *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1891 for (; i < data->count; i++) {
1892 (*bps)[i] = (struct ras_badpage){
1893 .bp = data->bps[i].retired_page,
1894 .size = AMDGPU_GPU_PAGE_SIZE,
1895 .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
1897 status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr,
1898 data->bps[i].retired_page);
1899 if (status == -EBUSY)
1900 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1901 else if (status == -ENOENT)
1902 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
1905 *count = data->count;
1907 mutex_unlock(&con->recovery_lock);
1911 static void amdgpu_ras_do_recovery(struct work_struct *work)
1913 struct amdgpu_ras *ras =
1914 container_of(work, struct amdgpu_ras, recovery_work);
1915 struct amdgpu_device *remote_adev = NULL;
1916 struct amdgpu_device *adev = ras->adev;
1917 struct list_head device_list, *device_list_handle = NULL;
1919 if (!ras->disable_ras_err_cnt_harvest) {
1920 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
1922 /* Build list of devices to query RAS related errors */
1923 if (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
1924 device_list_handle = &hive->device_list;
1926 INIT_LIST_HEAD(&device_list);
1927 list_add_tail(&adev->gmc.xgmi.head, &device_list);
1928 device_list_handle = &device_list;
1931 list_for_each_entry(remote_adev,
1932 device_list_handle, gmc.xgmi.head) {
1933 amdgpu_ras_query_err_status(remote_adev);
1934 amdgpu_ras_log_on_err_counter(remote_adev);
1937 amdgpu_put_xgmi_hive(hive);
1940 if (amdgpu_device_should_recover_gpu(ras->adev))
1941 amdgpu_device_gpu_recover(ras->adev, NULL);
1942 atomic_set(&ras->in_recovery, 0);
1945 /* alloc/realloc bps array */
1946 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1947 struct ras_err_handler_data *data, int pages)
1949 unsigned int old_space = data->count + data->space_left;
1950 unsigned int new_space = old_space + pages;
1951 unsigned int align_space = ALIGN(new_space, 512);
1952 void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1959 memcpy(bps, data->bps,
1960 data->count * sizeof(*data->bps));
1965 data->space_left += align_space - old_space;
1969 /* it deal with vram only. */
1970 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1971 struct eeprom_table_record *bps, int pages)
1973 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1974 struct ras_err_handler_data *data;
1978 if (!con || !con->eh_data || !bps || pages <= 0)
1981 mutex_lock(&con->recovery_lock);
1982 data = con->eh_data;
1986 for (i = 0; i < pages; i++) {
1987 if (amdgpu_ras_check_bad_page_unlock(con,
1988 bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
1991 if (!data->space_left &&
1992 amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
1997 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr,
1998 bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
1999 AMDGPU_GPU_PAGE_SIZE);
2001 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
2006 mutex_unlock(&con->recovery_lock);
2012 * write error record array to eeprom, the function should be
2013 * protected by recovery_lock
2015 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
2017 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2018 struct ras_err_handler_data *data;
2019 struct amdgpu_ras_eeprom_control *control;
2022 if (!con || !con->eh_data)
2025 mutex_lock(&con->recovery_lock);
2026 control = &con->eeprom_control;
2027 data = con->eh_data;
2028 save_count = data->count - control->ras_num_recs;
2029 mutex_unlock(&con->recovery_lock);
2030 /* only new entries are saved */
2031 if (save_count > 0) {
2032 if (amdgpu_ras_eeprom_append(control,
2033 &data->bps[control->ras_num_recs],
2035 dev_err(adev->dev, "Failed to save EEPROM table data!");
2039 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
2046 * read error record array in eeprom and reserve enough space for
2047 * storing new bad pages
2049 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
2051 struct amdgpu_ras_eeprom_control *control =
2052 &adev->psp.ras_context.ras->eeprom_control;
2053 struct eeprom_table_record *bps;
2056 /* no bad page record, skip eeprom access */
2057 if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)
2060 bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL);
2064 ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs);
2066 dev_err(adev->dev, "Failed to load EEPROM table records!");
2068 ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs);
2074 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
2077 struct ras_err_handler_data *data = con->eh_data;
2080 addr >>= AMDGPU_GPU_PAGE_SHIFT;
2081 for (i = 0; i < data->count; i++)
2082 if (addr == data->bps[i].retired_page)
2089 * check if an address belongs to bad page
2091 * Note: this check is only for umc block
2093 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
2096 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2099 if (!con || !con->eh_data)
2102 mutex_lock(&con->recovery_lock);
2103 ret = amdgpu_ras_check_bad_page_unlock(con, addr);
2104 mutex_unlock(&con->recovery_lock);
2108 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
2111 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2114 * Justification of value bad_page_cnt_threshold in ras structure
2116 * Generally, -1 <= amdgpu_bad_page_threshold <= max record length
2117 * in eeprom, and introduce two scenarios accordingly.
2119 * Bad page retirement enablement:
2120 * - If amdgpu_bad_page_threshold = -1,
2121 * bad_page_cnt_threshold = typical value by formula.
2123 * - When the value from user is 0 < amdgpu_bad_page_threshold <
2124 * max record length in eeprom, use it directly.
2126 * Bad page retirement disablement:
2127 * - If amdgpu_bad_page_threshold = 0, bad page retirement
2128 * functionality is disabled, and bad_page_cnt_threshold will
2132 if (amdgpu_bad_page_threshold < 0) {
2133 u64 val = adev->gmc.mc_vram_size;
2135 do_div(val, RAS_BAD_PAGE_COVER);
2136 con->bad_page_cnt_threshold = min(lower_32_bits(val),
2139 con->bad_page_cnt_threshold = min_t(int, max_count,
2140 amdgpu_bad_page_threshold);
2144 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
2146 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2147 struct ras_err_handler_data **data;
2148 u32 max_eeprom_records_count = 0;
2149 bool exc_err_limit = false;
2155 /* Allow access to RAS EEPROM via debugfs, when the ASIC
2156 * supports RAS and debugfs is enabled, but when
2157 * adev->ras_enabled is unset, i.e. when "ras_enable"
2158 * module parameter is set to 0.
2162 if (!adev->ras_enabled)
2165 data = &con->eh_data;
2166 *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
2172 mutex_init(&con->recovery_lock);
2173 INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
2174 atomic_set(&con->in_recovery, 0);
2175 con->eeprom_control.bad_channel_bitmap = 0;
2177 max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count();
2178 amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
2180 /* Todo: During test the SMU might fail to read the eeprom through I2C
2181 * when the GPU is pending on XGMI reset during probe time
2182 * (Mostly after second bus reset), skip it now
2184 if (adev->gmc.xgmi.pending_reset)
2186 ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
2188 * This calling fails when exc_err_limit is true or
2191 if (exc_err_limit || ret)
2194 if (con->eeprom_control.ras_num_recs) {
2195 ret = amdgpu_ras_load_bad_pages(adev);
2199 amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
2201 if (con->update_channel_flag == true) {
2202 amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap);
2203 con->update_channel_flag = false;
2207 #ifdef CONFIG_X86_MCE_AMD
2208 if ((adev->asic_type == CHIP_ALDEBARAN) &&
2209 (adev->gmc.xgmi.connected_to_cpu))
2210 amdgpu_register_bad_pages_mca_notifier(adev);
2215 kfree((*data)->bps);
2217 con->eh_data = NULL;
2219 dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);
2222 * Except error threshold exceeding case, other failure cases in this
2223 * function would not fail amdgpu driver init.
2233 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2235 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2236 struct ras_err_handler_data *data = con->eh_data;
2238 /* recovery_init failed to init it, fini is useless */
2242 cancel_work_sync(&con->recovery_work);
2244 mutex_lock(&con->recovery_lock);
2245 con->eh_data = NULL;
2248 mutex_unlock(&con->recovery_lock);
2254 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2256 return adev->asic_type == CHIP_VEGA10 ||
2257 adev->asic_type == CHIP_VEGA20 ||
2258 adev->asic_type == CHIP_ARCTURUS ||
2259 adev->asic_type == CHIP_ALDEBARAN ||
2260 adev->asic_type == CHIP_SIENNA_CICHLID;
2264 * this is workaround for vega20 workstation sku,
2265 * force enable gfx ras, ignore vbios gfx ras flag
2266 * due to GC EDC can not write
2268 static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
2270 struct atom_context *ctx = adev->mode_info.atom_context;
2275 if (strnstr(ctx->vbios_version, "D16406",
2276 sizeof(ctx->vbios_version)) ||
2277 strnstr(ctx->vbios_version, "D36002",
2278 sizeof(ctx->vbios_version)))
2279 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
2283 * check hardware's ras ability which will be saved in hw_supported.
2284 * if hardware does not support ras, we can skip some ras initializtion and
2285 * forbid some ras operations from IP.
2286 * if software itself, say boot parameter, limit the ras ability. We still
2287 * need allow IP do some limited operations, like disable. In such case,
2288 * we have to initialize ras as normal. but need check if operation is
2289 * allowed or not in each function.
2291 static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
2293 adev->ras_hw_enabled = adev->ras_enabled = 0;
2295 if (!adev->is_atom_fw ||
2296 !amdgpu_ras_asic_supported(adev))
2299 /* If driver run on sriov guest side, only enable ras for aldebaran */
2300 if (amdgpu_sriov_vf(adev) &&
2301 adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 2))
2304 if (!adev->gmc.xgmi.connected_to_cpu) {
2305 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2306 dev_info(adev->dev, "MEM ECC is active.\n");
2307 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
2308 1 << AMDGPU_RAS_BLOCK__DF);
2310 dev_info(adev->dev, "MEM ECC is not presented.\n");
2313 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2314 dev_info(adev->dev, "SRAM ECC is active.\n");
2315 if (!amdgpu_sriov_vf(adev)) {
2316 adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2317 1 << AMDGPU_RAS_BLOCK__DF);
2319 if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(2, 6, 0))
2320 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN |
2321 1 << AMDGPU_RAS_BLOCK__JPEG);
2323 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN |
2324 1 << AMDGPU_RAS_BLOCK__JPEG);
2326 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF |
2327 1 << AMDGPU_RAS_BLOCK__SDMA |
2328 1 << AMDGPU_RAS_BLOCK__GFX);
2331 dev_info(adev->dev, "SRAM ECC is not presented.\n");
2334 /* driver only manages a few IP blocks RAS feature
2335 * when GPU is connected cpu through XGMI */
2336 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
2337 1 << AMDGPU_RAS_BLOCK__SDMA |
2338 1 << AMDGPU_RAS_BLOCK__MMHUB);
2341 amdgpu_ras_get_quirks(adev);
2343 /* hw_supported needs to be aligned with RAS block mask. */
2344 adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
2346 adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
2347 adev->ras_hw_enabled & amdgpu_ras_mask;
2350 static void amdgpu_ras_counte_dw(struct work_struct *work)
2352 struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
2353 ras_counte_delay_work.work);
2354 struct amdgpu_device *adev = con->adev;
2355 struct drm_device *dev = adev_to_drm(adev);
2356 unsigned long ce_count, ue_count;
2359 res = pm_runtime_get_sync(dev->dev);
2363 /* Cache new values.
2365 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) {
2366 atomic_set(&con->ras_ce_count, ce_count);
2367 atomic_set(&con->ras_ue_count, ue_count);
2370 pm_runtime_mark_last_busy(dev->dev);
2372 pm_runtime_put_autosuspend(dev->dev);
2375 int amdgpu_ras_init(struct amdgpu_device *adev)
2377 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2379 bool df_poison, umc_poison;
2384 con = kmalloc(sizeof(struct amdgpu_ras) +
2385 sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT +
2386 sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT,
2387 GFP_KERNEL|__GFP_ZERO);
2392 INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
2393 atomic_set(&con->ras_ce_count, 0);
2394 atomic_set(&con->ras_ue_count, 0);
2396 con->objs = (struct ras_manager *)(con + 1);
2398 amdgpu_ras_set_context(adev, con);
2400 amdgpu_ras_check_supported(adev);
2402 if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
2403 /* set gfx block ras context feature for VEGA20 Gaming
2404 * send ras disable cmd to ras ta during ras late init.
2406 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
2407 con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2416 con->update_channel_flag = false;
2418 INIT_LIST_HEAD(&con->head);
2419 /* Might need get this flag from vbios. */
2420 con->flags = RAS_DEFAULT_FLAGS;
2422 /* initialize nbio ras function ahead of any other
2423 * ras functions so hardware fatal error interrupt
2424 * can be enabled as early as possible */
2425 switch (adev->asic_type) {
2428 case CHIP_ALDEBARAN:
2429 if (!adev->gmc.xgmi.connected_to_cpu) {
2430 adev->nbio.ras = &nbio_v7_4_ras;
2431 amdgpu_ras_register_ras_block(adev, &adev->nbio.ras->ras_block);
2432 adev->nbio.ras_if = &adev->nbio.ras->ras_block.ras_comm;
2436 /* nbio ras is not available */
2440 if (adev->nbio.ras &&
2441 adev->nbio.ras->init_ras_controller_interrupt) {
2442 r = adev->nbio.ras->init_ras_controller_interrupt(adev);
2447 if (adev->nbio.ras &&
2448 adev->nbio.ras->init_ras_err_event_athub_interrupt) {
2449 r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev);
2454 /* Init poison supported flag, the default value is false */
2455 if (adev->gmc.xgmi.connected_to_cpu) {
2456 /* enabled by default when GPU is connected to CPU */
2457 con->poison_supported = true;
2459 else if (adev->df.funcs &&
2460 adev->df.funcs->query_ras_poison_mode &&
2462 adev->umc.ras->query_ras_poison_mode) {
2464 adev->df.funcs->query_ras_poison_mode(adev);
2466 adev->umc.ras->query_ras_poison_mode(adev);
2467 /* Only poison is set in both DF and UMC, we can support it */
2468 if (df_poison && umc_poison)
2469 con->poison_supported = true;
2470 else if (df_poison != umc_poison)
2471 dev_warn(adev->dev, "Poison setting is inconsistent in DF/UMC(%d:%d)!\n",
2472 df_poison, umc_poison);
2475 if (amdgpu_ras_fs_init(adev)) {
2480 dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2481 "hardware ability[%x] ras_mask[%x]\n",
2482 adev->ras_hw_enabled, adev->ras_enabled);
2486 amdgpu_ras_set_context(adev, NULL);
2492 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2494 if (adev->gmc.xgmi.connected_to_cpu)
2499 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2500 struct ras_common_if *ras_block)
2502 struct ras_query_if info = {
2506 if (!amdgpu_persistent_edc_harvesting_supported(adev))
2509 if (amdgpu_ras_query_error_status(adev, &info) != 0)
2510 DRM_WARN("RAS init harvest failure");
2512 if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2513 DRM_WARN("RAS init harvest reset failure");
2518 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev)
2520 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2525 return con->poison_supported;
2528 /* helper function to handle common stuff in ip late init phase */
2529 int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
2530 struct ras_common_if *ras_block)
2532 struct amdgpu_ras_block_object *ras_obj = NULL;
2533 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2534 unsigned long ue_count, ce_count;
2537 /* disable RAS feature per IP block if it is not supported */
2538 if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2539 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2543 r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2545 if (adev->in_suspend || amdgpu_in_reset(adev)) {
2546 /* in resume phase, if fail to enable ras,
2547 * clean up all ras fs nodes, and disable ras */
2553 /* check for errors on warm reset edc persisant supported ASIC */
2554 amdgpu_persistent_edc_harvesting(adev, ras_block);
2556 /* in resume phase, no need to create ras fs node */
2557 if (adev->in_suspend || amdgpu_in_reset(adev))
2560 ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
2561 if (ras_obj->ras_cb || (ras_obj->hw_ops &&
2562 (ras_obj->hw_ops->query_poison_status ||
2563 ras_obj->hw_ops->handle_poison_consumption))) {
2564 r = amdgpu_ras_interrupt_add_handler(adev, ras_block);
2569 r = amdgpu_ras_sysfs_create(adev, ras_block);
2573 /* Those are the cached values at init.
2575 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) {
2576 atomic_set(&con->ras_ce_count, ce_count);
2577 atomic_set(&con->ras_ue_count, ue_count);
2583 if (ras_obj->ras_cb)
2584 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
2586 amdgpu_ras_feature_enable(adev, ras_block, 0);
2590 static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
2591 struct ras_common_if *ras_block)
2593 return amdgpu_ras_block_late_init(adev, ras_block);
2596 /* helper function to remove ras fs node and interrupt handler */
2597 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
2598 struct ras_common_if *ras_block)
2600 struct amdgpu_ras_block_object *ras_obj;
2604 amdgpu_ras_sysfs_remove(adev, ras_block);
2606 ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
2607 if (ras_obj->ras_cb)
2608 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
2611 static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev,
2612 struct ras_common_if *ras_block)
2614 return amdgpu_ras_block_late_fini(adev, ras_block);
2617 /* do some init work after IP late init as dependence.
2618 * and it runs in resume/gpu reset/booting up cases.
2620 void amdgpu_ras_resume(struct amdgpu_device *adev)
2622 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2623 struct ras_manager *obj, *tmp;
2625 if (!adev->ras_enabled || !con) {
2626 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2627 amdgpu_release_ras_context(adev);
2632 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2633 /* Set up all other IPs which are not implemented. There is a
2634 * tricky thing that IP's actual ras error type should be
2635 * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2636 * ERROR_NONE make sense anyway.
2638 amdgpu_ras_enable_all_features(adev, 1);
2640 /* We enable ras on all hw_supported block, but as boot
2641 * parameter might disable some of them and one or more IP has
2642 * not implemented yet. So we disable them on behalf.
2644 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2645 if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2646 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2647 /* there should be no any reference. */
2648 WARN_ON(alive_obj(obj));
2654 void amdgpu_ras_suspend(struct amdgpu_device *adev)
2656 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2658 if (!adev->ras_enabled || !con)
2661 amdgpu_ras_disable_all_features(adev, 0);
2662 /* Make sure all ras objects are disabled. */
2664 amdgpu_ras_disable_all_features(adev, 1);
2667 int amdgpu_ras_late_init(struct amdgpu_device *adev)
2669 struct amdgpu_ras_block_list *node, *tmp;
2670 struct amdgpu_ras_block_object *obj;
2673 /* Guest side doesn't need init ras feature */
2674 if (amdgpu_sriov_vf(adev))
2677 list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
2678 if (!node->ras_obj) {
2679 dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
2683 obj = node->ras_obj;
2684 if (obj->ras_late_init) {
2685 r = obj->ras_late_init(adev, &obj->ras_comm);
2687 dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n",
2688 obj->ras_comm.name, r);
2692 amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);
2698 /* do some fini work before IP fini as dependence */
2699 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2701 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2703 if (!adev->ras_enabled || !con)
2707 /* Need disable ras on all IPs here before ip [hw/sw]fini */
2708 amdgpu_ras_disable_all_features(adev, 0);
2709 amdgpu_ras_recovery_fini(adev);
2713 int amdgpu_ras_fini(struct amdgpu_device *adev)
2715 struct amdgpu_ras_block_list *ras_node, *tmp;
2716 struct amdgpu_ras_block_object *obj = NULL;
2717 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2719 if (!adev->ras_enabled || !con)
2722 list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) {
2723 if (ras_node->ras_obj) {
2724 obj = ras_node->ras_obj;
2725 if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) &&
2727 obj->ras_fini(adev, &obj->ras_comm);
2729 amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm);
2732 /* Clear ras blocks from ras_list and free ras block list node */
2733 list_del(&ras_node->node);
2737 amdgpu_ras_fs_fini(adev);
2738 amdgpu_ras_interrupt_remove_all(adev);
2740 WARN(con->features, "Feature mask is not cleared");
2743 amdgpu_ras_disable_all_features(adev, 1);
2745 cancel_delayed_work_sync(&con->ras_counte_delay_work);
2747 amdgpu_ras_set_context(adev, NULL);
2753 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2755 amdgpu_ras_check_supported(adev);
2756 if (!adev->ras_hw_enabled)
2759 if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2760 dev_info(adev->dev, "uncorrectable hardware error"
2761 "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
2763 amdgpu_ras_reset_gpu(adev);
2767 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2769 if (adev->asic_type == CHIP_VEGA20 &&
2770 adev->pm.fw_version <= 0x283400) {
2771 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2772 amdgpu_ras_intr_triggered();
2778 void amdgpu_release_ras_context(struct amdgpu_device *adev)
2780 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2785 if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
2786 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
2787 amdgpu_ras_set_context(adev, NULL);
2792 #ifdef CONFIG_X86_MCE_AMD
2793 static struct amdgpu_device *find_adev(uint32_t node_id)
2796 struct amdgpu_device *adev = NULL;
2798 for (i = 0; i < mce_adev_list.num_gpu; i++) {
2799 adev = mce_adev_list.devs[i];
2801 if (adev && adev->gmc.xgmi.connected_to_cpu &&
2802 adev->gmc.xgmi.physical_node_id == node_id)
2810 #define GET_MCA_IPID_GPUID(m) (((m) >> 44) & 0xF)
2811 #define GET_UMC_INST(m) (((m) >> 21) & 0x7)
2812 #define GET_CHAN_INDEX(m) ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4))
2813 #define GPU_ID_OFFSET 8
2815 static int amdgpu_bad_page_notifier(struct notifier_block *nb,
2816 unsigned long val, void *data)
2818 struct mce *m = (struct mce *)data;
2819 struct amdgpu_device *adev = NULL;
2820 uint32_t gpu_id = 0;
2821 uint32_t umc_inst = 0;
2822 uint32_t ch_inst, channel_index = 0;
2823 struct ras_err_data err_data = {0, 0, 0, NULL};
2824 struct eeprom_table_record err_rec;
2825 uint64_t retired_page;
2828 * If the error was generated in UMC_V2, which belongs to GPU UMCs,
2829 * and error occurred in DramECC (Extended error code = 0) then only
2830 * process the error, else bail out.
2832 if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) &&
2833 (XEC(m->status, 0x3f) == 0x0)))
2837 * If it is correctable error, return.
2839 if (mce_is_correctable(m))
2843 * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register.
2845 gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET;
2847 adev = find_adev(gpu_id);
2849 DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__,
2855 * If it is uncorrectable error, then find out UMC instance and
2858 umc_inst = GET_UMC_INST(m->ipid);
2859 ch_inst = GET_CHAN_INDEX(m->ipid);
2861 dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",
2865 * Translate UMC channel address to Physical address
2868 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num
2871 retired_page = ADDR_OF_8KB_BLOCK(m->addr) |
2872 ADDR_OF_256B_BLOCK(channel_index) |
2873 OFFSET_IN_256B_BLOCK(m->addr);
2875 memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
2876 err_data.err_addr = &err_rec;
2877 amdgpu_umc_fill_error_record(&err_data, m->addr,
2878 retired_page, channel_index, umc_inst);
2880 if (amdgpu_bad_page_threshold != 0) {
2881 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
2882 err_data.err_addr_cnt);
2883 amdgpu_ras_save_bad_pages(adev);
2889 static struct notifier_block amdgpu_bad_page_nb = {
2890 .notifier_call = amdgpu_bad_page_notifier,
2891 .priority = MCE_PRIO_UC,
2894 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev)
2897 * Add the adev to the mce_adev_list.
2898 * During mode2 reset, amdgpu device is temporarily
2899 * removed from the mgpu_info list which can cause
2900 * page retirement to fail.
2901 * Use this list instead of mgpu_info to find the amdgpu
2902 * device on which the UMC error was reported.
2904 mce_adev_list.devs[mce_adev_list.num_gpu++] = adev;
2907 * Register the x86 notifier only once
2908 * with MCE subsystem.
2910 if (notifier_registered == false) {
2911 mce_register_decode_chain(&amdgpu_bad_page_nb);
2912 notifier_registered = true;
2917 struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev)
2922 return adev->psp.ras_context.ras;
2925 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con)
2930 adev->psp.ras_context.ras = ras_con;
2934 /* check if ras is supported on block, say, sdma, gfx */
2935 int amdgpu_ras_is_supported(struct amdgpu_device *adev,
2938 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2940 if (block >= AMDGPU_RAS_BLOCK_COUNT)
2942 return ras && (adev->ras_enabled & (1 << block));
2945 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
2947 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2949 if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
2950 schedule_work(&ras->recovery_work);
2955 /* Register each ip ras block into amdgpu ras */
2956 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
2957 struct amdgpu_ras_block_object *ras_block_obj)
2959 struct amdgpu_ras_block_list *ras_node;
2960 if (!adev || !ras_block_obj)
2963 if (!amdgpu_ras_asic_supported(adev))
2966 ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL);
2970 INIT_LIST_HEAD(&ras_node->node);
2971 ras_node->ras_obj = ras_block_obj;
2972 list_add_tail(&ras_node->node, &adev->ras_list);