2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/debugfs.h>
25 #include <linux/list.h>
26 #include <linux/module.h>
27 #include <linux/uaccess.h>
28 #include <linux/reboot.h>
29 #include <linux/syscalls.h>
30 #include <linux/pm_runtime.h>
33 #include "amdgpu_ras.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_xgmi.h"
36 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
38 #ifdef CONFIG_X86_MCE_AMD
41 static bool notifier_registered;
43 static const char *RAS_FS_NAME = "ras";
45 const char *ras_error_string[] = {
49 "multi_uncorrectable",
53 const char *ras_block_string[] = {
73 const char *ras_mca_block_string[] = {
80 struct amdgpu_ras_block_list {
82 struct list_head node;
84 struct amdgpu_ras_block_object *ras_obj;
87 const char *get_ras_block_str(struct ras_common_if *ras_block)
92 if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT)
93 return "OUT OF RANGE";
95 if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)
96 return ras_mca_block_string[ras_block->sub_block_index];
98 return ras_block_string[ras_block->block];
101 #define ras_block_str(_BLOCK_) \
102 (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range")
104 #define ras_err_str(i) (ras_error_string[ffs(i)])
106 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
108 /* inject address is 52 bits */
109 #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52)
111 /* typical ECC bad page rate is 1 bad page per 100MB VRAM */
112 #define RAS_BAD_PAGE_COVER (100 * 1024 * 1024ULL)
114 enum amdgpu_ras_retire_page_reservation {
115 AMDGPU_RAS_RETIRE_PAGE_RESERVED,
116 AMDGPU_RAS_RETIRE_PAGE_PENDING,
117 AMDGPU_RAS_RETIRE_PAGE_FAULT,
120 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
122 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
124 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
126 #ifdef CONFIG_X86_MCE_AMD
127 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev);
128 struct mce_notifier_adev_list {
129 struct amdgpu_device *devs[MAX_GPU_INSTANCE];
132 static struct mce_notifier_adev_list mce_adev_list;
135 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
137 if (adev && amdgpu_ras_get_context(adev))
138 amdgpu_ras_get_context(adev)->error_query_ready = ready;
141 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
143 if (adev && amdgpu_ras_get_context(adev))
144 return amdgpu_ras_get_context(adev)->error_query_ready;
149 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
151 struct ras_err_data err_data = {0, 0, 0, NULL};
152 struct eeprom_table_record err_rec;
154 if ((address >= adev->gmc.mc_vram_size) ||
155 (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
157 "RAS WARN: input address 0x%llx is invalid.\n",
162 if (amdgpu_ras_check_bad_page(adev, address)) {
164 "RAS WARN: 0x%llx has already been marked as bad page!\n",
169 memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
170 err_data.err_addr = &err_rec;
171 amdgpu_umc_fill_error_record(&err_data, address,
172 (address >> AMDGPU_GPU_PAGE_SHIFT), 0, 0);
174 if (amdgpu_bad_page_threshold != 0) {
175 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
176 err_data.err_addr_cnt);
177 amdgpu_ras_save_bad_pages(adev);
180 dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
181 dev_warn(adev->dev, "Clear EEPROM:\n");
182 dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
187 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
188 size_t size, loff_t *pos)
190 struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
191 struct ras_query_if info = {
197 if (amdgpu_ras_query_error_status(obj->adev, &info))
200 s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
202 "ce", info.ce_count);
207 s = min_t(u64, s, size);
210 if (copy_to_user(buf, &val[*pos], s))
218 static const struct file_operations amdgpu_ras_debugfs_ops = {
219 .owner = THIS_MODULE,
220 .read = amdgpu_ras_debugfs_read,
222 .llseek = default_llseek
225 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
229 for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
231 if (strcmp(name, ras_block_string[i]) == 0)
237 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
238 const char __user *buf, size_t size,
239 loff_t *pos, struct ras_debug_if *data)
241 ssize_t s = min_t(u64, 64, size);
254 memset(str, 0, sizeof(str));
255 memset(data, 0, sizeof(*data));
257 if (copy_from_user(str, buf, s))
260 if (sscanf(str, "disable %32s", block_name) == 1)
262 else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
264 else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
266 else if (strstr(str, "retire_page") != NULL)
268 else if (str[0] && str[1] && str[2] && str[3])
269 /* ascii string, but commands are not matched. */
274 if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
275 sscanf(str, "%*s %llu", &address) != 1)
279 data->inject.address = address;
284 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
287 data->head.block = block_id;
288 /* only ue and ce errors are supported */
289 if (!memcmp("ue", err, 2))
290 data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
291 else if (!memcmp("ce", err, 2))
292 data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
299 if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
300 &sub_block, &address, &value) != 3 &&
301 sscanf(str, "%*s %*s %*s %u %llu %llu",
302 &sub_block, &address, &value) != 3)
304 data->head.sub_block_index = sub_block;
305 data->inject.address = address;
306 data->inject.value = value;
309 if (size < sizeof(*data))
312 if (copy_from_user(data, buf, sizeof(*data)))
320 * DOC: AMDGPU RAS debugfs control interface
322 * The control interface accepts struct ras_debug_if which has two members.
324 * First member: ras_debug_if::head or ras_debug_if::inject.
326 * head is used to indicate which IP block will be under control.
328 * head has four members, they are block, type, sub_block_index, name.
329 * block: which IP will be under control.
330 * type: what kind of error will be enabled/disabled/injected.
331 * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
332 * name: the name of IP.
334 * inject has two more members than head, they are address, value.
335 * As their names indicate, inject operation will write the
336 * value to the address.
338 * The second member: struct ras_debug_if::op.
339 * It has three kinds of operations.
341 * - 0: disable RAS on the block. Take ::head as its data.
342 * - 1: enable RAS on the block. Take ::head as its data.
343 * - 2: inject errors on the block. Take ::inject as its data.
345 * How to use the interface?
349 * Copy the struct ras_debug_if in your code and initialize it.
350 * Write the struct to the control interface.
354 * .. code-block:: bash
356 * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
357 * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
358 * echo "inject <block> <error> <sub-block> <address> <value> > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
360 * Where N, is the card which you want to affect.
362 * "disable" requires only the block.
363 * "enable" requires the block and error type.
364 * "inject" requires the block, error type, address, and value.
366 * The block is one of: umc, sdma, gfx, etc.
367 * see ras_block_string[] for details
369 * The error type is one of: ue, ce, where,
370 * ue is multi-uncorrectable
371 * ce is single-correctable
373 * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
374 * The address and value are hexadecimal numbers, leading 0x is optional.
378 * .. code-block:: bash
380 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
381 * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
382 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
384 * How to check the result of the operation?
386 * To check disable/enable, see "ras" features at,
387 * /sys/class/drm/card[0/1/2...]/device/ras/features
389 * To check inject, see the corresponding error count at,
390 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
393 * Operations are only allowed on blocks which are supported.
394 * Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
395 * to see which blocks support RAS on a particular asic.
398 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
399 const char __user *buf,
400 size_t size, loff_t *pos)
402 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
403 struct ras_debug_if data;
406 if (!amdgpu_ras_get_error_query_ready(adev)) {
407 dev_warn(adev->dev, "RAS WARN: error injection "
408 "currently inaccessible\n");
412 ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
417 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
424 if (!amdgpu_ras_is_supported(adev, data.head.block))
429 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
432 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
435 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
436 (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
437 dev_warn(adev->dev, "RAS WARN: input address "
438 "0x%llx is invalid.",
439 data.inject.address);
444 /* umc ce/ue error injection for a bad page is not allowed */
445 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
446 amdgpu_ras_check_bad_page(adev, data.inject.address)) {
447 dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has "
448 "already been marked as bad!\n",
449 data.inject.address);
453 /* data.inject.address is offset instead of absolute gpu address */
454 ret = amdgpu_ras_error_inject(adev, &data.inject);
468 * DOC: AMDGPU RAS debugfs EEPROM table reset interface
470 * Some boards contain an EEPROM which is used to persistently store a list of
471 * bad pages which experiences ECC errors in vram. This interface provides
472 * a way to reset the EEPROM, e.g., after testing error injection.
476 * .. code-block:: bash
478 * echo 1 > ../ras/ras_eeprom_reset
480 * will reset EEPROM table to 0 entries.
483 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
484 const char __user *buf,
485 size_t size, loff_t *pos)
487 struct amdgpu_device *adev =
488 (struct amdgpu_device *)file_inode(f)->i_private;
491 ret = amdgpu_ras_eeprom_reset_table(
492 &(amdgpu_ras_get_context(adev)->eeprom_control));
495 /* Something was written to EEPROM.
497 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
504 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
505 .owner = THIS_MODULE,
507 .write = amdgpu_ras_debugfs_ctrl_write,
508 .llseek = default_llseek
511 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
512 .owner = THIS_MODULE,
514 .write = amdgpu_ras_debugfs_eeprom_write,
515 .llseek = default_llseek
519 * DOC: AMDGPU RAS sysfs Error Count Interface
521 * It allows the user to read the error count for each IP block on the gpu through
522 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
524 * It outputs the multiple lines which report the uncorrected (ue) and corrected
527 * The format of one line is below,
533 * .. code-block:: bash
539 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
540 struct device_attribute *attr, char *buf)
542 struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
543 struct ras_query_if info = {
547 if (!amdgpu_ras_get_error_query_ready(obj->adev))
548 return sysfs_emit(buf, "Query currently inaccessible\n");
550 if (amdgpu_ras_query_error_status(obj->adev, &info))
553 if (obj->adev->asic_type == CHIP_ALDEBARAN) {
554 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
555 DRM_WARN("Failed to reset error counter and error status");
558 return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
559 "ce", info.ce_count);
564 #define get_obj(obj) do { (obj)->use++; } while (0)
565 #define alive_obj(obj) ((obj)->use)
567 static inline void put_obj(struct ras_manager *obj)
569 if (obj && (--obj->use == 0))
570 list_del(&obj->node);
571 if (obj && (obj->use < 0))
572 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head));
575 /* make one obj and return it. */
576 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
577 struct ras_common_if *head)
579 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
580 struct ras_manager *obj;
582 if (!adev->ras_enabled || !con)
585 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
588 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
589 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
592 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
594 obj = &con->objs[head->block];
596 /* already exist. return obj? */
602 list_add(&obj->node, &con->head);
608 /* return an obj equal to head, or the first when head is NULL */
609 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
610 struct ras_common_if *head)
612 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
613 struct ras_manager *obj;
616 if (!adev->ras_enabled || !con)
620 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
623 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
624 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
627 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
629 obj = &con->objs[head->block];
634 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
645 /* feature ctl begin */
646 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
647 struct ras_common_if *head)
649 return adev->ras_hw_enabled & BIT(head->block);
652 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
653 struct ras_common_if *head)
655 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
657 return con->features & BIT(head->block);
661 * if obj is not created, then create one.
662 * set feature enable flag.
664 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
665 struct ras_common_if *head, int enable)
667 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
668 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
670 /* If hardware does not support ras, then do not create obj.
671 * But if hardware support ras, we can create the obj.
672 * Ras framework checks con->hw_supported to see if it need do
673 * corresponding initialization.
674 * IP checks con->support to see if it need disable ras.
676 if (!amdgpu_ras_is_feature_allowed(adev, head))
681 obj = amdgpu_ras_create_obj(adev, head);
685 /* In case we create obj somewhere else */
688 con->features |= BIT(head->block);
690 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
691 con->features &= ~BIT(head->block);
699 /* wrapper of psp_ras_enable_features */
700 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
701 struct ras_common_if *head, bool enable)
703 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
704 union ta_ras_cmd_input *info;
710 info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
715 info->disable_features = (struct ta_ras_disable_features_input) {
716 .block_id = amdgpu_ras_block_to_ta(head->block),
717 .error_type = amdgpu_ras_error_to_ta(head->type),
720 info->enable_features = (struct ta_ras_enable_features_input) {
721 .block_id = amdgpu_ras_block_to_ta(head->block),
722 .error_type = amdgpu_ras_error_to_ta(head->type),
726 /* Do not enable if it is not allowed. */
727 WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
729 /* Only enable ras feature operation handle on host side */
730 if (!amdgpu_sriov_vf(adev) &&
731 !amdgpu_ras_intr_triggered()) {
732 ret = psp_ras_enable_features(&adev->psp, info, enable);
734 dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n",
735 enable ? "enable":"disable",
736 get_ras_block_str(head),
737 amdgpu_ras_is_poison_mode_supported(adev), ret);
743 __amdgpu_ras_feature_enable(adev, head, enable);
750 /* Only used in device probe stage and called only once. */
751 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
752 struct ras_common_if *head, bool enable)
754 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
760 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
762 /* There is no harm to issue a ras TA cmd regardless of
763 * the currecnt ras state.
764 * If current state == target state, it will do nothing
765 * But sometimes it requests driver to reset and repost
766 * with error code -EAGAIN.
768 ret = amdgpu_ras_feature_enable(adev, head, 1);
769 /* With old ras TA, we might fail to enable ras.
770 * Log it and just setup the object.
771 * TODO need remove this WA in the future.
773 if (ret == -EINVAL) {
774 ret = __amdgpu_ras_feature_enable(adev, head, 1);
777 "RAS INFO: %s setup object\n",
778 get_ras_block_str(head));
781 /* setup the object then issue a ras TA disable cmd.*/
782 ret = __amdgpu_ras_feature_enable(adev, head, 1);
786 /* gfx block ras dsiable cmd must send to ras-ta */
787 if (head->block == AMDGPU_RAS_BLOCK__GFX)
788 con->features |= BIT(head->block);
790 ret = amdgpu_ras_feature_enable(adev, head, 0);
792 /* clean gfx block ras features flag */
793 if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
794 con->features &= ~BIT(head->block);
797 ret = amdgpu_ras_feature_enable(adev, head, enable);
802 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
805 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
806 struct ras_manager *obj, *tmp;
808 list_for_each_entry_safe(obj, tmp, &con->head, node) {
810 * aka just release the obj and corresponding flags
813 if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
816 if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
821 return con->features;
824 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
827 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
829 const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE;
831 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
832 struct ras_common_if head = {
834 .type = default_ras_type,
835 .sub_block_index = 0,
838 if (i == AMDGPU_RAS_BLOCK__MCA)
843 * bypass psp. vbios enable ras for us.
844 * so just create the obj
846 if (__amdgpu_ras_feature_enable(adev, &head, 1))
849 if (amdgpu_ras_feature_enable(adev, &head, 1))
854 for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
855 struct ras_common_if head = {
856 .block = AMDGPU_RAS_BLOCK__MCA,
857 .type = default_ras_type,
858 .sub_block_index = i,
863 * bypass psp. vbios enable ras for us.
864 * so just create the obj
866 if (__amdgpu_ras_feature_enable(adev, &head, 1))
869 if (amdgpu_ras_feature_enable(adev, &head, 1))
874 return con->features;
876 /* feature ctl end */
878 static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj,
879 enum amdgpu_ras_block block)
884 if (block_obj->ras_comm.block == block)
890 static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev,
891 enum amdgpu_ras_block block, uint32_t sub_block_index)
893 struct amdgpu_ras_block_list *node, *tmp;
894 struct amdgpu_ras_block_object *obj;
896 if (block >= AMDGPU_RAS_BLOCK__LAST)
899 if (!amdgpu_ras_is_supported(adev, block))
902 list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
903 if (!node->ras_obj) {
904 dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
909 if (obj->ras_block_match) {
910 if (obj->ras_block_match(obj, block, sub_block_index) == 0)
913 if (amdgpu_ras_block_match_default(obj, block) == 0)
921 static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data)
923 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
927 * choosing right query method according to
928 * whether smu support query error information
930 ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc));
931 if (ret == -EOPNOTSUPP) {
932 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
933 adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
934 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
936 /* umc query_ras_error_address is also responsible for clearing
939 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
940 adev->umc.ras->ras_block.hw_ops->query_ras_error_address)
941 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data);
944 adev->umc.ras->ecc_info_query_ras_error_count)
945 adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data);
948 adev->umc.ras->ecc_info_query_ras_error_address)
949 adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data);
953 /* query/inject/cure begin */
954 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
955 struct ras_query_if *info)
957 struct amdgpu_ras_block_object *block_obj = NULL;
958 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
959 struct ras_err_data err_data = {0, 0, 0, NULL};
964 if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {
965 amdgpu_ras_get_ecc_info(adev, &err_data);
967 block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);
968 if (!block_obj || !block_obj->hw_ops) {
969 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
970 get_ras_block_str(&info->head));
974 if (block_obj->hw_ops->query_ras_error_count)
975 block_obj->hw_ops->query_ras_error_count(adev, &err_data);
977 if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||
978 (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||
979 (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {
980 if (block_obj->hw_ops->query_ras_error_status)
981 block_obj->hw_ops->query_ras_error_status(adev);
985 obj->err_data.ue_count += err_data.ue_count;
986 obj->err_data.ce_count += err_data.ce_count;
988 info->ue_count = obj->err_data.ue_count;
989 info->ce_count = obj->err_data.ce_count;
991 if (err_data.ce_count) {
992 if (adev->smuio.funcs &&
993 adev->smuio.funcs->get_socket_id &&
994 adev->smuio.funcs->get_die_id) {
995 dev_info(adev->dev, "socket: %d, die: %d "
996 "%ld correctable hardware errors "
997 "detected in %s block, no user "
998 "action is needed.\n",
999 adev->smuio.funcs->get_socket_id(adev),
1000 adev->smuio.funcs->get_die_id(adev),
1001 obj->err_data.ce_count,
1002 get_ras_block_str(&info->head));
1004 dev_info(adev->dev, "%ld correctable hardware errors "
1005 "detected in %s block, no user "
1006 "action is needed.\n",
1007 obj->err_data.ce_count,
1008 get_ras_block_str(&info->head));
1011 if (err_data.ue_count) {
1012 if (adev->smuio.funcs &&
1013 adev->smuio.funcs->get_socket_id &&
1014 adev->smuio.funcs->get_die_id) {
1015 dev_info(adev->dev, "socket: %d, die: %d "
1016 "%ld uncorrectable hardware errors "
1017 "detected in %s block\n",
1018 adev->smuio.funcs->get_socket_id(adev),
1019 adev->smuio.funcs->get_die_id(adev),
1020 obj->err_data.ue_count,
1021 get_ras_block_str(&info->head));
1023 dev_info(adev->dev, "%ld uncorrectable hardware errors "
1024 "detected in %s block\n",
1025 obj->err_data.ue_count,
1026 get_ras_block_str(&info->head));
1030 if (!amdgpu_persistent_edc_harvesting_supported(adev))
1031 amdgpu_ras_reset_error_status(adev, info->head.block);
1036 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
1037 enum amdgpu_ras_block block)
1039 struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1041 if (!amdgpu_ras_is_supported(adev, block))
1044 if (!block_obj || !block_obj->hw_ops) {
1045 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1046 ras_block_str(block));
1050 if (block_obj->hw_ops->reset_ras_error_count)
1051 block_obj->hw_ops->reset_ras_error_count(adev);
1053 if ((block == AMDGPU_RAS_BLOCK__GFX) ||
1054 (block == AMDGPU_RAS_BLOCK__MMHUB)) {
1055 if (block_obj->hw_ops->reset_ras_error_status)
1056 block_obj->hw_ops->reset_ras_error_status(adev);
1062 /* wrapper of psp_ras_trigger_error */
1063 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
1064 struct ras_inject_if *info)
1066 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1067 struct ta_ras_trigger_error_input block_info = {
1068 .block_id = amdgpu_ras_block_to_ta(info->head.block),
1069 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
1070 .sub_block_index = info->head.sub_block_index,
1071 .address = info->address,
1072 .value = info->value,
1075 struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev,
1077 info->head.sub_block_index);
1082 if (!block_obj || !block_obj->hw_ops) {
1083 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1084 get_ras_block_str(&info->head));
1088 /* Calculate XGMI relative offset */
1089 if (adev->gmc.xgmi.num_physical_nodes > 1) {
1090 block_info.address =
1091 amdgpu_xgmi_get_relative_phy_addr(adev,
1092 block_info.address);
1095 if (info->head.block == AMDGPU_RAS_BLOCK__GFX) {
1096 if (block_obj->hw_ops->ras_error_inject)
1097 ret = block_obj->hw_ops->ras_error_inject(adev, info);
1099 /* If defined special ras_error_inject(e.g: xgmi), implement special ras_error_inject */
1100 if (block_obj->hw_ops->ras_error_inject)
1101 ret = block_obj->hw_ops->ras_error_inject(adev, &block_info);
1102 else /*If not defined .ras_error_inject, use default ras_error_inject*/
1103 ret = psp_ras_trigger_error(&adev->psp, &block_info);
1107 dev_err(adev->dev, "ras inject %s failed %d\n",
1108 get_ras_block_str(&info->head), ret);
1114 * amdgpu_ras_query_error_count -- Get error counts of all IPs
1115 * @adev: pointer to AMD GPU device
1116 * @ce_count: pointer to an integer to be set to the count of correctible errors.
1117 * @ue_count: pointer to an integer to be set to the count of uncorrectible
1120 * If set, @ce_count or @ue_count, count and return the corresponding
1121 * error counts in those integer pointers. Return 0 if the device
1122 * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
1124 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1125 unsigned long *ce_count,
1126 unsigned long *ue_count)
1128 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1129 struct ras_manager *obj;
1130 unsigned long ce, ue;
1132 if (!adev->ras_enabled || !con)
1135 /* Don't count since no reporting.
1137 if (!ce_count && !ue_count)
1142 list_for_each_entry(obj, &con->head, node) {
1143 struct ras_query_if info = {
1148 res = amdgpu_ras_query_error_status(adev, &info);
1152 ce += info.ce_count;
1153 ue += info.ue_count;
1164 /* query/inject/cure end */
1169 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1170 struct ras_badpage **bps, unsigned int *count);
1172 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1175 case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1177 case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1179 case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1186 * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1188 * It allows user to read the bad pages of vram on the gpu through
1189 * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1191 * It outputs multiple lines, and each line stands for one gpu page.
1193 * The format of one line is below,
1194 * gpu pfn : gpu page size : flags
1196 * gpu pfn and gpu page size are printed in hex format.
1197 * flags can be one of below character,
1199 * R: reserved, this gpu page is reserved and not able to use.
1201 * P: pending for reserve, this gpu page is marked as bad, will be reserved
1202 * in next window of page_reserve.
1204 * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1208 * .. code-block:: bash
1210 * 0x00000001 : 0x00001000 : R
1211 * 0x00000002 : 0x00001000 : P
1215 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1216 struct kobject *kobj, struct bin_attribute *attr,
1217 char *buf, loff_t ppos, size_t count)
1219 struct amdgpu_ras *con =
1220 container_of(attr, struct amdgpu_ras, badpages_attr);
1221 struct amdgpu_device *adev = con->adev;
1222 const unsigned int element_size =
1223 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1224 unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1225 unsigned int end = div64_ul(ppos + count - 1, element_size);
1227 struct ras_badpage *bps = NULL;
1228 unsigned int bps_count = 0;
1230 memset(buf, 0, count);
1232 if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1235 for (; start < end && start < bps_count; start++)
1236 s += scnprintf(&buf[s], element_size + 1,
1237 "0x%08x : 0x%08x : %1s\n",
1240 amdgpu_ras_badpage_flags_str(bps[start].flags));
1247 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1248 struct device_attribute *attr, char *buf)
1250 struct amdgpu_ras *con =
1251 container_of(attr, struct amdgpu_ras, features_attr);
1253 return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
1256 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1258 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1260 sysfs_remove_file_from_group(&adev->dev->kobj,
1261 &con->badpages_attr.attr,
1265 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1267 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1268 struct attribute *attrs[] = {
1269 &con->features_attr.attr,
1272 struct attribute_group group = {
1273 .name = RAS_FS_NAME,
1277 sysfs_remove_group(&adev->dev->kobj, &group);
1282 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1283 struct ras_common_if *head)
1285 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1287 if (!obj || obj->attr_inuse)
1292 snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name),
1293 "%s_err_count", head->name);
1295 obj->sysfs_attr = (struct device_attribute){
1297 .name = obj->fs_data.sysfs_name,
1300 .show = amdgpu_ras_sysfs_read,
1302 sysfs_attr_init(&obj->sysfs_attr.attr);
1304 if (sysfs_add_file_to_group(&adev->dev->kobj,
1305 &obj->sysfs_attr.attr,
1311 obj->attr_inuse = 1;
1316 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1317 struct ras_common_if *head)
1319 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1321 if (!obj || !obj->attr_inuse)
1324 sysfs_remove_file_from_group(&adev->dev->kobj,
1325 &obj->sysfs_attr.attr,
1327 obj->attr_inuse = 0;
1333 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1335 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1336 struct ras_manager *obj, *tmp;
1338 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1339 amdgpu_ras_sysfs_remove(adev, &obj->head);
1342 if (amdgpu_bad_page_threshold != 0)
1343 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1345 amdgpu_ras_sysfs_remove_feature_node(adev);
1352 * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1354 * Normally when there is an uncorrectable error, the driver will reset
1355 * the GPU to recover. However, in the event of an unrecoverable error,
1356 * the driver provides an interface to reboot the system automatically
1359 * The following file in debugfs provides that interface:
1360 * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1364 * .. code-block:: bash
1366 * echo true > .../ras/auto_reboot
1370 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1372 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1373 struct drm_minor *minor = adev_to_drm(adev)->primary;
1376 dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1377 debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1378 &amdgpu_ras_debugfs_ctrl_ops);
1379 debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1380 &amdgpu_ras_debugfs_eeprom_ops);
1381 debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1382 &con->bad_page_cnt_threshold);
1383 debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
1384 debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
1385 debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
1386 &amdgpu_ras_debugfs_eeprom_size_ops);
1387 con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",
1389 &amdgpu_ras_debugfs_eeprom_table_ops);
1390 amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);
1393 * After one uncorrectable error happens, usually GPU recovery will
1394 * be scheduled. But due to the known problem in GPU recovery failing
1395 * to bring GPU back, below interface provides one direct way to
1396 * user to reboot system automatically in such case within
1397 * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1398 * will never be called.
1400 debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1403 * User could set this not to clean up hardware's error count register
1404 * of RAS IPs during ras recovery.
1406 debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1407 &con->disable_ras_err_cnt_harvest);
1411 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1412 struct ras_fs_if *head,
1415 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1422 memcpy(obj->fs_data.debugfs_name,
1424 sizeof(obj->fs_data.debugfs_name));
1426 debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1427 obj, &amdgpu_ras_debugfs_ops);
1430 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1432 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1434 struct ras_manager *obj;
1435 struct ras_fs_if fs_info;
1438 * it won't be called in resume path, no need to check
1439 * suspend and gpu reset status
1441 if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1444 dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1446 list_for_each_entry(obj, &con->head, node) {
1447 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1448 (obj->attr_inuse == 1)) {
1449 sprintf(fs_info.debugfs_name, "%s_err_inject",
1450 get_ras_block_str(&obj->head));
1451 fs_info.head = obj->head;
1452 amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1460 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1461 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1462 static DEVICE_ATTR(features, S_IRUGO,
1463 amdgpu_ras_sysfs_features_read, NULL);
1464 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1466 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1467 struct attribute_group group = {
1468 .name = RAS_FS_NAME,
1470 struct attribute *attrs[] = {
1471 &con->features_attr.attr,
1474 struct bin_attribute *bin_attrs[] = {
1480 /* add features entry */
1481 con->features_attr = dev_attr_features;
1482 group.attrs = attrs;
1483 sysfs_attr_init(attrs[0]);
1485 if (amdgpu_bad_page_threshold != 0) {
1486 /* add bad_page_features entry */
1487 bin_attr_gpu_vram_bad_pages.private = NULL;
1488 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1489 bin_attrs[0] = &con->badpages_attr;
1490 group.bin_attrs = bin_attrs;
1491 sysfs_bin_attr_init(bin_attrs[0]);
1494 r = sysfs_create_group(&adev->dev->kobj, &group);
1496 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1501 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1503 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1504 struct ras_manager *con_obj, *ip_obj, *tmp;
1506 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1507 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1508 ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1514 amdgpu_ras_sysfs_remove_all(adev);
1521 /* For the hardware that cannot enable bif ring for both ras_controller_irq
1522 * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
1523 * register to check whether the interrupt is triggered or not, and properly
1524 * ack the interrupt if it is there
1526 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev)
1528 /* Fatal error events are handled on host side */
1529 if (amdgpu_sriov_vf(adev) ||
1530 !amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF))
1533 if (adev->nbio.ras &&
1534 adev->nbio.ras->handle_ras_controller_intr_no_bifring)
1535 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev);
1537 if (adev->nbio.ras &&
1538 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring)
1539 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev);
1542 static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj,
1543 struct amdgpu_iv_entry *entry)
1545 bool poison_stat = false;
1546 struct amdgpu_device *adev = obj->adev;
1547 struct ras_err_data err_data = {0, 0, 0, NULL};
1548 struct amdgpu_ras_block_object *block_obj =
1549 amdgpu_ras_get_ras_block(adev, obj->head.block, 0);
1551 if (!block_obj || !block_obj->hw_ops)
1554 /* both query_poison_status and handle_poison_consumption are optional,
1555 * but at least one of them should be implemented if we need poison
1556 * consumption handler
1558 if (block_obj->hw_ops->query_poison_status) {
1559 poison_stat = block_obj->hw_ops->query_poison_status(adev);
1561 /* Not poison consumption interrupt, no need to handle it */
1562 dev_info(adev->dev, "No RAS poison status in %s poison IH.\n",
1563 block_obj->ras_comm.name);
1569 if (!adev->gmc.xgmi.connected_to_cpu)
1570 amdgpu_umc_poison_handler(adev, &err_data, false);
1572 if (block_obj->hw_ops->handle_poison_consumption)
1573 poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);
1575 /* gpu reset is fallback for failed and default cases */
1577 dev_info(adev->dev, "GPU reset for %s RAS poison consumption is issued!\n",
1578 block_obj->ras_comm.name);
1579 amdgpu_ras_reset_gpu(adev);
1583 static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj,
1584 struct amdgpu_iv_entry *entry)
1586 dev_info(obj->adev->dev,
1587 "Poison is created, no user action is needed.\n");
1590 static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj,
1591 struct amdgpu_iv_entry *entry)
1593 struct ras_ih_data *data = &obj->ih_data;
1594 struct ras_err_data err_data = {0, 0, 0, NULL};
1600 /* Let IP handle its data, maybe we need get the output
1601 * from the callback to update the error type/count, etc
1603 ret = data->cb(obj->adev, &err_data, entry);
1604 /* ue will trigger an interrupt, and in that case
1605 * we need do a reset to recovery the whole system.
1606 * But leave IP do that recovery, here we just dispatch
1609 if (ret == AMDGPU_RAS_SUCCESS) {
1610 /* these counts could be left as 0 if
1611 * some blocks do not count error number
1613 obj->err_data.ue_count += err_data.ue_count;
1614 obj->err_data.ce_count += err_data.ce_count;
1618 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1620 struct ras_ih_data *data = &obj->ih_data;
1621 struct amdgpu_iv_entry entry;
1623 while (data->rptr != data->wptr) {
1625 memcpy(&entry, &data->ring[data->rptr],
1626 data->element_size);
1629 data->rptr = (data->aligned_element_size +
1630 data->rptr) % data->ring_size;
1632 if (amdgpu_ras_is_poison_mode_supported(obj->adev)) {
1633 if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1634 amdgpu_ras_interrupt_poison_creation_handler(obj, &entry);
1636 amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry);
1638 if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1639 amdgpu_ras_interrupt_umc_handler(obj, &entry);
1641 dev_warn(obj->adev->dev,
1642 "No RAS interrupt handler for non-UMC block with poison disabled.\n");
1647 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1649 struct ras_ih_data *data =
1650 container_of(work, struct ras_ih_data, ih_work);
1651 struct ras_manager *obj =
1652 container_of(data, struct ras_manager, ih_data);
1654 amdgpu_ras_interrupt_handler(obj);
1657 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1658 struct ras_dispatch_if *info)
1660 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1661 struct ras_ih_data *data = &obj->ih_data;
1666 if (data->inuse == 0)
1669 /* Might be overflow... */
1670 memcpy(&data->ring[data->wptr], info->entry,
1671 data->element_size);
1674 data->wptr = (data->aligned_element_size +
1675 data->wptr) % data->ring_size;
1677 schedule_work(&data->ih_work);
1682 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1683 struct ras_common_if *head)
1685 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1686 struct ras_ih_data *data;
1691 data = &obj->ih_data;
1692 if (data->inuse == 0)
1695 cancel_work_sync(&data->ih_work);
1698 memset(data, 0, sizeof(*data));
1704 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1705 struct ras_common_if *head)
1707 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1708 struct ras_ih_data *data;
1709 struct amdgpu_ras_block_object *ras_obj;
1712 /* in case we registe the IH before enable ras feature */
1713 obj = amdgpu_ras_create_obj(adev, head);
1719 ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm);
1721 data = &obj->ih_data;
1722 /* add the callback.etc */
1723 *data = (struct ras_ih_data) {
1725 .cb = ras_obj->ras_cb,
1726 .element_size = sizeof(struct amdgpu_iv_entry),
1731 INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1733 data->aligned_element_size = ALIGN(data->element_size, 8);
1734 /* the ring can store 64 iv entries. */
1735 data->ring_size = 64 * data->aligned_element_size;
1736 data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1748 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1750 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1751 struct ras_manager *obj, *tmp;
1753 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1754 amdgpu_ras_interrupt_remove_handler(adev, &obj->head);
1761 /* traversal all IPs except NBIO to query error counter */
1762 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1764 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1765 struct ras_manager *obj;
1767 if (!adev->ras_enabled || !con)
1770 list_for_each_entry(obj, &con->head, node) {
1771 struct ras_query_if info = {
1776 * PCIE_BIF IP has one different isr by ras controller
1777 * interrupt, the specific ras counter query will be
1778 * done in that isr. So skip such block from common
1779 * sync flood interrupt isr calling.
1781 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1785 * this is a workaround for aldebaran, skip send msg to
1786 * smu to get ecc_info table due to smu handle get ecc
1787 * info table failed temporarily.
1788 * should be removed until smu fix handle ecc_info table.
1790 if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) &&
1791 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)))
1794 amdgpu_ras_query_error_status(adev, &info);
1798 /* Parse RdRspStatus and WrRspStatus */
1799 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1800 struct ras_query_if *info)
1802 struct amdgpu_ras_block_object *block_obj;
1804 * Only two block need to query read/write
1805 * RspStatus at current state
1807 if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) &&
1808 (info->head.block != AMDGPU_RAS_BLOCK__MMHUB))
1811 block_obj = amdgpu_ras_get_ras_block(adev,
1813 info->head.sub_block_index);
1815 if (!block_obj || !block_obj->hw_ops) {
1816 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1817 get_ras_block_str(&info->head));
1821 if (block_obj->hw_ops->query_ras_error_status)
1822 block_obj->hw_ops->query_ras_error_status(adev);
1826 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1828 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1829 struct ras_manager *obj;
1831 if (!adev->ras_enabled || !con)
1834 list_for_each_entry(obj, &con->head, node) {
1835 struct ras_query_if info = {
1839 amdgpu_ras_error_status_query(adev, &info);
1843 /* recovery begin */
1845 /* return 0 on success.
1846 * caller need free bps.
1848 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1849 struct ras_badpage **bps, unsigned int *count)
1851 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1852 struct ras_err_handler_data *data;
1854 int ret = 0, status;
1856 if (!con || !con->eh_data || !bps || !count)
1859 mutex_lock(&con->recovery_lock);
1860 data = con->eh_data;
1861 if (!data || data->count == 0) {
1867 *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1873 for (; i < data->count; i++) {
1874 (*bps)[i] = (struct ras_badpage){
1875 .bp = data->bps[i].retired_page,
1876 .size = AMDGPU_GPU_PAGE_SIZE,
1877 .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
1879 status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr,
1880 data->bps[i].retired_page);
1881 if (status == -EBUSY)
1882 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1883 else if (status == -ENOENT)
1884 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
1887 *count = data->count;
1889 mutex_unlock(&con->recovery_lock);
1893 static void amdgpu_ras_do_recovery(struct work_struct *work)
1895 struct amdgpu_ras *ras =
1896 container_of(work, struct amdgpu_ras, recovery_work);
1897 struct amdgpu_device *remote_adev = NULL;
1898 struct amdgpu_device *adev = ras->adev;
1899 struct list_head device_list, *device_list_handle = NULL;
1901 if (!ras->disable_ras_err_cnt_harvest) {
1902 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
1904 /* Build list of devices to query RAS related errors */
1905 if (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
1906 device_list_handle = &hive->device_list;
1908 INIT_LIST_HEAD(&device_list);
1909 list_add_tail(&adev->gmc.xgmi.head, &device_list);
1910 device_list_handle = &device_list;
1913 list_for_each_entry(remote_adev,
1914 device_list_handle, gmc.xgmi.head) {
1915 amdgpu_ras_query_err_status(remote_adev);
1916 amdgpu_ras_log_on_err_counter(remote_adev);
1919 amdgpu_put_xgmi_hive(hive);
1922 if (amdgpu_device_should_recover_gpu(ras->adev))
1923 amdgpu_device_gpu_recover(ras->adev, NULL);
1924 atomic_set(&ras->in_recovery, 0);
1927 /* alloc/realloc bps array */
1928 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1929 struct ras_err_handler_data *data, int pages)
1931 unsigned int old_space = data->count + data->space_left;
1932 unsigned int new_space = old_space + pages;
1933 unsigned int align_space = ALIGN(new_space, 512);
1934 void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1941 memcpy(bps, data->bps,
1942 data->count * sizeof(*data->bps));
1947 data->space_left += align_space - old_space;
1951 /* it deal with vram only. */
1952 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1953 struct eeprom_table_record *bps, int pages)
1955 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1956 struct ras_err_handler_data *data;
1960 if (!con || !con->eh_data || !bps || pages <= 0)
1963 mutex_lock(&con->recovery_lock);
1964 data = con->eh_data;
1968 for (i = 0; i < pages; i++) {
1969 if (amdgpu_ras_check_bad_page_unlock(con,
1970 bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
1973 if (!data->space_left &&
1974 amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
1979 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr,
1980 bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
1981 AMDGPU_GPU_PAGE_SIZE);
1983 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
1988 mutex_unlock(&con->recovery_lock);
1994 * write error record array to eeprom, the function should be
1995 * protected by recovery_lock
1997 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1999 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2000 struct ras_err_handler_data *data;
2001 struct amdgpu_ras_eeprom_control *control;
2004 if (!con || !con->eh_data)
2007 mutex_lock(&con->recovery_lock);
2008 control = &con->eeprom_control;
2009 data = con->eh_data;
2010 save_count = data->count - control->ras_num_recs;
2011 mutex_unlock(&con->recovery_lock);
2012 /* only new entries are saved */
2013 if (save_count > 0) {
2014 if (amdgpu_ras_eeprom_append(control,
2015 &data->bps[control->ras_num_recs],
2017 dev_err(adev->dev, "Failed to save EEPROM table data!");
2021 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
2028 * read error record array in eeprom and reserve enough space for
2029 * storing new bad pages
2031 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
2033 struct amdgpu_ras_eeprom_control *control =
2034 &adev->psp.ras_context.ras->eeprom_control;
2035 struct eeprom_table_record *bps;
2038 /* no bad page record, skip eeprom access */
2039 if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)
2042 bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL);
2046 ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs);
2048 dev_err(adev->dev, "Failed to load EEPROM table records!");
2050 ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs);
2056 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
2059 struct ras_err_handler_data *data = con->eh_data;
2062 addr >>= AMDGPU_GPU_PAGE_SHIFT;
2063 for (i = 0; i < data->count; i++)
2064 if (addr == data->bps[i].retired_page)
2071 * check if an address belongs to bad page
2073 * Note: this check is only for umc block
2075 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
2078 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2081 if (!con || !con->eh_data)
2084 mutex_lock(&con->recovery_lock);
2085 ret = amdgpu_ras_check_bad_page_unlock(con, addr);
2086 mutex_unlock(&con->recovery_lock);
2090 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
2093 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2096 * Justification of value bad_page_cnt_threshold in ras structure
2098 * Generally, -1 <= amdgpu_bad_page_threshold <= max record length
2099 * in eeprom, and introduce two scenarios accordingly.
2101 * Bad page retirement enablement:
2102 * - If amdgpu_bad_page_threshold = -1,
2103 * bad_page_cnt_threshold = typical value by formula.
2105 * - When the value from user is 0 < amdgpu_bad_page_threshold <
2106 * max record length in eeprom, use it directly.
2108 * Bad page retirement disablement:
2109 * - If amdgpu_bad_page_threshold = 0, bad page retirement
2110 * functionality is disabled, and bad_page_cnt_threshold will
2114 if (amdgpu_bad_page_threshold < 0) {
2115 u64 val = adev->gmc.mc_vram_size;
2117 do_div(val, RAS_BAD_PAGE_COVER);
2118 con->bad_page_cnt_threshold = min(lower_32_bits(val),
2121 con->bad_page_cnt_threshold = min_t(int, max_count,
2122 amdgpu_bad_page_threshold);
2126 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
2128 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2129 struct ras_err_handler_data **data;
2130 u32 max_eeprom_records_count = 0;
2131 bool exc_err_limit = false;
2137 /* Allow access to RAS EEPROM via debugfs, when the ASIC
2138 * supports RAS and debugfs is enabled, but when
2139 * adev->ras_enabled is unset, i.e. when "ras_enable"
2140 * module parameter is set to 0.
2144 if (!adev->ras_enabled)
2147 data = &con->eh_data;
2148 *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
2154 mutex_init(&con->recovery_lock);
2155 INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
2156 atomic_set(&con->in_recovery, 0);
2157 con->eeprom_control.bad_channel_bitmap = 0;
2159 max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count();
2160 amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
2162 /* Todo: During test the SMU might fail to read the eeprom through I2C
2163 * when the GPU is pending on XGMI reset during probe time
2164 * (Mostly after second bus reset), skip it now
2166 if (adev->gmc.xgmi.pending_reset)
2168 ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
2170 * This calling fails when exc_err_limit is true or
2173 if (exc_err_limit || ret)
2176 if (con->eeprom_control.ras_num_recs) {
2177 ret = amdgpu_ras_load_bad_pages(adev);
2181 amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
2183 if (con->update_channel_flag == true) {
2184 amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap);
2185 con->update_channel_flag = false;
2189 #ifdef CONFIG_X86_MCE_AMD
2190 if ((adev->asic_type == CHIP_ALDEBARAN) &&
2191 (adev->gmc.xgmi.connected_to_cpu))
2192 amdgpu_register_bad_pages_mca_notifier(adev);
2197 kfree((*data)->bps);
2199 con->eh_data = NULL;
2201 dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);
2204 * Except error threshold exceeding case, other failure cases in this
2205 * function would not fail amdgpu driver init.
2215 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2217 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2218 struct ras_err_handler_data *data = con->eh_data;
2220 /* recovery_init failed to init it, fini is useless */
2224 cancel_work_sync(&con->recovery_work);
2226 mutex_lock(&con->recovery_lock);
2227 con->eh_data = NULL;
2230 mutex_unlock(&con->recovery_lock);
2236 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2238 return adev->asic_type == CHIP_VEGA10 ||
2239 adev->asic_type == CHIP_VEGA20 ||
2240 adev->asic_type == CHIP_ARCTURUS ||
2241 adev->asic_type == CHIP_ALDEBARAN ||
2242 adev->asic_type == CHIP_SIENNA_CICHLID;
2246 * this is workaround for vega20 workstation sku,
2247 * force enable gfx ras, ignore vbios gfx ras flag
2248 * due to GC EDC can not write
2250 static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
2252 struct atom_context *ctx = adev->mode_info.atom_context;
2257 if (strnstr(ctx->vbios_version, "D16406",
2258 sizeof(ctx->vbios_version)) ||
2259 strnstr(ctx->vbios_version, "D36002",
2260 sizeof(ctx->vbios_version)))
2261 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
2265 * check hardware's ras ability which will be saved in hw_supported.
2266 * if hardware does not support ras, we can skip some ras initializtion and
2267 * forbid some ras operations from IP.
2268 * if software itself, say boot parameter, limit the ras ability. We still
2269 * need allow IP do some limited operations, like disable. In such case,
2270 * we have to initialize ras as normal. but need check if operation is
2271 * allowed or not in each function.
2273 static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
2275 adev->ras_hw_enabled = adev->ras_enabled = 0;
2277 if (!adev->is_atom_fw ||
2278 !amdgpu_ras_asic_supported(adev))
2281 if (!(amdgpu_sriov_vf(adev) &&
2282 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2))))
2285 if (!adev->gmc.xgmi.connected_to_cpu) {
2286 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2287 dev_info(adev->dev, "MEM ECC is active.\n");
2288 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
2289 1 << AMDGPU_RAS_BLOCK__DF);
2291 dev_info(adev->dev, "MEM ECC is not presented.\n");
2294 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2295 dev_info(adev->dev, "SRAM ECC is active.\n");
2296 if (!amdgpu_sriov_vf(adev)) {
2297 adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2298 1 << AMDGPU_RAS_BLOCK__DF);
2300 if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(2, 6, 0))
2301 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN |
2302 1 << AMDGPU_RAS_BLOCK__JPEG);
2304 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN |
2305 1 << AMDGPU_RAS_BLOCK__JPEG);
2307 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF |
2308 1 << AMDGPU_RAS_BLOCK__SDMA |
2309 1 << AMDGPU_RAS_BLOCK__GFX);
2312 dev_info(adev->dev, "SRAM ECC is not presented.\n");
2315 /* driver only manages a few IP blocks RAS feature
2316 * when GPU is connected cpu through XGMI */
2317 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
2318 1 << AMDGPU_RAS_BLOCK__SDMA |
2319 1 << AMDGPU_RAS_BLOCK__MMHUB);
2322 amdgpu_ras_get_quirks(adev);
2324 /* hw_supported needs to be aligned with RAS block mask. */
2325 adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
2327 adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
2328 adev->ras_hw_enabled & amdgpu_ras_mask;
2331 static void amdgpu_ras_counte_dw(struct work_struct *work)
2333 struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
2334 ras_counte_delay_work.work);
2335 struct amdgpu_device *adev = con->adev;
2336 struct drm_device *dev = adev_to_drm(adev);
2337 unsigned long ce_count, ue_count;
2340 res = pm_runtime_get_sync(dev->dev);
2344 /* Cache new values.
2346 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) {
2347 atomic_set(&con->ras_ce_count, ce_count);
2348 atomic_set(&con->ras_ue_count, ue_count);
2351 pm_runtime_mark_last_busy(dev->dev);
2353 pm_runtime_put_autosuspend(dev->dev);
2356 int amdgpu_ras_init(struct amdgpu_device *adev)
2358 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2360 bool df_poison, umc_poison;
2365 con = kmalloc(sizeof(struct amdgpu_ras) +
2366 sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT +
2367 sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT,
2368 GFP_KERNEL|__GFP_ZERO);
2373 INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
2374 atomic_set(&con->ras_ce_count, 0);
2375 atomic_set(&con->ras_ue_count, 0);
2377 con->objs = (struct ras_manager *)(con + 1);
2379 amdgpu_ras_set_context(adev, con);
2381 amdgpu_ras_check_supported(adev);
2383 if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
2384 /* set gfx block ras context feature for VEGA20 Gaming
2385 * send ras disable cmd to ras ta during ras late init.
2387 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
2388 con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2397 con->update_channel_flag = false;
2399 INIT_LIST_HEAD(&con->head);
2400 /* Might need get this flag from vbios. */
2401 con->flags = RAS_DEFAULT_FLAGS;
2403 /* initialize nbio ras function ahead of any other
2404 * ras functions so hardware fatal error interrupt
2405 * can be enabled as early as possible */
2406 switch (adev->asic_type) {
2409 case CHIP_ALDEBARAN:
2410 if (!adev->gmc.xgmi.connected_to_cpu) {
2411 adev->nbio.ras = &nbio_v7_4_ras;
2412 amdgpu_ras_register_ras_block(adev, &adev->nbio.ras->ras_block);
2413 adev->nbio.ras_if = &adev->nbio.ras->ras_block.ras_comm;
2417 /* nbio ras is not available */
2421 if (adev->nbio.ras &&
2422 adev->nbio.ras->init_ras_controller_interrupt) {
2423 r = adev->nbio.ras->init_ras_controller_interrupt(adev);
2428 if (adev->nbio.ras &&
2429 adev->nbio.ras->init_ras_err_event_athub_interrupt) {
2430 r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev);
2435 /* Init poison supported flag, the default value is false */
2436 if (adev->gmc.xgmi.connected_to_cpu) {
2437 /* enabled by default when GPU is connected to CPU */
2438 con->poison_supported = true;
2440 else if (adev->df.funcs &&
2441 adev->df.funcs->query_ras_poison_mode &&
2443 adev->umc.ras->query_ras_poison_mode) {
2445 adev->df.funcs->query_ras_poison_mode(adev);
2447 adev->umc.ras->query_ras_poison_mode(adev);
2448 /* Only poison is set in both DF and UMC, we can support it */
2449 if (df_poison && umc_poison)
2450 con->poison_supported = true;
2451 else if (df_poison != umc_poison)
2452 dev_warn(adev->dev, "Poison setting is inconsistent in DF/UMC(%d:%d)!\n",
2453 df_poison, umc_poison);
2456 if (amdgpu_ras_fs_init(adev)) {
2461 dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2462 "hardware ability[%x] ras_mask[%x]\n",
2463 adev->ras_hw_enabled, adev->ras_enabled);
2467 amdgpu_ras_set_context(adev, NULL);
2473 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2475 if (adev->gmc.xgmi.connected_to_cpu)
2480 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2481 struct ras_common_if *ras_block)
2483 struct ras_query_if info = {
2487 if (!amdgpu_persistent_edc_harvesting_supported(adev))
2490 if (amdgpu_ras_query_error_status(adev, &info) != 0)
2491 DRM_WARN("RAS init harvest failure");
2493 if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2494 DRM_WARN("RAS init harvest reset failure");
2499 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev)
2501 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2506 return con->poison_supported;
2509 /* helper function to handle common stuff in ip late init phase */
2510 int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
2511 struct ras_common_if *ras_block)
2513 struct amdgpu_ras_block_object *ras_obj = NULL;
2514 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2515 unsigned long ue_count, ce_count;
2518 /* disable RAS feature per IP block if it is not supported */
2519 if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2520 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2524 r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2526 if (adev->in_suspend || amdgpu_in_reset(adev)) {
2527 /* in resume phase, if fail to enable ras,
2528 * clean up all ras fs nodes, and disable ras */
2534 /* check for errors on warm reset edc persisant supported ASIC */
2535 amdgpu_persistent_edc_harvesting(adev, ras_block);
2537 /* in resume phase, no need to create ras fs node */
2538 if (adev->in_suspend || amdgpu_in_reset(adev))
2541 ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
2542 if (ras_obj->ras_cb || (ras_obj->hw_ops &&
2543 (ras_obj->hw_ops->query_poison_status ||
2544 ras_obj->hw_ops->handle_poison_consumption))) {
2545 r = amdgpu_ras_interrupt_add_handler(adev, ras_block);
2550 r = amdgpu_ras_sysfs_create(adev, ras_block);
2554 /* Those are the cached values at init.
2556 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) {
2557 atomic_set(&con->ras_ce_count, ce_count);
2558 atomic_set(&con->ras_ue_count, ue_count);
2564 if (ras_obj->ras_cb)
2565 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
2567 amdgpu_ras_feature_enable(adev, ras_block, 0);
2571 static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
2572 struct ras_common_if *ras_block)
2574 return amdgpu_ras_block_late_init(adev, ras_block);
2577 /* helper function to remove ras fs node and interrupt handler */
2578 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
2579 struct ras_common_if *ras_block)
2581 struct amdgpu_ras_block_object *ras_obj;
2585 amdgpu_ras_sysfs_remove(adev, ras_block);
2587 ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
2588 if (ras_obj->ras_cb)
2589 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
2592 static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev,
2593 struct ras_common_if *ras_block)
2595 return amdgpu_ras_block_late_fini(adev, ras_block);
2598 /* do some init work after IP late init as dependence.
2599 * and it runs in resume/gpu reset/booting up cases.
2601 void amdgpu_ras_resume(struct amdgpu_device *adev)
2603 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2604 struct ras_manager *obj, *tmp;
2606 if (!adev->ras_enabled || !con) {
2607 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2608 amdgpu_release_ras_context(adev);
2613 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2614 /* Set up all other IPs which are not implemented. There is a
2615 * tricky thing that IP's actual ras error type should be
2616 * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2617 * ERROR_NONE make sense anyway.
2619 amdgpu_ras_enable_all_features(adev, 1);
2621 /* We enable ras on all hw_supported block, but as boot
2622 * parameter might disable some of them and one or more IP has
2623 * not implemented yet. So we disable them on behalf.
2625 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2626 if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2627 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2628 /* there should be no any reference. */
2629 WARN_ON(alive_obj(obj));
2635 void amdgpu_ras_suspend(struct amdgpu_device *adev)
2637 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2639 if (!adev->ras_enabled || !con)
2642 amdgpu_ras_disable_all_features(adev, 0);
2643 /* Make sure all ras objects are disabled. */
2645 amdgpu_ras_disable_all_features(adev, 1);
2648 int amdgpu_ras_late_init(struct amdgpu_device *adev)
2650 struct amdgpu_ras_block_list *node, *tmp;
2651 struct amdgpu_ras_block_object *obj;
2654 /* Guest side doesn't need init ras feature */
2655 if (amdgpu_sriov_vf(adev))
2658 list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
2659 if (!node->ras_obj) {
2660 dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
2664 obj = node->ras_obj;
2665 if (obj->ras_late_init) {
2666 r = obj->ras_late_init(adev, &obj->ras_comm);
2668 dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n",
2669 obj->ras_comm.name, r);
2673 amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);
2679 /* do some fini work before IP fini as dependence */
2680 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2682 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2684 if (!adev->ras_enabled || !con)
2688 /* Need disable ras on all IPs here before ip [hw/sw]fini */
2689 amdgpu_ras_disable_all_features(adev, 0);
2690 amdgpu_ras_recovery_fini(adev);
2694 int amdgpu_ras_fini(struct amdgpu_device *adev)
2696 struct amdgpu_ras_block_list *ras_node, *tmp;
2697 struct amdgpu_ras_block_object *obj = NULL;
2698 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2700 if (!adev->ras_enabled || !con)
2703 list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) {
2704 if (ras_node->ras_obj) {
2705 obj = ras_node->ras_obj;
2706 if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) &&
2708 obj->ras_fini(adev, &obj->ras_comm);
2710 amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm);
2713 /* Clear ras blocks from ras_list and free ras block list node */
2714 list_del(&ras_node->node);
2718 amdgpu_ras_fs_fini(adev);
2719 amdgpu_ras_interrupt_remove_all(adev);
2721 WARN(con->features, "Feature mask is not cleared");
2724 amdgpu_ras_disable_all_features(adev, 1);
2726 cancel_delayed_work_sync(&con->ras_counte_delay_work);
2728 amdgpu_ras_set_context(adev, NULL);
2734 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2736 amdgpu_ras_check_supported(adev);
2737 if (!adev->ras_hw_enabled)
2740 if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2741 dev_info(adev->dev, "uncorrectable hardware error"
2742 "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
2744 amdgpu_ras_reset_gpu(adev);
2748 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2750 if (adev->asic_type == CHIP_VEGA20 &&
2751 adev->pm.fw_version <= 0x283400) {
2752 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2753 amdgpu_ras_intr_triggered();
2759 void amdgpu_release_ras_context(struct amdgpu_device *adev)
2761 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2766 if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
2767 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
2768 amdgpu_ras_set_context(adev, NULL);
2773 #ifdef CONFIG_X86_MCE_AMD
2774 static struct amdgpu_device *find_adev(uint32_t node_id)
2777 struct amdgpu_device *adev = NULL;
2779 for (i = 0; i < mce_adev_list.num_gpu; i++) {
2780 adev = mce_adev_list.devs[i];
2782 if (adev && adev->gmc.xgmi.connected_to_cpu &&
2783 adev->gmc.xgmi.physical_node_id == node_id)
2791 #define GET_MCA_IPID_GPUID(m) (((m) >> 44) & 0xF)
2792 #define GET_UMC_INST(m) (((m) >> 21) & 0x7)
2793 #define GET_CHAN_INDEX(m) ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4))
2794 #define GPU_ID_OFFSET 8
2796 static int amdgpu_bad_page_notifier(struct notifier_block *nb,
2797 unsigned long val, void *data)
2799 struct mce *m = (struct mce *)data;
2800 struct amdgpu_device *adev = NULL;
2801 uint32_t gpu_id = 0;
2802 uint32_t umc_inst = 0;
2803 uint32_t ch_inst, channel_index = 0;
2804 struct ras_err_data err_data = {0, 0, 0, NULL};
2805 struct eeprom_table_record err_rec;
2806 uint64_t retired_page;
2809 * If the error was generated in UMC_V2, which belongs to GPU UMCs,
2810 * and error occurred in DramECC (Extended error code = 0) then only
2811 * process the error, else bail out.
2813 if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) &&
2814 (XEC(m->status, 0x3f) == 0x0)))
2818 * If it is correctable error, return.
2820 if (mce_is_correctable(m))
2824 * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register.
2826 gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET;
2828 adev = find_adev(gpu_id);
2830 DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__,
2836 * If it is uncorrectable error, then find out UMC instance and
2839 umc_inst = GET_UMC_INST(m->ipid);
2840 ch_inst = GET_CHAN_INDEX(m->ipid);
2842 dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",
2846 * Translate UMC channel address to Physical address
2849 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num
2852 retired_page = ADDR_OF_8KB_BLOCK(m->addr) |
2853 ADDR_OF_256B_BLOCK(channel_index) |
2854 OFFSET_IN_256B_BLOCK(m->addr);
2856 memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
2857 err_data.err_addr = &err_rec;
2858 amdgpu_umc_fill_error_record(&err_data, m->addr,
2859 retired_page, channel_index, umc_inst);
2861 if (amdgpu_bad_page_threshold != 0) {
2862 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
2863 err_data.err_addr_cnt);
2864 amdgpu_ras_save_bad_pages(adev);
2870 static struct notifier_block amdgpu_bad_page_nb = {
2871 .notifier_call = amdgpu_bad_page_notifier,
2872 .priority = MCE_PRIO_UC,
2875 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev)
2878 * Add the adev to the mce_adev_list.
2879 * During mode2 reset, amdgpu device is temporarily
2880 * removed from the mgpu_info list which can cause
2881 * page retirement to fail.
2882 * Use this list instead of mgpu_info to find the amdgpu
2883 * device on which the UMC error was reported.
2885 mce_adev_list.devs[mce_adev_list.num_gpu++] = adev;
2888 * Register the x86 notifier only once
2889 * with MCE subsystem.
2891 if (notifier_registered == false) {
2892 mce_register_decode_chain(&amdgpu_bad_page_nb);
2893 notifier_registered = true;
2898 struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev)
2903 return adev->psp.ras_context.ras;
2906 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con)
2911 adev->psp.ras_context.ras = ras_con;
2915 /* check if ras is supported on block, say, sdma, gfx */
2916 int amdgpu_ras_is_supported(struct amdgpu_device *adev,
2919 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2921 if (block >= AMDGPU_RAS_BLOCK_COUNT)
2923 return ras && (adev->ras_enabled & (1 << block));
2926 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
2928 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2930 if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
2931 schedule_work(&ras->recovery_work);
2936 /* Register each ip ras block into amdgpu ras */
2937 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
2938 struct amdgpu_ras_block_object *ras_block_obj)
2940 struct amdgpu_ras_block_list *ras_node;
2941 if (!adev || !ras_block_obj)
2944 if (!amdgpu_ras_asic_supported(adev))
2947 ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL);
2951 INIT_LIST_HEAD(&ras_node->node);
2952 ras_node->ras_obj = ras_block_obj;
2953 list_add_tail(&ras_node->node, &adev->ras_list);