git.itanic.dy.fi Git - linux-stable/blob - drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_atombios.h"
  25 #include "nbio_v7_7.h"
  26
  27 #include "nbio/nbio_7_7_0_offset.h"
  28 #include "nbio/nbio_7_7_0_sh_mask.h"
  29 #include <uapi/linux/kfd_ioctl.h>
  30
  31 static void nbio_v7_7_remap_hdp_registers(struct amdgpu_device *adev)
  32 {
  33         WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
  34                      adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
  35         WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
  36                      adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
  37 }
  38
  39 static u32 nbio_v7_7_get_rev_id(struct amdgpu_device *adev)
  40 {
  41         u32 tmp;
  42
  43         tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
  44         tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
  45         tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
  46
  47         return tmp;
  48 }
  49
  50 static void nbio_v7_7_mc_access_enable(struct amdgpu_device *adev, bool enable)
  51 {
  52         if (enable)
  53                 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN,
  54                         BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK |
  55                         BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK);
  56         else
  57                 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN, 0);
  58 }
  59
  60 static u32 nbio_v7_7_get_memsize(struct amdgpu_device *adev)
  61 {
  62         return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE);
  63 }
  64
  65 static void nbio_v7_7_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
  66                                           bool use_doorbell, int doorbell_index,
  67                                           int doorbell_size)
  68 {
  69         u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE);
  70         u32 doorbell_range = RREG32_PCIE_PORT(reg);
  71
  72         if (use_doorbell) {
  73                 doorbell_range = REG_SET_FIELD(doorbell_range,
  74                                                GDC0_BIF_SDMA0_DOORBELL_RANGE,
  75                                                OFFSET, doorbell_index);
  76                 doorbell_range = REG_SET_FIELD(doorbell_range,
  77                                                GDC0_BIF_SDMA0_DOORBELL_RANGE,
  78                                                SIZE, doorbell_size);
  79         } else {
  80                 doorbell_range = REG_SET_FIELD(doorbell_range,
  81                                                GDC0_BIF_SDMA0_DOORBELL_RANGE,
  82                                                SIZE, 0);
  83         }
  84
  85         WREG32_PCIE_PORT(reg, doorbell_range);
  86 }
  87
  88 static void nbio_v7_7_enable_doorbell_aperture(struct amdgpu_device *adev,
  89                                                bool enable)
  90 {
  91         u32 reg;
  92
  93         reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);
  94         reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,
  95                             BIF_DOORBELL_APER_EN, enable ? 1 : 0);
  96
  97         WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg);
  98 }
  99
 100 static void nbio_v7_7_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
 101                                                         bool enable)
 102 {
 103         u32 tmp = 0;
 104
 105         if (enable) {
 106                 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
 107                                 DOORBELL_SELFRING_GPA_APER_EN, 1) |
 108                         REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
 109                                 DOORBELL_SELFRING_GPA_APER_MODE, 1) |
 110                         REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
 111                                 DOORBELL_SELFRING_GPA_APER_SIZE, 0);
 112
 113                 WREG32_SOC15(NBIO, 0,
 114                         regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
 115                         lower_32_bits(adev->doorbell.base));
 116                 WREG32_SOC15(NBIO, 0,
 117                         regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
 118                         upper_32_bits(adev->doorbell.base));
 119         }
 120
 121         WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
 122                 tmp);
 123 }
 124
 125
 126 static void nbio_v7_7_ih_doorbell_range(struct amdgpu_device *adev,
 127                                         bool use_doorbell, int doorbell_index)
 128 {
 129         u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0,
 130                                                                 regGDC0_BIF_IH_DOORBELL_RANGE);
 131
 132         if (use_doorbell) {
 133                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
 134                                                   GDC0_BIF_IH_DOORBELL_RANGE, OFFSET,
 135                                                   doorbell_index);
 136                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
 137                                                   GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
 138                                                   2);
 139         } else {
 140                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
 141                                                   GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
 142                                                   0);
 143         }
 144
 145         WREG32_SOC15(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE,
 146                          ih_doorbell_range);
 147 }
 148
 149 static void nbio_v7_7_ih_control(struct amdgpu_device *adev)
 150 {
 151         u32 interrupt_cntl;
 152
 153         /* setup interrupt control */
 154         WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL2,
 155                      adev->dummy_page_addr >> 8);
 156
 157         interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL);
 158         /*
 159          * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
 160          * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
 161          */
 162         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL,
 163                                        IH_DUMMY_RD_OVERRIDE, 0);
 164
 165         /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
 166         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL,
 167                                        IH_REQ_NONSNOOP_EN, 0);
 168
 169         WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL, interrupt_cntl);
 170 }
 171
 172 static u32 nbio_v7_7_get_hdp_flush_req_offset(struct amdgpu_device *adev)
 173 {
 174         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
 175 }
 176
 177 static u32 nbio_v7_7_get_hdp_flush_done_offset(struct amdgpu_device *adev)
 178 {
 179         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
 180 }
 181
 182 static u32 nbio_v7_7_get_pcie_index_offset(struct amdgpu_device *adev)
 183 {
 184         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
 185 }
 186
 187 static u32 nbio_v7_7_get_pcie_data_offset(struct amdgpu_device *adev)
 188 {
 189         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2);
 190 }
 191
 192 static u32 nbio_v7_7_get_pcie_port_index_offset(struct amdgpu_device *adev)
 193 {
 194         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
 195 }
 196
 197 static u32 nbio_v7_7_get_pcie_port_data_offset(struct amdgpu_device *adev)
 198 {
 199         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
 200 }
 201
 202 const struct nbio_hdp_flush_reg nbio_v7_7_hdp_flush_reg = {
 203         .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
 204         .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
 205         .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
 206         .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
 207         .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
 208         .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
 209         .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
 210         .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
 211         .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
 212         .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
 213         .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
 214         .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
 215 };
 216
 217 static void nbio_v7_7_init_registers(struct amdgpu_device *adev)
 218 {
 219         uint32_t def, data;
 220
 221         def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3);
 222         data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,
 223                              CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
 224         data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,
 225                              CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
 226
 227         if (def != data)
 228                 WREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3, data);
 229
 230 }
 231
 232 const struct amdgpu_nbio_funcs nbio_v7_7_funcs = {
 233         .get_hdp_flush_req_offset = nbio_v7_7_get_hdp_flush_req_offset,
 234         .get_hdp_flush_done_offset = nbio_v7_7_get_hdp_flush_done_offset,
 235         .get_pcie_index_offset = nbio_v7_7_get_pcie_index_offset,
 236         .get_pcie_data_offset = nbio_v7_7_get_pcie_data_offset,
 237         .get_pcie_port_index_offset = nbio_v7_7_get_pcie_port_index_offset,
 238         .get_pcie_port_data_offset = nbio_v7_7_get_pcie_port_data_offset,
 239         .get_rev_id = nbio_v7_7_get_rev_id,
 240         .mc_access_enable = nbio_v7_7_mc_access_enable,
 241         .get_memsize = nbio_v7_7_get_memsize,
 242         .sdma_doorbell_range = nbio_v7_7_sdma_doorbell_range,
 243         .enable_doorbell_aperture = nbio_v7_7_enable_doorbell_aperture,
 244         .enable_doorbell_selfring_aperture = nbio_v7_7_enable_doorbell_selfring_aperture,
 245         .ih_doorbell_range = nbio_v7_7_ih_doorbell_range,
 246         .ih_control = nbio_v7_7_ih_control,
 247         .init_registers = nbio_v7_7_init_registers,
 248         .remap_hdp_registers = nbio_v7_7_remap_hdp_registers,
 249 };