git.itanic.dy.fi Git - linux-stable/blob - drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include <linux/pci.h>
  28 #include <linux/i2c.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_dpm.h"
  31 #include "amdgpu_smu.h"
  32 #include "atomfirmware.h"
  33 #include "amdgpu_atomfirmware.h"
  34 #include "amdgpu_atombios.h"
  35 #include "smu_v11_0.h"
  36 #include "smu11_driver_if_sienna_cichlid.h"
  37 #include "soc15_common.h"
  38 #include "atom.h"
  39 #include "sienna_cichlid_ppt.h"
  40 #include "smu_v11_0_7_pptable.h"
  41 #include "smu_v11_0_7_ppsmc.h"
  42 #include "nbio/nbio_2_3_offset.h"
  43 #include "nbio/nbio_2_3_sh_mask.h"
  44 #include "thm/thm_11_0_2_offset.h"
  45 #include "thm/thm_11_0_2_sh_mask.h"
  46 #include "mp/mp_11_0_offset.h"
  47 #include "mp/mp_11_0_sh_mask.h"
  48
  49 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  50 #include "amdgpu_ras.h"
  51 #include "smu_cmn.h"
  52
  53 /*
  54  * DO NOT use these for err/warn/info/debug messages.
  55  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  56  * They are more MGPU friendly.
  57  */
  58 #undef pr_err
  59 #undef pr_warn
  60 #undef pr_info
  61 #undef pr_debug
  62
  63 #define FEATURE_MASK(feature) (1ULL << feature)
  64 #define SMC_DPM_FEATURE ( \
  65         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  66         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  67         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  68         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  69         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  70         FEATURE_MASK(FEATURE_DPM_FCLK_BIT)       | \
  71         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)    | \
  72         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
  73
  74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
  75
  76 #define GET_PPTABLE_MEMBER(field, member) do {\
  77         if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\
  78                 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
  79         else\
  80                 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
  81 } while(0)
  82
  83 /* STB FIFO depth is in 64bit units */
  84 #define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8
  85
  86 /*
  87  * SMU support ECCTABLE since version 58.70.0,
  88  * use this to check whether ECCTABLE feature is supported.
  89  */
  90 #define SUPPORT_ECCTABLE_SMU_VERSION 0x003a4600
  91
  92 static int get_table_size(struct smu_context *smu)
  93 {
  94         if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
  95                 return sizeof(PPTable_beige_goby_t);
  96         else
  97                 return sizeof(PPTable_t);
  98 }
  99
 100 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
 101         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                 1),
 102         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,               1),
 103         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,          1),
 104         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow,   0),
 105         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh,  0),
 106         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures,        0),
 107         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures,       0),
 108         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow,        1),
 109         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh,       1),
 110         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow,       1),
 111         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh,      1),
 112         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetRunningSmuFeaturesLow,    1),
 113         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetRunningSmuFeaturesHigh,   1),
 114         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,             1),
 115         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                 0),
 116         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,       1),
 117         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,        1),
 118         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,        0),
 119         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,         0),
 120         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,       1),
 121         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,       0),
 122         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,           0),
 123         MSG_MAP(RunDcBtc,                       PPSMC_MSG_RunDcBtc,                    0),
 124         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                   0),
 125         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,            1),
 126         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,            1),
 127         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,            1),
 128         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,            0),
 129         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,               1),
 130         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq,               1),
 131         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex,           1),
 132         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode,               0),
 133         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh,       0),
 134         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow,        0),
 135         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters,      0),
 136         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt,       0),
 137         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource,           0),
 138         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch,           0),
 139         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps,                 0),
 140         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,         1),
 141         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                 0),
 142         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,              0),
 143         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit,                 0),
 144         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq,         1),
 145         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco,                    0),
 146         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                  0),
 147         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                0),
 148         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                 0),
 149         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,               0),
 150         MSG_MAP(BacoAudioD3PME,                 PPSMC_MSG_BacoAudioD3PME,              0),
 151         MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3,                       0),
 152         MSG_MAP(Mode1Reset,                     PPSMC_MSG_Mode1Reset,                  0),
 153         MSG_MAP(SetMGpuFanBoostLimitRpm,        PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),
 154         MSG_MAP(SetGpoFeaturePMask,             PPSMC_MSG_SetGpoFeaturePMask,          0),
 155         MSG_MAP(DisallowGpo,                    PPSMC_MSG_DisallowGpo,                 0),
 156         MSG_MAP(Enable2ndUSB20Port,             PPSMC_MSG_Enable2ndUSB20Port,          0),
 157 };
 158
 159 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
 160         CLK_MAP(GFXCLK,         PPCLK_GFXCLK),
 161         CLK_MAP(SCLK,           PPCLK_GFXCLK),
 162         CLK_MAP(SOCCLK,         PPCLK_SOCCLK),
 163         CLK_MAP(FCLK,           PPCLK_FCLK),
 164         CLK_MAP(UCLK,           PPCLK_UCLK),
 165         CLK_MAP(MCLK,           PPCLK_UCLK),
 166         CLK_MAP(DCLK,           PPCLK_DCLK_0),
 167         CLK_MAP(DCLK1,          PPCLK_DCLK_1),
 168         CLK_MAP(VCLK,           PPCLK_VCLK_0),
 169         CLK_MAP(VCLK1,          PPCLK_VCLK_1),
 170         CLK_MAP(DCEFCLK,        PPCLK_DCEFCLK),
 171         CLK_MAP(DISPCLK,        PPCLK_DISPCLK),
 172         CLK_MAP(PIXCLK,         PPCLK_PIXCLK),
 173         CLK_MAP(PHYCLK,         PPCLK_PHYCLK),
 174 };
 175
 176 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
 177         FEA_MAP(DPM_PREFETCHER),
 178         FEA_MAP(DPM_GFXCLK),
 179         FEA_MAP(DPM_GFX_GPO),
 180         FEA_MAP(DPM_UCLK),
 181         FEA_MAP(DPM_FCLK),
 182         FEA_MAP(DPM_SOCCLK),
 183         FEA_MAP(DPM_MP0CLK),
 184         FEA_MAP(DPM_LINK),
 185         FEA_MAP(DPM_DCEFCLK),
 186         FEA_MAP(DPM_XGMI),
 187         FEA_MAP(MEM_VDDCI_SCALING),
 188         FEA_MAP(MEM_MVDD_SCALING),
 189         FEA_MAP(DS_GFXCLK),
 190         FEA_MAP(DS_SOCCLK),
 191         FEA_MAP(DS_FCLK),
 192         FEA_MAP(DS_LCLK),
 193         FEA_MAP(DS_DCEFCLK),
 194         FEA_MAP(DS_UCLK),
 195         FEA_MAP(GFX_ULV),
 196         FEA_MAP(FW_DSTATE),
 197         FEA_MAP(GFXOFF),
 198         FEA_MAP(BACO),
 199         FEA_MAP(MM_DPM_PG),
 200         FEA_MAP(RSMU_SMN_CG),
 201         FEA_MAP(PPT),
 202         FEA_MAP(TDC),
 203         FEA_MAP(APCC_PLUS),
 204         FEA_MAP(GTHR),
 205         FEA_MAP(ACDC),
 206         FEA_MAP(VR0HOT),
 207         FEA_MAP(VR1HOT),
 208         FEA_MAP(FW_CTF),
 209         FEA_MAP(FAN_CONTROL),
 210         FEA_MAP(THERMAL),
 211         FEA_MAP(GFX_DCS),
 212         FEA_MAP(RM),
 213         FEA_MAP(LED_DISPLAY),
 214         FEA_MAP(GFX_SS),
 215         FEA_MAP(OUT_OF_BAND_MONITOR),
 216         FEA_MAP(TEMP_DEPENDENT_VMIN),
 217         FEA_MAP(MMHUB_PG),
 218         FEA_MAP(ATHUB_PG),
 219         FEA_MAP(APCC_DFLL),
 220 };
 221
 222 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
 223         TAB_MAP(PPTABLE),
 224         TAB_MAP(WATERMARKS),
 225         TAB_MAP(AVFS_PSM_DEBUG),
 226         TAB_MAP(AVFS_FUSE_OVERRIDE),
 227         TAB_MAP(PMSTATUSLOG),
 228         TAB_MAP(SMU_METRICS),
 229         TAB_MAP(DRIVER_SMU_CONFIG),
 230         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 231         TAB_MAP(OVERDRIVE),
 232         TAB_MAP(I2C_COMMANDS),
 233         TAB_MAP(PACE),
 234         TAB_MAP(ECCINFO),
 235 };
 236
 237 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 238         PWR_MAP(AC),
 239         PWR_MAP(DC),
 240 };
 241
 242 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 243         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 244         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 245         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 246         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 247         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 248         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 249         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 250 };
 251
 252 static const uint8_t sienna_cichlid_throttler_map[] = {
 253         [THROTTLER_TEMP_EDGE_BIT]       = (SMU_THROTTLER_TEMP_EDGE_BIT),
 254         [THROTTLER_TEMP_HOTSPOT_BIT]    = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
 255         [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 256         [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 257         [THROTTLER_TEMP_VR_MEM0_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 258         [THROTTLER_TEMP_VR_MEM1_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
 259         [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 260         [THROTTLER_TEMP_LIQUID0_BIT]    = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
 261         [THROTTLER_TEMP_LIQUID1_BIT]    = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
 262         [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 263         [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 264         [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 265         [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 266         [THROTTLER_PPT2_BIT]            = (SMU_THROTTLER_PPT2_BIT),
 267         [THROTTLER_PPT3_BIT]            = (SMU_THROTTLER_PPT3_BIT),
 268         [THROTTLER_FIT_BIT]             = (SMU_THROTTLER_FIT_BIT),
 269         [THROTTLER_PPM_BIT]             = (SMU_THROTTLER_PPM_BIT),
 270         [THROTTLER_APCC_BIT]            = (SMU_THROTTLER_APCC_BIT),
 271 };
 272
 273 static int
 274 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 275                                   uint32_t *feature_mask, uint32_t num)
 276 {
 277         struct amdgpu_device *adev = smu->adev;
 278
 279         if (num > 2)
 280                 return -EINVAL;
 281
 282         memset(feature_mask, 0, sizeof(uint32_t) * num);
 283
 284         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 285                                 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
 286                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 287                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 288                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 289                                 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
 290                                 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
 291                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 292                                 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
 293                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 294                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 295                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 296                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 297                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 298                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 299                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 300                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 301                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 302                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 303                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 304
 305         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
 306                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 307                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
 308         }
 309
 310         if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
 311             (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) &&
 312             !(adev->flags & AMD_IS_APU))
 313                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
 314
 315         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 316                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 317                                         | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 318                                         | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 319
 320         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 321                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 322
 323         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 324                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 325
 326         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 327                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 328
 329         if (adev->pm.pp_feature & PP_ULV_MASK)
 330                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 331
 332         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 333                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 334
 335         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 336                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 337
 338         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 339                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 340
 341         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 342                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 343
 344         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
 345             smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 346                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
 347
 348         if (smu->dc_controlled_by_gpio)
 349        *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
 350
 351         if (amdgpu_device_should_use_aspm(adev))
 352                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
 353
 354         return 0;
 355 }
 356
 357 static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
 358 {
 359         struct smu_table_context *table_context = &smu->smu_table;
 360         struct smu_11_0_7_powerplay_table *powerplay_table =
 361                 table_context->power_play_table;
 362         struct smu_baco_context *smu_baco = &smu->smu_baco;
 363         struct amdgpu_device *adev = smu->adev;
 364         uint32_t val;
 365
 366         if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) {
 367                 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
 368                 smu_baco->platform_support =
 369                         (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
 370                                                                         false;
 371         }
 372 }
 373
 374 static void sienna_cichlid_check_fan_support(struct smu_context *smu)
 375 {
 376         struct smu_table_context *table_context = &smu->smu_table;
 377         PPTable_t *pptable = table_context->driver_pptable;
 378         uint64_t features = *(uint64_t *) pptable->FeaturesToRun;
 379
 380         /* Fan control is not possible if PPTable has it disabled */
 381         smu->adev->pm.no_fan =
 382                 !(features & (1ULL << FEATURE_FAN_CONTROL_BIT));
 383         if (smu->adev->pm.no_fan)
 384                 dev_info_once(smu->adev->dev,
 385                               "PMFW based fan control disabled");
 386 }
 387
 388 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
 389 {
 390         struct smu_table_context *table_context = &smu->smu_table;
 391         struct smu_11_0_7_powerplay_table *powerplay_table =
 392                 table_context->power_play_table;
 393
 394         if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
 395                 smu->dc_controlled_by_gpio = true;
 396
 397         sienna_cichlid_check_bxco_support(smu);
 398         sienna_cichlid_check_fan_support(smu);
 399
 400         table_context->thermal_controller_type =
 401                 powerplay_table->thermal_controller_type;
 402
 403         /*
 404          * Instead of having its own buffer space and get overdrive_table copied,
 405          * smu->od_settings just points to the actual overdrive_table
 406          */
 407         smu->od_settings = &powerplay_table->overdrive_table;
 408
 409         return 0;
 410 }
 411
 412 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
 413 {
 414         struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
 415         int index, ret;
 416         I2cControllerConfig_t *table_member;
 417
 418         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 419                                             smc_dpm_info);
 420
 421         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 422                                       (uint8_t **)&smc_dpm_table);
 423         if (ret)
 424                 return ret;
 425         GET_PPTABLE_MEMBER(I2cControllers, &table_member);
 426         memcpy(table_member, smc_dpm_table->I2cControllers,
 427                         sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
 428
 429         return 0;
 430 }
 431
 432 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
 433 {
 434         struct smu_table_context *table_context = &smu->smu_table;
 435         struct smu_11_0_7_powerplay_table *powerplay_table =
 436                 table_context->power_play_table;
 437         int table_size;
 438
 439         table_size = get_table_size(smu);
 440         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 441                table_size);
 442
 443         return 0;
 444 }
 445
 446 static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu)
 447 {
 448         struct amdgpu_device *adev = smu->adev;
 449         uint32_t *board_reserved;
 450         uint16_t *freq_table_gfx;
 451         uint32_t i;
 452
 453         /* Fix some OEM SKU specific stability issues */
 454         GET_PPTABLE_MEMBER(BoardReserved, &board_reserved);
 455         if ((adev->pdev->device == 0x73DF) &&
 456             (adev->pdev->revision == 0XC3) &&
 457             (adev->pdev->subsystem_device == 0x16C2) &&
 458             (adev->pdev->subsystem_vendor == 0x1043))
 459                 board_reserved[0] = 1387;
 460
 461         GET_PPTABLE_MEMBER(FreqTableGfx, &freq_table_gfx);
 462         if ((adev->pdev->device == 0x73DF) &&
 463             (adev->pdev->revision == 0XC3) &&
 464             ((adev->pdev->subsystem_device == 0x16C2) ||
 465             (adev->pdev->subsystem_device == 0x133C)) &&
 466             (adev->pdev->subsystem_vendor == 0x1043)) {
 467                 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) {
 468                         if (freq_table_gfx[i] > 2500)
 469                                 freq_table_gfx[i] = 2500;
 470                 }
 471         }
 472
 473         return 0;
 474 }
 475
 476 static int sienna_cichlid_setup_pptable(struct smu_context *smu)
 477 {
 478         int ret = 0;
 479
 480         ret = smu_v11_0_setup_pptable(smu);
 481         if (ret)
 482                 return ret;
 483
 484         ret = sienna_cichlid_store_powerplay_table(smu);
 485         if (ret)
 486                 return ret;
 487
 488         ret = sienna_cichlid_append_powerplay_table(smu);
 489         if (ret)
 490                 return ret;
 491
 492         ret = sienna_cichlid_check_powerplay_table(smu);
 493         if (ret)
 494                 return ret;
 495
 496         return sienna_cichlid_patch_pptable_quirk(smu);
 497 }
 498
 499 static int sienna_cichlid_tables_init(struct smu_context *smu)
 500 {
 501         struct smu_table_context *smu_table = &smu->smu_table;
 502         struct smu_table *tables = smu_table->tables;
 503         int table_size;
 504
 505         table_size = get_table_size(smu);
 506         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
 507                                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 508         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 509                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 510         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
 511                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 512         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 513                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 514         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 515                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 516         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 517                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 518         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 519                        sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
 520                        AMDGPU_GEM_DOMAIN_VRAM);
 521         SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
 522                         PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 523         SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfigExternal_t),
 524                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 525
 526         smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
 527         if (!smu_table->metrics_table)
 528                 goto err0_out;
 529         smu_table->metrics_time = 0;
 530
 531         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 532         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 533         if (!smu_table->gpu_metrics_table)
 534                 goto err1_out;
 535
 536         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 537         if (!smu_table->watermarks_table)
 538                 goto err2_out;
 539
 540         smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
 541         if (!smu_table->ecc_table)
 542                 goto err3_out;
 543
 544         smu_table->driver_smu_config_table =
 545                 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL);
 546         if (!smu_table->driver_smu_config_table)
 547                 goto err4_out;
 548
 549         return 0;
 550
 551 err4_out:
 552         kfree(smu_table->ecc_table);
 553 err3_out:
 554         kfree(smu_table->watermarks_table);
 555 err2_out:
 556         kfree(smu_table->gpu_metrics_table);
 557 err1_out:
 558         kfree(smu_table->metrics_table);
 559 err0_out:
 560         return -ENOMEM;
 561 }
 562
 563 static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu)
 564 {
 565         struct smu_table_context *smu_table= &smu->smu_table;
 566         SmuMetricsExternal_t *metrics_ext =
 567                 (SmuMetricsExternal_t *)(smu_table->metrics_table);
 568         uint32_t throttler_status = 0;
 569         int i;
 570
 571         if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
 572              (smu->smc_fw_version >= 0x3A4900)) {
 573                 for (i = 0; i < THROTTLER_COUNT; i++)
 574                         throttler_status |=
 575                                 (metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0);
 576         } else if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
 577              (smu->smc_fw_version >= 0x3A4300)) {
 578                 for (i = 0; i < THROTTLER_COUNT; i++)
 579                         throttler_status |=
 580                                 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
 581         } else {
 582                 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus;
 583         }
 584
 585         return throttler_status;
 586 }
 587
 588 static int sienna_cichlid_get_power_limit(struct smu_context *smu,
 589                                           uint32_t *current_power_limit,
 590                                           uint32_t *default_power_limit,
 591                                           uint32_t *max_power_limit)
 592 {
 593         struct smu_11_0_7_powerplay_table *powerplay_table =
 594                 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
 595         uint32_t power_limit, od_percent;
 596         uint16_t *table_member;
 597
 598         GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
 599
 600         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
 601                 power_limit =
 602                         table_member[PPT_THROTTLER_PPT0];
 603         }
 604
 605         if (current_power_limit)
 606                 *current_power_limit = power_limit;
 607         if (default_power_limit)
 608                 *default_power_limit = power_limit;
 609
 610         if (max_power_limit) {
 611                 if (smu->od_enabled) {
 612                         od_percent =
 613                                 le32_to_cpu(powerplay_table->overdrive_table.max[
 614                                                         SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
 615
 616                         dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n",
 617                                         od_percent, power_limit);
 618
 619                         power_limit *= (100 + od_percent);
 620                         power_limit /= 100;
 621                 }
 622                 *max_power_limit = power_limit;
 623         }
 624
 625         return 0;
 626 }
 627
 628 static void sienna_cichlid_get_smartshift_power_percentage(struct smu_context *smu,
 629                                         uint32_t *apu_percent,
 630                                         uint32_t *dgpu_percent)
 631 {
 632         struct smu_table_context *smu_table = &smu->smu_table;
 633         SmuMetrics_V4_t *metrics_v4 =
 634                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V4);
 635         uint16_t powerRatio = 0;
 636         uint16_t apu_power_limit = 0;
 637         uint16_t dgpu_power_limit = 0;
 638         uint32_t apu_boost = 0;
 639         uint32_t dgpu_boost = 0;
 640         uint32_t cur_power_limit;
 641
 642         if (metrics_v4->ApuSTAPMSmartShiftLimit != 0) {
 643                 sienna_cichlid_get_power_limit(smu, &cur_power_limit, NULL, NULL);
 644                 apu_power_limit = metrics_v4->ApuSTAPMLimit;
 645                 dgpu_power_limit = cur_power_limit;
 646                 powerRatio = (((apu_power_limit +
 647                                                   dgpu_power_limit) * 100) /
 648                                                   metrics_v4->ApuSTAPMSmartShiftLimit);
 649                 if (powerRatio > 100) {
 650                         apu_power_limit = (apu_power_limit * 100) /
 651                                                                          powerRatio;
 652                         dgpu_power_limit = (dgpu_power_limit * 100) /
 653                                                                           powerRatio;
 654                 }
 655                 if (metrics_v4->AverageApuSocketPower > apu_power_limit &&
 656                          apu_power_limit != 0) {
 657                         apu_boost = ((metrics_v4->AverageApuSocketPower -
 658                                                         apu_power_limit) * 100) /
 659                                                         apu_power_limit;
 660                         if (apu_boost > 100)
 661                                 apu_boost = 100;
 662                 }
 663
 664                 if (metrics_v4->AverageSocketPower > dgpu_power_limit &&
 665                          dgpu_power_limit != 0) {
 666                         dgpu_boost = ((metrics_v4->AverageSocketPower -
 667                                                          dgpu_power_limit) * 100) /
 668                                                          dgpu_power_limit;
 669                         if (dgpu_boost > 100)
 670                                 dgpu_boost = 100;
 671                 }
 672
 673                 if (dgpu_boost >= apu_boost)
 674                         apu_boost = 0;
 675                 else
 676                         dgpu_boost = 0;
 677         }
 678         *apu_percent = apu_boost;
 679         *dgpu_percent = dgpu_boost;
 680 }
 681
 682 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
 683                                                MetricsMember_t member,
 684                                                uint32_t *value)
 685 {
 686         struct smu_table_context *smu_table= &smu->smu_table;
 687         SmuMetrics_t *metrics =
 688                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
 689         SmuMetrics_V2_t *metrics_v2 =
 690                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
 691         SmuMetrics_V3_t *metrics_v3 =
 692                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V3);
 693         bool use_metrics_v2 = false;
 694         bool use_metrics_v3 = false;
 695         uint16_t average_gfx_activity;
 696         int ret = 0;
 697         uint32_t apu_percent = 0;
 698         uint32_t dgpu_percent = 0;
 699
 700         switch (smu->adev->ip_versions[MP1_HWIP][0]) {
 701         case IP_VERSION(11, 0, 7):
 702                 if (smu->smc_fw_version >= 0x3A4900)
 703                         use_metrics_v3 = true;
 704                 else if (smu->smc_fw_version >= 0x3A4300)
 705                         use_metrics_v2 = true;
 706                 break;
 707         case IP_VERSION(11, 0, 11):
 708                 if (smu->smc_fw_version >= 0x412D00)
 709                         use_metrics_v2 = true;
 710                 break;
 711         case IP_VERSION(11, 0, 12):
 712                 if (smu->smc_fw_version >= 0x3B2300)
 713                         use_metrics_v2 = true;
 714                 break;
 715         case IP_VERSION(11, 0, 13):
 716                 if (smu->smc_fw_version >= 0x491100)
 717                         use_metrics_v2 = true;
 718                 break;
 719         default:
 720                 break;
 721         }
 722
 723         ret = smu_cmn_get_metrics_table(smu,
 724                                         NULL,
 725                                         false);
 726         if (ret)
 727                 return ret;
 728
 729         switch (member) {
 730         case METRICS_CURR_GFXCLK:
 731                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
 732                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] :
 733                         metrics->CurrClock[PPCLK_GFXCLK];
 734                 break;
 735         case METRICS_CURR_SOCCLK:
 736                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
 737                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] :
 738                         metrics->CurrClock[PPCLK_SOCCLK];
 739                 break;
 740         case METRICS_CURR_UCLK:
 741                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
 742                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :
 743                         metrics->CurrClock[PPCLK_UCLK];
 744                 break;
 745         case METRICS_CURR_VCLK:
 746                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
 747                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] :
 748                         metrics->CurrClock[PPCLK_VCLK_0];
 749                 break;
 750         case METRICS_CURR_VCLK1:
 751                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
 752                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] :
 753                         metrics->CurrClock[PPCLK_VCLK_1];
 754                 break;
 755         case METRICS_CURR_DCLK:
 756                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
 757                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] :
 758                         metrics->CurrClock[PPCLK_DCLK_0];
 759                 break;
 760         case METRICS_CURR_DCLK1:
 761                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
 762                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
 763                         metrics->CurrClock[PPCLK_DCLK_1];
 764                 break;
 765         case METRICS_CURR_DCEFCLK:
 766                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCEFCLK] :
 767                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] :
 768                         metrics->CurrClock[PPCLK_DCEFCLK];
 769                 break;
 770         case METRICS_CURR_FCLK:
 771                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_FCLK] :
 772                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] :
 773                         metrics->CurrClock[PPCLK_FCLK];
 774                 break;
 775         case METRICS_AVERAGE_GFXCLK:
 776                 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
 777                         use_metrics_v2 ? metrics_v2->AverageGfxActivity :
 778                         metrics->AverageGfxActivity;
 779                 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
 780                         *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
 781                                 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
 782                                 metrics->AverageGfxclkFrequencyPostDs;
 783                 else
 784                         *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
 785                                 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
 786                                 metrics->AverageGfxclkFrequencyPreDs;
 787                 break;
 788         case METRICS_AVERAGE_FCLK:
 789                 *value = use_metrics_v3 ? metrics_v3->AverageFclkFrequencyPostDs :
 790                         use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs :
 791                         metrics->AverageFclkFrequencyPostDs;
 792                 break;
 793         case METRICS_AVERAGE_UCLK:
 794                 *value = use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
 795                         use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
 796                         metrics->AverageUclkFrequencyPostDs;
 797                 break;
 798         case METRICS_AVERAGE_GFXACTIVITY:
 799                 *value = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
 800                         use_metrics_v2 ? metrics_v2->AverageGfxActivity :
 801                         metrics->AverageGfxActivity;
 802                 break;
 803         case METRICS_AVERAGE_MEMACTIVITY:
 804                 *value = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
 805                         use_metrics_v2 ? metrics_v2->AverageUclkActivity :
 806                         metrics->AverageUclkActivity;
 807                 break;
 808         case METRICS_AVERAGE_SOCKETPOWER:
 809                 *value = use_metrics_v3 ? metrics_v3->AverageSocketPower << 8 :
 810                         use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 :
 811                         metrics->AverageSocketPower << 8;
 812                 break;
 813         case METRICS_TEMPERATURE_EDGE:
 814                 *value = (use_metrics_v3 ? metrics_v3->TemperatureEdge :
 815                         use_metrics_v2 ? metrics_v2->TemperatureEdge :
 816                         metrics->TemperatureEdge) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 817                 break;
 818         case METRICS_TEMPERATURE_HOTSPOT:
 819                 *value = (use_metrics_v3 ? metrics_v3->TemperatureHotspot :
 820                         use_metrics_v2 ? metrics_v2->TemperatureHotspot :
 821                         metrics->TemperatureHotspot) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 822                 break;
 823         case METRICS_TEMPERATURE_MEM:
 824                 *value = (use_metrics_v3 ? metrics_v3->TemperatureMem :
 825                         use_metrics_v2 ? metrics_v2->TemperatureMem :
 826                         metrics->TemperatureMem) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 827                 break;
 828         case METRICS_TEMPERATURE_VRGFX:
 829                 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
 830                         use_metrics_v2 ? metrics_v2->TemperatureVrGfx :
 831                         metrics->TemperatureVrGfx) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 832                 break;
 833         case METRICS_TEMPERATURE_VRSOC:
 834                 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
 835                         use_metrics_v2 ? metrics_v2->TemperatureVrSoc :
 836                         metrics->TemperatureVrSoc) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 837                 break;
 838         case METRICS_THROTTLER_STATUS:
 839                 *value = sienna_cichlid_get_throttler_status_locked(smu);
 840                 break;
 841         case METRICS_CURR_FANSPEED:
 842                 *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
 843                         use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
 844                 break;
 845         case METRICS_UNIQUE_ID_UPPER32:
 846                 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
 847                 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumUpper32 : 0;
 848                 break;
 849         case METRICS_UNIQUE_ID_LOWER32:
 850                 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
 851                 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumLower32 : 0;
 852                 break;
 853         case METRICS_SS_APU_SHARE:
 854                 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
 855                 *value = apu_percent;
 856                 break;
 857         case METRICS_SS_DGPU_SHARE:
 858                 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
 859                 *value = dgpu_percent;
 860                 break;
 861
 862         default:
 863                 *value = UINT_MAX;
 864                 break;
 865         }
 866
 867         return ret;
 868
 869 }
 870
 871 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
 872 {
 873         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 874
 875         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 876                                        GFP_KERNEL);
 877         if (!smu_dpm->dpm_context)
 878                 return -ENOMEM;
 879
 880         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 881
 882         return 0;
 883 }
 884
 885 static void sienna_cichlid_stb_init(struct smu_context *smu);
 886
 887 static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
 888 {
 889         int ret = 0;
 890
 891         ret = sienna_cichlid_tables_init(smu);
 892         if (ret)
 893                 return ret;
 894
 895         ret = sienna_cichlid_allocate_dpm_context(smu);
 896         if (ret)
 897                 return ret;
 898
 899         sienna_cichlid_stb_init(smu);
 900
 901         return smu_v11_0_init_smc_tables(smu);
 902 }
 903
 904 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 905 {
 906         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 907         struct smu_11_0_dpm_table *dpm_table;
 908         struct amdgpu_device *adev = smu->adev;
 909         int i, ret = 0;
 910         DpmDescriptor_t *table_member;
 911
 912         /* socclk dpm table setup */
 913         dpm_table = &dpm_context->dpm_tables.soc_table;
 914         GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
 915         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 916                 ret = smu_v11_0_set_single_dpm_table(smu,
 917                                                      SMU_SOCCLK,
 918                                                      dpm_table);
 919                 if (ret)
 920                         return ret;
 921                 dpm_table->is_fine_grained =
 922                         !table_member[PPCLK_SOCCLK].SnapToDiscrete;
 923         } else {
 924                 dpm_table->count = 1;
 925                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 926                 dpm_table->dpm_levels[0].enabled = true;
 927                 dpm_table->min = dpm_table->dpm_levels[0].value;
 928                 dpm_table->max = dpm_table->dpm_levels[0].value;
 929         }
 930
 931         /* gfxclk dpm table setup */
 932         dpm_table = &dpm_context->dpm_tables.gfx_table;
 933         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 934                 ret = smu_v11_0_set_single_dpm_table(smu,
 935                                                      SMU_GFXCLK,
 936                                                      dpm_table);
 937                 if (ret)
 938                         return ret;
 939                 dpm_table->is_fine_grained =
 940                         !table_member[PPCLK_GFXCLK].SnapToDiscrete;
 941         } else {
 942                 dpm_table->count = 1;
 943                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 944                 dpm_table->dpm_levels[0].enabled = true;
 945                 dpm_table->min = dpm_table->dpm_levels[0].value;
 946                 dpm_table->max = dpm_table->dpm_levels[0].value;
 947         }
 948
 949         /* uclk dpm table setup */
 950         dpm_table = &dpm_context->dpm_tables.uclk_table;
 951         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 952                 ret = smu_v11_0_set_single_dpm_table(smu,
 953                                                      SMU_UCLK,
 954                                                      dpm_table);
 955                 if (ret)
 956                         return ret;
 957                 dpm_table->is_fine_grained =
 958                         !table_member[PPCLK_UCLK].SnapToDiscrete;
 959         } else {
 960                 dpm_table->count = 1;
 961                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 962                 dpm_table->dpm_levels[0].enabled = true;
 963                 dpm_table->min = dpm_table->dpm_levels[0].value;
 964                 dpm_table->max = dpm_table->dpm_levels[0].value;
 965         }
 966
 967         /* fclk dpm table setup */
 968         dpm_table = &dpm_context->dpm_tables.fclk_table;
 969         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 970                 ret = smu_v11_0_set_single_dpm_table(smu,
 971                                                      SMU_FCLK,
 972                                                      dpm_table);
 973                 if (ret)
 974                         return ret;
 975                 dpm_table->is_fine_grained =
 976                         !table_member[PPCLK_FCLK].SnapToDiscrete;
 977         } else {
 978                 dpm_table->count = 1;
 979                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 980                 dpm_table->dpm_levels[0].enabled = true;
 981                 dpm_table->min = dpm_table->dpm_levels[0].value;
 982                 dpm_table->max = dpm_table->dpm_levels[0].value;
 983         }
 984
 985         /* vclk0/1 dpm table setup */
 986         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 987                 if (adev->vcn.harvest_config & (1 << i))
 988                         continue;
 989
 990                 dpm_table = &dpm_context->dpm_tables.vclk_table;
 991                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 992                         ret = smu_v11_0_set_single_dpm_table(smu,
 993                                                              i ? SMU_VCLK1 : SMU_VCLK,
 994                                                              dpm_table);
 995                         if (ret)
 996                                 return ret;
 997                         dpm_table->is_fine_grained =
 998                                 !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete;
 999                 } else {
1000                         dpm_table->count = 1;
1001                         dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
1002                         dpm_table->dpm_levels[0].enabled = true;
1003                         dpm_table->min = dpm_table->dpm_levels[0].value;
1004                         dpm_table->max = dpm_table->dpm_levels[0].value;
1005                 }
1006         }
1007
1008         /* dclk0/1 dpm table setup */
1009         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1010                 if (adev->vcn.harvest_config & (1 << i))
1011                         continue;
1012                 dpm_table = &dpm_context->dpm_tables.dclk_table;
1013                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1014                         ret = smu_v11_0_set_single_dpm_table(smu,
1015                                                              i ? SMU_DCLK1 : SMU_DCLK,
1016                                                              dpm_table);
1017                         if (ret)
1018                                 return ret;
1019                         dpm_table->is_fine_grained =
1020                                 !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete;
1021                 } else {
1022                         dpm_table->count = 1;
1023                         dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
1024                         dpm_table->dpm_levels[0].enabled = true;
1025                         dpm_table->min = dpm_table->dpm_levels[0].value;
1026                         dpm_table->max = dpm_table->dpm_levels[0].value;
1027                 }
1028         }
1029
1030         /* dcefclk dpm table setup */
1031         dpm_table = &dpm_context->dpm_tables.dcef_table;
1032         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1033                 ret = smu_v11_0_set_single_dpm_table(smu,
1034                                                      SMU_DCEFCLK,
1035                                                      dpm_table);
1036                 if (ret)
1037                         return ret;
1038                 dpm_table->is_fine_grained =
1039                         !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
1040         } else {
1041                 dpm_table->count = 1;
1042                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1043                 dpm_table->dpm_levels[0].enabled = true;
1044                 dpm_table->min = dpm_table->dpm_levels[0].value;
1045                 dpm_table->max = dpm_table->dpm_levels[0].value;
1046         }
1047
1048         /* pixelclk dpm table setup */
1049         dpm_table = &dpm_context->dpm_tables.pixel_table;
1050         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1051                 ret = smu_v11_0_set_single_dpm_table(smu,
1052                                                      SMU_PIXCLK,
1053                                                      dpm_table);
1054                 if (ret)
1055                         return ret;
1056                 dpm_table->is_fine_grained =
1057                         !table_member[PPCLK_PIXCLK].SnapToDiscrete;
1058         } else {
1059                 dpm_table->count = 1;
1060                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1061                 dpm_table->dpm_levels[0].enabled = true;
1062                 dpm_table->min = dpm_table->dpm_levels[0].value;
1063                 dpm_table->max = dpm_table->dpm_levels[0].value;
1064         }
1065
1066         /* displayclk dpm table setup */
1067         dpm_table = &dpm_context->dpm_tables.display_table;
1068         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1069                 ret = smu_v11_0_set_single_dpm_table(smu,
1070                                                      SMU_DISPCLK,
1071                                                      dpm_table);
1072                 if (ret)
1073                         return ret;
1074                 dpm_table->is_fine_grained =
1075                         !table_member[PPCLK_DISPCLK].SnapToDiscrete;
1076         } else {
1077                 dpm_table->count = 1;
1078                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1079                 dpm_table->dpm_levels[0].enabled = true;
1080                 dpm_table->min = dpm_table->dpm_levels[0].value;
1081                 dpm_table->max = dpm_table->dpm_levels[0].value;
1082         }
1083
1084         /* phyclk dpm table setup */
1085         dpm_table = &dpm_context->dpm_tables.phy_table;
1086         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1087                 ret = smu_v11_0_set_single_dpm_table(smu,
1088                                                      SMU_PHYCLK,
1089                                                      dpm_table);
1090                 if (ret)
1091                         return ret;
1092                 dpm_table->is_fine_grained =
1093                         !table_member[PPCLK_PHYCLK].SnapToDiscrete;
1094         } else {
1095                 dpm_table->count = 1;
1096                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1097                 dpm_table->dpm_levels[0].enabled = true;
1098                 dpm_table->min = dpm_table->dpm_levels[0].value;
1099                 dpm_table->max = dpm_table->dpm_levels[0].value;
1100         }
1101
1102         return 0;
1103 }
1104
1105 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1106 {
1107         struct amdgpu_device *adev = smu->adev;
1108         int i, ret = 0;
1109
1110         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1111                 if (adev->vcn.harvest_config & (1 << i))
1112                         continue;
1113                 /* vcn dpm on is a prerequisite for vcn power gate messages */
1114                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1115                         ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1116                                                               SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
1117                                                               0x10000 * i, NULL);
1118                         if (ret)
1119                                 return ret;
1120                 }
1121         }
1122
1123         return ret;
1124 }
1125
1126 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1127 {
1128         int ret = 0;
1129
1130         if (enable) {
1131                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1132                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
1133                         if (ret)
1134                                 return ret;
1135                 }
1136         } else {
1137                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1138                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
1139                         if (ret)
1140                                 return ret;
1141                 }
1142         }
1143
1144         return ret;
1145 }
1146
1147 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
1148                                        enum smu_clk_type clk_type,
1149                                        uint32_t *value)
1150 {
1151         MetricsMember_t member_type;
1152         int clk_id = 0;
1153
1154         clk_id = smu_cmn_to_asic_specific_index(smu,
1155                                                 CMN2ASIC_MAPPING_CLK,
1156                                                 clk_type);
1157         if (clk_id < 0)
1158                 return clk_id;
1159
1160         switch (clk_id) {
1161         case PPCLK_GFXCLK:
1162                 member_type = METRICS_CURR_GFXCLK;
1163                 break;
1164         case PPCLK_UCLK:
1165                 member_type = METRICS_CURR_UCLK;
1166                 break;
1167         case PPCLK_SOCCLK:
1168                 member_type = METRICS_CURR_SOCCLK;
1169                 break;
1170         case PPCLK_FCLK:
1171                 member_type = METRICS_CURR_FCLK;
1172                 break;
1173         case PPCLK_VCLK_0:
1174                 member_type = METRICS_CURR_VCLK;
1175                 break;
1176         case PPCLK_VCLK_1:
1177                 member_type = METRICS_CURR_VCLK1;
1178                 break;
1179         case PPCLK_DCLK_0:
1180                 member_type = METRICS_CURR_DCLK;
1181                 break;
1182         case PPCLK_DCLK_1:
1183                 member_type = METRICS_CURR_DCLK1;
1184                 break;
1185         case PPCLK_DCEFCLK:
1186                 member_type = METRICS_CURR_DCEFCLK;
1187                 break;
1188         default:
1189                 return -EINVAL;
1190         }
1191
1192         return sienna_cichlid_get_smu_metrics_data(smu,
1193                                                    member_type,
1194                                                    value);
1195
1196 }
1197
1198 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1199 {
1200         DpmDescriptor_t *dpm_desc = NULL;
1201         DpmDescriptor_t *table_member;
1202         uint32_t clk_index = 0;
1203
1204         GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
1205         clk_index = smu_cmn_to_asic_specific_index(smu,
1206                                                    CMN2ASIC_MAPPING_CLK,
1207                                                    clk_type);
1208         dpm_desc = &table_member[clk_index];
1209
1210         /* 0 - Fine grained DPM, 1 - Discrete DPM */
1211         return dpm_desc->SnapToDiscrete == 0;
1212 }
1213
1214 static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
1215                                                    enum SMU_11_0_7_ODFEATURE_CAP cap)
1216 {
1217         return od_table->cap[cap];
1218 }
1219
1220 static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
1221                                                 enum SMU_11_0_7_ODSETTING_ID setting,
1222                                                 uint32_t *min, uint32_t *max)
1223 {
1224         if (min)
1225                 *min = od_table->min[setting];
1226         if (max)
1227                 *max = od_table->max[setting];
1228 }
1229
1230 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1231                         enum smu_clk_type clk_type, char *buf)
1232 {
1233         struct amdgpu_device *adev = smu->adev;
1234         struct smu_table_context *table_context = &smu->smu_table;
1235         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1236         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1237         uint16_t *table_member;
1238
1239         struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1240         OverDriveTable_t *od_table =
1241                 (OverDriveTable_t *)table_context->overdrive_table;
1242         int i, size = 0, ret = 0;
1243         uint32_t cur_value = 0, value = 0, count = 0;
1244         uint32_t freq_values[3] = {0};
1245         uint32_t mark_index = 0;
1246         uint32_t gen_speed, lane_width;
1247         uint32_t min_value, max_value;
1248         uint32_t smu_version;
1249
1250         smu_cmn_get_sysfs_buf(&buf, &size);
1251
1252         switch (clk_type) {
1253         case SMU_GFXCLK:
1254         case SMU_SCLK:
1255         case SMU_SOCCLK:
1256         case SMU_MCLK:
1257         case SMU_UCLK:
1258         case SMU_FCLK:
1259         case SMU_VCLK:
1260         case SMU_VCLK1:
1261         case SMU_DCLK:
1262         case SMU_DCLK1:
1263         case SMU_DCEFCLK:
1264                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1265                 if (ret)
1266                         goto print_clk_out;
1267
1268                 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1269                 if (ret)
1270                         goto print_clk_out;
1271
1272                 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1273                         for (i = 0; i < count; i++) {
1274                                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1275                                 if (ret)
1276                                         goto print_clk_out;
1277
1278                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1279                                                 cur_value == value ? "*" : "");
1280                         }
1281                 } else {
1282                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1283                         if (ret)
1284                                 goto print_clk_out;
1285                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1286                         if (ret)
1287                                 goto print_clk_out;
1288
1289                         freq_values[1] = cur_value;
1290                         mark_index = cur_value == freq_values[0] ? 0 :
1291                                      cur_value == freq_values[2] ? 2 : 1;
1292
1293                         count = 3;
1294                         if (mark_index != 1) {
1295                                 count = 2;
1296                                 freq_values[1] = freq_values[2];
1297                         }
1298
1299                         for (i = 0; i < count; i++) {
1300                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
1301                                                 cur_value  == freq_values[i] ? "*" : "");
1302                         }
1303
1304                 }
1305                 break;
1306         case SMU_PCIE:
1307                 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1308                 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1309                 GET_PPTABLE_MEMBER(LclkFreq, &table_member);
1310                 for (i = 0; i < NUM_LINK_LEVELS; i++)
1311                         size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1312                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1313                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1314                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1315                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1316                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1317                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1318                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1319                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1320                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1321                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1322                                         table_member[i],
1323                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1324                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1325                                         "*" : "");
1326                 break;
1327         case SMU_OD_SCLK:
1328                 if (!smu->od_enabled || !od_table || !od_settings)
1329                         break;
1330
1331                 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1332                         break;
1333
1334                 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1335                 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1336                 break;
1337
1338         case SMU_OD_MCLK:
1339                 if (!smu->od_enabled || !od_table || !od_settings)
1340                         break;
1341
1342                 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1343                         break;
1344
1345                 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1346                 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
1347                 break;
1348
1349         case SMU_OD_VDDGFX_OFFSET:
1350                 if (!smu->od_enabled || !od_table || !od_settings)
1351                         break;
1352
1353                 /*
1354                  * OD GFX Voltage Offset functionality is supported only by 58.41.0
1355                  * and onwards SMU firmwares.
1356                  */
1357                 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1358                 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
1359                      (smu_version < 0x003a2900))
1360                         break;
1361
1362                 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1363                 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset);
1364                 break;
1365
1366         case SMU_OD_RANGE:
1367                 if (!smu->od_enabled || !od_table || !od_settings)
1368                         break;
1369
1370                 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1371
1372                 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1373                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1374                                                             &min_value, NULL);
1375                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1376                                                             NULL, &max_value);
1377                         size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1378                                         min_value, max_value);
1379                 }
1380
1381                 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1382                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1383                                                             &min_value, NULL);
1384                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1385                                                             NULL, &max_value);
1386                         size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1387                                         min_value, max_value);
1388                 }
1389                 break;
1390
1391         default:
1392                 break;
1393         }
1394
1395 print_clk_out:
1396         return size;
1397 }
1398
1399 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1400                                    enum smu_clk_type clk_type, uint32_t mask)
1401 {
1402         int ret = 0;
1403         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1404
1405         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1406         soft_max_level = mask ? (fls(mask) - 1) : 0;
1407
1408         switch (clk_type) {
1409         case SMU_GFXCLK:
1410         case SMU_SCLK:
1411         case SMU_SOCCLK:
1412         case SMU_MCLK:
1413         case SMU_UCLK:
1414         case SMU_FCLK:
1415                 /* There is only 2 levels for fine grained DPM */
1416                 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1417                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1418                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1419                 }
1420
1421                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1422                 if (ret)
1423                         goto forec_level_out;
1424
1425                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1426                 if (ret)
1427                         goto forec_level_out;
1428
1429                 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1430                 if (ret)
1431                         goto forec_level_out;
1432                 break;
1433         case SMU_DCEFCLK:
1434                 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1435                 break;
1436         default:
1437                 break;
1438         }
1439
1440 forec_level_out:
1441         return 0;
1442 }
1443
1444 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1445 {
1446         struct smu_11_0_dpm_context *dpm_context =
1447                                 smu->smu_dpm.dpm_context;
1448         struct smu_11_0_dpm_table *gfx_table =
1449                                 &dpm_context->dpm_tables.gfx_table;
1450         struct smu_11_0_dpm_table *mem_table =
1451                                 &dpm_context->dpm_tables.uclk_table;
1452         struct smu_11_0_dpm_table *soc_table =
1453                                 &dpm_context->dpm_tables.soc_table;
1454         struct smu_umd_pstate_table *pstate_table =
1455                                 &smu->pstate_table;
1456         struct amdgpu_device *adev = smu->adev;
1457
1458         pstate_table->gfxclk_pstate.min = gfx_table->min;
1459         pstate_table->gfxclk_pstate.peak = gfx_table->max;
1460
1461         pstate_table->uclk_pstate.min = mem_table->min;
1462         pstate_table->uclk_pstate.peak = mem_table->max;
1463
1464         pstate_table->socclk_pstate.min = soc_table->min;
1465         pstate_table->socclk_pstate.peak = soc_table->max;
1466
1467         switch (adev->asic_type) {
1468         case CHIP_SIENNA_CICHLID:
1469         case CHIP_NAVY_FLOUNDER:
1470                 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
1471                 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
1472                 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
1473                 break;
1474         case CHIP_DIMGREY_CAVEFISH:
1475                 pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;
1476                 pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;
1477                 pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;
1478                 break;
1479         case CHIP_BEIGE_GOBY:
1480                 pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;
1481                 pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;
1482                 pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;
1483                 break;
1484         default:
1485                 break;
1486         }
1487
1488         return 0;
1489 }
1490
1491 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1492 {
1493         int ret = 0;
1494         uint32_t max_freq = 0;
1495
1496         /* Sienna_Cichlid do not support to change display num currently */
1497         return 0;
1498 #if 0
1499         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1500         if (ret)
1501                 return ret;
1502 #endif
1503
1504         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1505                 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1506                 if (ret)
1507                         return ret;
1508                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1509                 if (ret)
1510                         return ret;
1511         }
1512
1513         return ret;
1514 }
1515
1516 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1517 {
1518         int ret = 0;
1519
1520         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1521             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1522             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1523 #if 0
1524                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1525                                                   smu->display_config->num_display,
1526                                                   NULL);
1527 #endif
1528                 if (ret)
1529                         return ret;
1530         }
1531
1532         return ret;
1533 }
1534
1535 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1536 {
1537         int ret = 0;
1538         uint64_t feature_enabled;
1539
1540         ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1541         if (ret)
1542                 return false;
1543
1544         return !!(feature_enabled & SMC_DPM_FEATURE);
1545 }
1546
1547 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1548                                             uint32_t *speed)
1549 {
1550         if (!speed)
1551                 return -EINVAL;
1552
1553         /*
1554          * For Sienna_Cichlid and later, the fan speed(rpm) reported
1555          * by pmfw is always trustable(even when the fan control feature
1556          * disabled or 0 RPM kicked in).
1557          */
1558         return sienna_cichlid_get_smu_metrics_data(smu,
1559                                                    METRICS_CURR_FANSPEED,
1560                                                    speed);
1561 }
1562
1563 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1564 {
1565         uint16_t *table_member;
1566
1567         GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1568         smu->fan_max_rpm = *table_member;
1569
1570         return 0;
1571 }
1572
1573 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1574 {
1575         DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1576         DpmActivityMonitorCoeffInt_t *activity_monitor =
1577                 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1578         uint32_t i, size = 0;
1579         int16_t workload_type = 0;
1580         static const char *title[] = {
1581                         "PROFILE_INDEX(NAME)",
1582                         "CLOCK_TYPE(NAME)",
1583                         "FPS",
1584                         "MinFreqType",
1585                         "MinActiveFreqType",
1586                         "MinActiveFreq",
1587                         "BoosterFreqType",
1588                         "BoosterFreq",
1589                         "PD_Data_limit_c",
1590                         "PD_Data_error_coeff",
1591                         "PD_Data_error_rate_coeff"};
1592         int result = 0;
1593
1594         if (!buf)
1595                 return -EINVAL;
1596
1597         size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1598                         title[0], title[1], title[2], title[3], title[4], title[5],
1599                         title[6], title[7], title[8], title[9], title[10]);
1600
1601         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1602                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1603                 workload_type = smu_cmn_to_asic_specific_index(smu,
1604                                                                CMN2ASIC_MAPPING_WORKLOAD,
1605                                                                i);
1606                 if (workload_type < 0)
1607                         return -EINVAL;
1608
1609                 result = smu_cmn_update_table(smu,
1610                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1611                                           (void *)(&activity_monitor_external), false);
1612                 if (result) {
1613                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1614                         return result;
1615                 }
1616
1617                 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1618                         i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1619
1620                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1621                         " ",
1622                         0,
1623                         "GFXCLK",
1624                         activity_monitor->Gfx_FPS,
1625                         activity_monitor->Gfx_MinFreqStep,
1626                         activity_monitor->Gfx_MinActiveFreqType,
1627                         activity_monitor->Gfx_MinActiveFreq,
1628                         activity_monitor->Gfx_BoosterFreqType,
1629                         activity_monitor->Gfx_BoosterFreq,
1630                         activity_monitor->Gfx_PD_Data_limit_c,
1631                         activity_monitor->Gfx_PD_Data_error_coeff,
1632                         activity_monitor->Gfx_PD_Data_error_rate_coeff);
1633
1634                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1635                         " ",
1636                         1,
1637                         "SOCCLK",
1638                         activity_monitor->Fclk_FPS,
1639                         activity_monitor->Fclk_MinFreqStep,
1640                         activity_monitor->Fclk_MinActiveFreqType,
1641                         activity_monitor->Fclk_MinActiveFreq,
1642                         activity_monitor->Fclk_BoosterFreqType,
1643                         activity_monitor->Fclk_BoosterFreq,
1644                         activity_monitor->Fclk_PD_Data_limit_c,
1645                         activity_monitor->Fclk_PD_Data_error_coeff,
1646                         activity_monitor->Fclk_PD_Data_error_rate_coeff);
1647
1648                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1649                         " ",
1650                         2,
1651                         "MEMLK",
1652                         activity_monitor->Mem_FPS,
1653                         activity_monitor->Mem_MinFreqStep,
1654                         activity_monitor->Mem_MinActiveFreqType,
1655                         activity_monitor->Mem_MinActiveFreq,
1656                         activity_monitor->Mem_BoosterFreqType,
1657                         activity_monitor->Mem_BoosterFreq,
1658                         activity_monitor->Mem_PD_Data_limit_c,
1659                         activity_monitor->Mem_PD_Data_error_coeff,
1660                         activity_monitor->Mem_PD_Data_error_rate_coeff);
1661         }
1662
1663         return size;
1664 }
1665
1666 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1667 {
1668
1669         DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1670         DpmActivityMonitorCoeffInt_t *activity_monitor =
1671                 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1672         int workload_type, ret = 0;
1673
1674         smu->power_profile_mode = input[size];
1675
1676         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1677                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1678                 return -EINVAL;
1679         }
1680
1681         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1682
1683                 ret = smu_cmn_update_table(smu,
1684                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1685                                        (void *)(&activity_monitor_external), false);
1686                 if (ret) {
1687                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1688                         return ret;
1689                 }
1690
1691                 switch (input[0]) {
1692                 case 0: /* Gfxclk */
1693                         activity_monitor->Gfx_FPS = input[1];
1694                         activity_monitor->Gfx_MinFreqStep = input[2];
1695                         activity_monitor->Gfx_MinActiveFreqType = input[3];
1696                         activity_monitor->Gfx_MinActiveFreq = input[4];
1697                         activity_monitor->Gfx_BoosterFreqType = input[5];
1698                         activity_monitor->Gfx_BoosterFreq = input[6];
1699                         activity_monitor->Gfx_PD_Data_limit_c = input[7];
1700                         activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1701                         activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
1702                         break;
1703                 case 1: /* Socclk */
1704                         activity_monitor->Fclk_FPS = input[1];
1705                         activity_monitor->Fclk_MinFreqStep = input[2];
1706                         activity_monitor->Fclk_MinActiveFreqType = input[3];
1707                         activity_monitor->Fclk_MinActiveFreq = input[4];
1708                         activity_monitor->Fclk_BoosterFreqType = input[5];
1709                         activity_monitor->Fclk_BoosterFreq = input[6];
1710                         activity_monitor->Fclk_PD_Data_limit_c = input[7];
1711                         activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1712                         activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
1713                         break;
1714                 case 2: /* Memlk */
1715                         activity_monitor->Mem_FPS = input[1];
1716                         activity_monitor->Mem_MinFreqStep = input[2];
1717                         activity_monitor->Mem_MinActiveFreqType = input[3];
1718                         activity_monitor->Mem_MinActiveFreq = input[4];
1719                         activity_monitor->Mem_BoosterFreqType = input[5];
1720                         activity_monitor->Mem_BoosterFreq = input[6];
1721                         activity_monitor->Mem_PD_Data_limit_c = input[7];
1722                         activity_monitor->Mem_PD_Data_error_coeff = input[8];
1723                         activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
1724                         break;
1725                 }
1726
1727                 ret = smu_cmn_update_table(smu,
1728                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1729                                        (void *)(&activity_monitor_external), true);
1730                 if (ret) {
1731                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1732                         return ret;
1733                 }
1734         }
1735
1736         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1737         workload_type = smu_cmn_to_asic_specific_index(smu,
1738                                                        CMN2ASIC_MAPPING_WORKLOAD,
1739                                                        smu->power_profile_mode);
1740         if (workload_type < 0)
1741                 return -EINVAL;
1742         smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1743                                     1 << workload_type, NULL);
1744
1745         return ret;
1746 }
1747
1748 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1749 {
1750         struct smu_clocks min_clocks = {0};
1751         struct pp_display_clock_request clock_req;
1752         int ret = 0;
1753
1754         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1755         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1756         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1757
1758         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1759                 clock_req.clock_type = amd_pp_dcef_clock;
1760                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1761
1762                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1763                 if (!ret) {
1764                         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1765                                 ret = smu_cmn_send_smc_msg_with_param(smu,
1766                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1767                                                                   min_clocks.dcef_clock_in_sr/100,
1768                                                                   NULL);
1769                                 if (ret) {
1770                                         dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1771                                         return ret;
1772                                 }
1773                         }
1774                 } else {
1775                         dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1776                 }
1777         }
1778
1779         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1780                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1781                 if (ret) {
1782                         dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1783                         return ret;
1784                 }
1785         }
1786
1787         return 0;
1788 }
1789
1790 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1791                                                struct pp_smu_wm_range_sets *clock_ranges)
1792 {
1793         Watermarks_t *table = smu->smu_table.watermarks_table;
1794         int ret = 0;
1795         int i;
1796
1797         if (clock_ranges) {
1798                 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1799                     clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1800                         return -EINVAL;
1801
1802                 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1803                         table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1804                                 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1805                         table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1806                                 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1807                         table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1808                                 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1809                         table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1810                                 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1811
1812                         table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1813                                 clock_ranges->reader_wm_sets[i].wm_inst;
1814                 }
1815
1816                 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1817                         table->WatermarkRow[WM_SOCCLK][i].MinClock =
1818                                 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1819                         table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1820                                 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1821                         table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1822                                 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1823                         table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1824                                 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1825
1826                         table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1827                                 clock_ranges->writer_wm_sets[i].wm_inst;
1828                 }
1829
1830                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1831         }
1832
1833         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1834              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1835                 ret = smu_cmn_write_watermarks_table(smu);
1836                 if (ret) {
1837                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1838                         return ret;
1839                 }
1840                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1841         }
1842
1843         return 0;
1844 }
1845
1846 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1847                                  enum amd_pp_sensors sensor,
1848                                  void *data, uint32_t *size)
1849 {
1850         int ret = 0;
1851         uint16_t *temp;
1852         struct amdgpu_device *adev = smu->adev;
1853
1854         if(!data || !size)
1855                 return -EINVAL;
1856
1857         switch (sensor) {
1858         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1859                 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1860                 *(uint16_t *)data = *temp;
1861                 *size = 4;
1862                 break;
1863         case AMDGPU_PP_SENSOR_MEM_LOAD:
1864                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1865                                                           METRICS_AVERAGE_MEMACTIVITY,
1866                                                           (uint32_t *)data);
1867                 *size = 4;
1868                 break;
1869         case AMDGPU_PP_SENSOR_GPU_LOAD:
1870                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1871                                                           METRICS_AVERAGE_GFXACTIVITY,
1872                                                           (uint32_t *)data);
1873                 *size = 4;
1874                 break;
1875         case AMDGPU_PP_SENSOR_GPU_POWER:
1876                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1877                                                           METRICS_AVERAGE_SOCKETPOWER,
1878                                                           (uint32_t *)data);
1879                 *size = 4;
1880                 break;
1881         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1882                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1883                                                           METRICS_TEMPERATURE_HOTSPOT,
1884                                                           (uint32_t *)data);
1885                 *size = 4;
1886                 break;
1887         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1888                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1889                                                           METRICS_TEMPERATURE_EDGE,
1890                                                           (uint32_t *)data);
1891                 *size = 4;
1892                 break;
1893         case AMDGPU_PP_SENSOR_MEM_TEMP:
1894                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1895                                                           METRICS_TEMPERATURE_MEM,
1896                                                           (uint32_t *)data);
1897                 *size = 4;
1898                 break;
1899         case AMDGPU_PP_SENSOR_GFX_MCLK:
1900                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1901                 *(uint32_t *)data *= 100;
1902                 *size = 4;
1903                 break;
1904         case AMDGPU_PP_SENSOR_GFX_SCLK:
1905                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1906                 *(uint32_t *)data *= 100;
1907                 *size = 4;
1908                 break;
1909         case AMDGPU_PP_SENSOR_VDDGFX:
1910                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1911                 *size = 4;
1912                 break;
1913         case AMDGPU_PP_SENSOR_SS_APU_SHARE:
1914                 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) {
1915                         ret = sienna_cichlid_get_smu_metrics_data(smu,
1916                                                 METRICS_SS_APU_SHARE, (uint32_t *)data);
1917                         *size = 4;
1918                 } else {
1919                         ret = -EOPNOTSUPP;
1920                 }
1921                 break;
1922         case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
1923                 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) {
1924                         ret = sienna_cichlid_get_smu_metrics_data(smu,
1925                                                 METRICS_SS_DGPU_SHARE, (uint32_t *)data);
1926                         *size = 4;
1927                 } else {
1928                         ret = -EOPNOTSUPP;
1929                 }
1930                 break;
1931         default:
1932                 ret = -EOPNOTSUPP;
1933                 break;
1934         }
1935
1936         return ret;
1937 }
1938
1939 static void sienna_cichlid_get_unique_id(struct smu_context *smu)
1940 {
1941         struct amdgpu_device *adev = smu->adev;
1942         uint32_t upper32 = 0, lower32 = 0;
1943
1944         /* Only supported as of version 0.58.83.0 and only on Sienna Cichlid */
1945         if (smu->smc_fw_version < 0x3A5300 ||
1946             smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7))
1947                 return;
1948
1949         if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32))
1950                 goto out;
1951         if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32))
1952                 goto out;
1953
1954 out:
1955
1956         adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1957         if (adev->serial[0] == '\0')
1958                 sprintf(adev->serial, "%016llx", adev->unique_id);
1959 }
1960
1961 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1962 {
1963         uint32_t num_discrete_levels = 0;
1964         uint16_t *dpm_levels = NULL;
1965         uint16_t i = 0;
1966         struct smu_table_context *table_context = &smu->smu_table;
1967         DpmDescriptor_t *table_member1;
1968         uint16_t *table_member2;
1969
1970         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1971                 return -EINVAL;
1972
1973         GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
1974         num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
1975         GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
1976         dpm_levels = table_member2;
1977
1978         if (num_discrete_levels == 0 || dpm_levels == NULL)
1979                 return -EINVAL;
1980
1981         *num_states = num_discrete_levels;
1982         for (i = 0; i < num_discrete_levels; i++) {
1983                 /* convert to khz */
1984                 *clocks_in_khz = (*dpm_levels) * 1000;
1985                 clocks_in_khz++;
1986                 dpm_levels++;
1987         }
1988
1989         return 0;
1990 }
1991
1992 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1993                                                 struct smu_temperature_range *range)
1994 {
1995         struct smu_table_context *table_context = &smu->smu_table;
1996         struct smu_11_0_7_powerplay_table *powerplay_table =
1997                                 table_context->power_play_table;
1998         uint16_t *table_member;
1999         uint16_t temp_edge, temp_hotspot, temp_mem;
2000
2001         if (!range)
2002                 return -EINVAL;
2003
2004         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2005
2006         GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
2007         temp_edge = table_member[TEMP_EDGE];
2008         temp_hotspot = table_member[TEMP_HOTSPOT];
2009         temp_mem = table_member[TEMP_MEM];
2010
2011         range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2012         range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
2013                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2014         range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2015         range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
2016                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2017         range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2018         range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
2019                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2020
2021         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2022
2023         return 0;
2024 }
2025
2026 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
2027                                                 bool disable_memory_clock_switch)
2028 {
2029         int ret = 0;
2030         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2031                 (struct smu_11_0_max_sustainable_clocks *)
2032                         smu->smu_table.max_sustainable_clocks;
2033         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2034         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2035
2036         if(smu->disable_uclk_switch == disable_memory_clock_switch)
2037                 return 0;
2038
2039         if(disable_memory_clock_switch)
2040                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
2041         else
2042                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
2043
2044         if(!ret)
2045                 smu->disable_uclk_switch = disable_memory_clock_switch;
2046
2047         return ret;
2048 }
2049
2050 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
2051                                          uint32_t pcie_gen_cap,
2052                                          uint32_t pcie_width_cap)
2053 {
2054         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2055
2056         uint32_t smu_pcie_arg;
2057         uint8_t *table_member1, *table_member2;
2058         int ret, i;
2059
2060         GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
2061         GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
2062
2063         /* lclk dpm table setup */
2064         for (i = 0; i < MAX_PCIE_CONF; i++) {
2065                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = table_member1[i];
2066                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = table_member2[i];
2067         }
2068
2069         for (i = 0; i < NUM_LINK_LEVELS; i++) {
2070                 smu_pcie_arg = (i << 16) |
2071                         ((table_member1[i] <= pcie_gen_cap) ?
2072                          (table_member1[i] << 8) :
2073                          (pcie_gen_cap << 8)) |
2074                         ((table_member2[i] <= pcie_width_cap) ?
2075                          table_member2[i] :
2076                          pcie_width_cap);
2077
2078                 ret = smu_cmn_send_smc_msg_with_param(smu,
2079                                 SMU_MSG_OverridePcieParameters,
2080                                 smu_pcie_arg,
2081                                 NULL);
2082                 if (ret)
2083                         return ret;
2084
2085                 if (table_member1[i] > pcie_gen_cap)
2086                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
2087                 if (table_member2[i] > pcie_width_cap)
2088                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
2089         }
2090
2091         return 0;
2092 }
2093
2094 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
2095                                 enum smu_clk_type clk_type,
2096                                 uint32_t *min, uint32_t *max)
2097 {
2098         return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
2099 }
2100
2101 static void sienna_cichlid_dump_od_table(struct smu_context *smu,
2102                                          OverDriveTable_t *od_table)
2103 {
2104         struct amdgpu_device *adev = smu->adev;
2105         uint32_t smu_version;
2106
2107         dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
2108                                                           od_table->GfxclkFmax);
2109         dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
2110                                                         od_table->UclkFmax);
2111
2112         smu_cmn_get_smc_version(smu, NULL, &smu_version);
2113         if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
2114                (smu_version < 0x003a2900)))
2115                 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
2116 }
2117
2118 static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
2119 {
2120         OverDriveTable_t *od_table =
2121                 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2122         OverDriveTable_t *boot_od_table =
2123                 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2124         OverDriveTable_t *user_od_table =
2125                 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
2126         int ret = 0;
2127
2128         /*
2129          * For S3/S4/Runpm resume, no need to setup those overdrive tables again as
2130          *   - either they already have the default OD settings got during cold bootup
2131          *   - or they have some user customized OD settings which cannot be overwritten
2132          */
2133         if (smu->adev->in_suspend)
2134                 return 0;
2135
2136         ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
2137                                    0, (void *)boot_od_table, false);
2138         if (ret) {
2139                 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2140                 return ret;
2141         }
2142
2143         sienna_cichlid_dump_od_table(smu, boot_od_table);
2144
2145         memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
2146         memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2147
2148         return 0;
2149 }
2150
2151 static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
2152                                                  struct smu_11_0_7_overdrive_table *od_table,
2153                                                  enum SMU_11_0_7_ODSETTING_ID setting,
2154                                                  uint32_t value)
2155 {
2156         if (value < od_table->min[setting]) {
2157                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
2158                                           setting, value, od_table->min[setting]);
2159                 return -EINVAL;
2160         }
2161         if (value > od_table->max[setting]) {
2162                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
2163                                           setting, value, od_table->max[setting]);
2164                 return -EINVAL;
2165         }
2166
2167         return 0;
2168 }
2169
2170 static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
2171                                             enum PP_OD_DPM_TABLE_COMMAND type,
2172                                             long input[], uint32_t size)
2173 {
2174         struct smu_table_context *table_context = &smu->smu_table;
2175         OverDriveTable_t *od_table =
2176                 (OverDriveTable_t *)table_context->overdrive_table;
2177         struct smu_11_0_7_overdrive_table *od_settings =
2178                 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
2179         struct amdgpu_device *adev = smu->adev;
2180         enum SMU_11_0_7_ODSETTING_ID freq_setting;
2181         uint16_t *freq_ptr;
2182         int i, ret = 0;
2183         uint32_t smu_version;
2184
2185         if (!smu->od_enabled) {
2186                 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2187                 return -EINVAL;
2188         }
2189
2190         if (!smu->od_settings) {
2191                 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2192                 return -ENOENT;
2193         }
2194
2195         if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2196                 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2197                 return -EINVAL;
2198         }
2199
2200         switch (type) {
2201         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2202                 if (!sienna_cichlid_is_od_feature_supported(od_settings,
2203                                                             SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
2204                         dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2205                         return -ENOTSUPP;
2206                 }
2207
2208                 for (i = 0; i < size; i += 2) {
2209                         if (i + 2 > size) {
2210                                 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2211                                 return -EINVAL;
2212                         }
2213
2214                         switch (input[i]) {
2215                         case 0:
2216                                 if (input[i + 1] > od_table->GfxclkFmax) {
2217                                         dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2218                                                 input[i + 1], od_table->GfxclkFmax);
2219                                         return -EINVAL;
2220                                 }
2221
2222                                 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
2223                                 freq_ptr = &od_table->GfxclkFmin;
2224                                 break;
2225
2226                         case 1:
2227                                 if (input[i + 1] < od_table->GfxclkFmin) {
2228                                         dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2229                                                 input[i + 1], od_table->GfxclkFmin);
2230                                         return -EINVAL;
2231                                 }
2232
2233                                 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2234                                 freq_ptr = &od_table->GfxclkFmax;
2235                                 break;
2236
2237                         default:
2238                                 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2239                                 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2240                                 return -EINVAL;
2241                         }
2242
2243                         ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2244                                                                     freq_setting, input[i + 1]);
2245                         if (ret)
2246                                 return ret;
2247
2248                         *freq_ptr = (uint16_t)input[i + 1];
2249                 }
2250                 break;
2251
2252         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2253                 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2254                         dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2255                         return -ENOTSUPP;
2256                 }
2257
2258                 for (i = 0; i < size; i += 2) {
2259                         if (i + 2 > size) {
2260                                 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2261                                 return -EINVAL;
2262                         }
2263
2264                         switch (input[i]) {
2265                         case 0:
2266                                 if (input[i + 1] > od_table->UclkFmax) {
2267                                         dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2268                                                 input[i + 1], od_table->UclkFmax);
2269                                         return -EINVAL;
2270                                 }
2271
2272                                 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2273                                 freq_ptr = &od_table->UclkFmin;
2274                                 break;
2275
2276                         case 1:
2277                                 if (input[i + 1] < od_table->UclkFmin) {
2278                                         dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2279                                                 input[i + 1], od_table->UclkFmin);
2280                                         return -EINVAL;
2281                                 }
2282
2283                                 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2284                                 freq_ptr = &od_table->UclkFmax;
2285                                 break;
2286
2287                         default:
2288                                 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2289                                 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2290                                 return -EINVAL;
2291                         }
2292
2293                         ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2294                                                                     freq_setting, input[i + 1]);
2295                         if (ret)
2296                                 return ret;
2297
2298                         *freq_ptr = (uint16_t)input[i + 1];
2299                 }
2300                 break;
2301
2302         case PP_OD_RESTORE_DEFAULT_TABLE:
2303                 memcpy(table_context->overdrive_table,
2304                                 table_context->boot_overdrive_table,
2305                                 sizeof(OverDriveTable_t));
2306                 fallthrough;
2307
2308         case PP_OD_COMMIT_DPM_TABLE:
2309                 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2310                         sienna_cichlid_dump_od_table(smu, od_table);
2311                         ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2312                         if (ret) {
2313                                 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2314                                 return ret;
2315                         }
2316                         memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2317                         smu->user_dpm_profile.user_od = true;
2318
2319                         if (!memcmp(table_context->user_overdrive_table,
2320                                     table_context->boot_overdrive_table,
2321                                     sizeof(OverDriveTable_t)))
2322                                 smu->user_dpm_profile.user_od = false;
2323                 }
2324                 break;
2325
2326         case PP_OD_EDIT_VDDGFX_OFFSET:
2327                 if (size != 1) {
2328                         dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2329                         return -EINVAL;
2330                 }
2331
2332                 /*
2333                  * OD GFX Voltage Offset functionality is supported only by 58.41.0
2334                  * and onwards SMU firmwares.
2335                  */
2336                 smu_cmn_get_smc_version(smu, NULL, &smu_version);
2337                 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
2338                      (smu_version < 0x003a2900)) {
2339                         dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2340                                                 "only by 58.41.0 and onwards SMU firmwares!\n");
2341                         return -EOPNOTSUPP;
2342                 }
2343
2344                 od_table->VddGfxOffset = (int16_t)input[0];
2345
2346                 sienna_cichlid_dump_od_table(smu, od_table);
2347                 break;
2348
2349         default:
2350                 return -ENOSYS;
2351         }
2352
2353         return ret;
2354 }
2355
2356 static int sienna_cichlid_run_btc(struct smu_context *smu)
2357 {
2358         int res;
2359
2360         res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2361         if (res)
2362                 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2363
2364         return res;
2365 }
2366
2367 static int sienna_cichlid_baco_enter(struct smu_context *smu)
2368 {
2369         struct amdgpu_device *adev = smu->adev;
2370
2371         if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
2372                 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2373         else
2374                 return smu_v11_0_baco_enter(smu);
2375 }
2376
2377 static int sienna_cichlid_baco_exit(struct smu_context *smu)
2378 {
2379         struct amdgpu_device *adev = smu->adev;
2380
2381         if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2382                 /* Wait for PMFW handling for the Dstate change */
2383                 msleep(10);
2384                 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2385         } else {
2386                 return smu_v11_0_baco_exit(smu);
2387         }
2388 }
2389
2390 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2391 {
2392         struct amdgpu_device *adev = smu->adev;
2393         uint32_t val;
2394         u32 smu_version;
2395
2396         /**
2397          * SRIOV env will not support SMU mode1 reset
2398          * PM FW support mode1 reset from 58.26
2399          */
2400         smu_cmn_get_smc_version(smu, NULL, &smu_version);
2401         if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2402                 return false;
2403
2404         /**
2405          * mode1 reset relies on PSP, so we should check if
2406          * PSP is alive.
2407          */
2408         val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2409         return val != 0x0;
2410 }
2411
2412 static void beige_goby_dump_pptable(struct smu_context *smu)
2413 {
2414         struct smu_table_context *table_context = &smu->smu_table;
2415         PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2416         int i;
2417
2418         dev_info(smu->adev->dev, "Dumped PPTable:\n");
2419
2420         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2421         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2422         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2423
2424         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2425                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2426                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2427                 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2428                 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2429         }
2430
2431         for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2432                 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2433                 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2434         }
2435
2436         for (i = 0; i < TEMP_COUNT; i++) {
2437                 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2438         }
2439
2440         dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2441         dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2442         dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2443         dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2444         dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2445
2446         dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2447         for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2448                 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2449                 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2450         }
2451         dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2452
2453         dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2454
2455         dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2456         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2457         dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2458         dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2459
2460         dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2461
2462         dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2463
2464         dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2465         dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2466         dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2467         dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2468
2469         dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2470         dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2471
2472         dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2473         dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2474         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2475         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2476         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2477         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2478         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2479         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2480
2481         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2482                         "  .VoltageMode          = 0x%02x\n"
2483                         "  .SnapToDiscrete       = 0x%02x\n"
2484                         "  .NumDiscreteLevels    = 0x%02x\n"
2485                         "  .padding              = 0x%02x\n"
2486                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2487                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2488                         "  .SsFmin               = 0x%04x\n"
2489                         "  .Padding_16           = 0x%04x\n",
2490                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2491                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2492                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2493                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2494                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2495                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2496                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2497                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2498                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2499                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2500                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2501
2502         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2503                         "  .VoltageMode          = 0x%02x\n"
2504                         "  .SnapToDiscrete       = 0x%02x\n"
2505                         "  .NumDiscreteLevels    = 0x%02x\n"
2506                         "  .padding              = 0x%02x\n"
2507                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2508                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2509                         "  .SsFmin               = 0x%04x\n"
2510                         "  .Padding_16           = 0x%04x\n",
2511                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2512                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2513                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2514                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2515                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2516                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2517                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2518                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2519                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2520                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2521                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2522
2523         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2524                         "  .VoltageMode          = 0x%02x\n"
2525                         "  .SnapToDiscrete       = 0x%02x\n"
2526                         "  .NumDiscreteLevels    = 0x%02x\n"
2527                         "  .padding              = 0x%02x\n"
2528                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2529                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2530                         "  .SsFmin               = 0x%04x\n"
2531                         "  .Padding_16           = 0x%04x\n",
2532                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2533                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2534                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2535                         pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2536                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2537                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2538                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2539                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2540                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2541                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2542                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2543
2544         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2545                         "  .VoltageMode          = 0x%02x\n"
2546                         "  .SnapToDiscrete       = 0x%02x\n"
2547                         "  .NumDiscreteLevels    = 0x%02x\n"
2548                         "  .padding              = 0x%02x\n"
2549                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2550                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2551                         "  .SsFmin               = 0x%04x\n"
2552                         "  .Padding_16           = 0x%04x\n",
2553                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2554                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2555                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2556                         pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2557                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2558                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2559                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2560                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2561                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2562                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2563                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2564
2565         dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2566                         "  .VoltageMode          = 0x%02x\n"
2567                         "  .SnapToDiscrete       = 0x%02x\n"
2568                         "  .NumDiscreteLevels    = 0x%02x\n"
2569                         "  .padding              = 0x%02x\n"
2570                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2571                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2572                         "  .SsFmin               = 0x%04x\n"
2573                         "  .Padding_16           = 0x%04x\n",
2574                         pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2575                         pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2576                         pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2577                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2578                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2579                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2580                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2581                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2582                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2583                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2584                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2585
2586         dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2587                         "  .VoltageMode          = 0x%02x\n"
2588                         "  .SnapToDiscrete       = 0x%02x\n"
2589                         "  .NumDiscreteLevels    = 0x%02x\n"
2590                         "  .padding              = 0x%02x\n"
2591                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2592                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2593                         "  .SsFmin               = 0x%04x\n"
2594                         "  .Padding_16           = 0x%04x\n",
2595                         pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2596                         pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2597                         pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2598                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2599                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2600                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2601                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2602                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2603                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2604                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2605                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2606
2607         dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2608                         "  .VoltageMode          = 0x%02x\n"
2609                         "  .SnapToDiscrete       = 0x%02x\n"
2610                         "  .NumDiscreteLevels    = 0x%02x\n"
2611                         "  .padding              = 0x%02x\n"
2612                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2613                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2614                         "  .SsFmin               = 0x%04x\n"
2615                         "  .Padding_16           = 0x%04x\n",
2616                         pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2617                         pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2618                         pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2619                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2620                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2621                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2622                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2623                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2624                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2625                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2626                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2627
2628         dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2629                         "  .VoltageMode          = 0x%02x\n"
2630                         "  .SnapToDiscrete       = 0x%02x\n"
2631                         "  .NumDiscreteLevels    = 0x%02x\n"
2632                         "  .padding              = 0x%02x\n"
2633                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2634                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2635                         "  .SsFmin               = 0x%04x\n"
2636                         "  .Padding_16           = 0x%04x\n",
2637                         pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2638                         pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2639                         pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2640                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2641                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2642                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2643                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2644                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2645                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2646                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2647                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2648
2649         dev_info(smu->adev->dev, "FreqTableGfx\n");
2650         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2651                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2652
2653         dev_info(smu->adev->dev, "FreqTableVclk\n");
2654         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2655                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2656
2657         dev_info(smu->adev->dev, "FreqTableDclk\n");
2658         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2659                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2660
2661         dev_info(smu->adev->dev, "FreqTableSocclk\n");
2662         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2663                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2664
2665         dev_info(smu->adev->dev, "FreqTableUclk\n");
2666         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2667                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2668
2669         dev_info(smu->adev->dev, "FreqTableFclk\n");
2670         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2671                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2672
2673         dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2674         dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2675         dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2676         dev_info(smu->adev->dev, "  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2677         dev_info(smu->adev->dev, "  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2678         dev_info(smu->adev->dev, "  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2679         dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2680         dev_info(smu->adev->dev, "  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2681         dev_info(smu->adev->dev, "  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2682
2683         dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2684         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2685                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2686
2687         dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2688         dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2689
2690         dev_info(smu->adev->dev, "Mp0clkFreq\n");
2691         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2692                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2693
2694         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2695         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2696                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2697
2698         dev_info(smu->adev->dev, "MemVddciVoltage\n");
2699         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2700                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2701
2702         dev_info(smu->adev->dev, "MemMvddVoltage\n");
2703         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2704                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2705
2706         dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2707         dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2708         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2709         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2710         dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2711
2712         dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2713
2714         dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2715         dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2716         dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2717         dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2718         dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2719         dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2720         dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2721         dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2722         dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2723         dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2724         dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2725
2726         dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2727         dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2728         dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2729         dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2730         dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2731         dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2732
2733         dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2734         dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2735         dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2736         dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2737         dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2738
2739         dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2740         for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2741                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2742
2743         dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2744         dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2745         dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2746         dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2747
2748         dev_info(smu->adev->dev, "UclkDpmPstates\n");
2749         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2750                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2751
2752         dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2753         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2754                 pptable->UclkDpmSrcFreqRange.Fmin);
2755         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2756                 pptable->UclkDpmSrcFreqRange.Fmax);
2757         dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2758         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2759                 pptable->UclkDpmTargFreqRange.Fmin);
2760         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2761                 pptable->UclkDpmTargFreqRange.Fmax);
2762         dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2763         dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2764
2765         dev_info(smu->adev->dev, "PcieGenSpeed\n");
2766         for (i = 0; i < NUM_LINK_LEVELS; i++)
2767                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2768
2769         dev_info(smu->adev->dev, "PcieLaneCount\n");
2770         for (i = 0; i < NUM_LINK_LEVELS; i++)
2771                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2772
2773         dev_info(smu->adev->dev, "LclkFreq\n");
2774         for (i = 0; i < NUM_LINK_LEVELS; i++)
2775                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2776
2777         dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2778         dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2779
2780         dev_info(smu->adev->dev, "FanGain\n");
2781         for (i = 0; i < TEMP_COUNT; i++)
2782                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2783
2784         dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2785         dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2786         dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2787         dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2788         dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2789         dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2790         dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2791         dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2792         dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2793         dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2794         dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2795         dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2796
2797         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2798         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2799         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2800         dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2801
2802         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2803         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2804         dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2805         dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2806
2807         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2808                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2809                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2810                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2811         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2812                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2813                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2814                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2815         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2816                         pptable->dBtcGbGfxPll.a,
2817                         pptable->dBtcGbGfxPll.b,
2818                         pptable->dBtcGbGfxPll.c);
2819         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2820                         pptable->dBtcGbGfxDfll.a,
2821                         pptable->dBtcGbGfxDfll.b,
2822                         pptable->dBtcGbGfxDfll.c);
2823         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2824                         pptable->dBtcGbSoc.a,
2825                         pptable->dBtcGbSoc.b,
2826                         pptable->dBtcGbSoc.c);
2827         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2828                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2829                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2830         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2831                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2832                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2833
2834         dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2835         for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2836                 dev_info(smu->adev->dev, "              Fset[%d] = 0x%x\n",
2837                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2838                 dev_info(smu->adev->dev, "              Vdroop[%d] = 0x%x\n",
2839                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2840         }
2841
2842         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2843                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2844                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2845                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2846         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2847                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2848                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2849                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2850
2851         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2852         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2853
2854         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2855         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2856         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2857         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2858
2859         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2860         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2861         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2862         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2863
2864         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2865         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2866
2867         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2868         for (i = 0; i < NUM_XGMI_LEVELS; i++)
2869                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2870         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2871         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2872
2873         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2874         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2875                         pptable->ReservedEquation0.a,
2876                         pptable->ReservedEquation0.b,
2877                         pptable->ReservedEquation0.c);
2878         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2879                         pptable->ReservedEquation1.a,
2880                         pptable->ReservedEquation1.b,
2881                         pptable->ReservedEquation1.c);
2882         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2883                         pptable->ReservedEquation2.a,
2884                         pptable->ReservedEquation2.b,
2885                         pptable->ReservedEquation2.c);
2886         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2887                         pptable->ReservedEquation3.a,
2888                         pptable->ReservedEquation3.b,
2889                         pptable->ReservedEquation3.c);
2890
2891         dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2892         dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2893         dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2894         dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2895         dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2896         dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2897         dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2898         dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2899
2900         dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2901         dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2902         dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2903         dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2904         dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2905         dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2906
2907         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2908                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2909                 dev_info(smu->adev->dev, "                   .Enabled = 0x%x\n",
2910                                 pptable->I2cControllers[i].Enabled);
2911                 dev_info(smu->adev->dev, "                   .Speed = 0x%x\n",
2912                                 pptable->I2cControllers[i].Speed);
2913                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
2914                                 pptable->I2cControllers[i].SlaveAddress);
2915                 dev_info(smu->adev->dev, "                   .ControllerPort = 0x%x\n",
2916                                 pptable->I2cControllers[i].ControllerPort);
2917                 dev_info(smu->adev->dev, "                   .ControllerName = 0x%x\n",
2918                                 pptable->I2cControllers[i].ControllerName);
2919                 dev_info(smu->adev->dev, "                   .ThermalThrottler = 0x%x\n",
2920                                 pptable->I2cControllers[i].ThermalThrotter);
2921                 dev_info(smu->adev->dev, "                   .I2cProtocol = 0x%x\n",
2922                                 pptable->I2cControllers[i].I2cProtocol);
2923                 dev_info(smu->adev->dev, "                   .PaddingConfig = 0x%x\n",
2924                                 pptable->I2cControllers[i].PaddingConfig);
2925         }
2926
2927         dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2928         dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2929         dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2930         dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2931
2932         dev_info(smu->adev->dev, "Board Parameters:\n");
2933         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2934         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2935         dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2936         dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2937         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2938         dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2939         dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2940         dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2941
2942         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2943         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2944         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2945
2946         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2947         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2948         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2949
2950         dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2951         dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2952         dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2953
2954         dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2955         dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2956         dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2957
2958         dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2959
2960         dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2961         dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2962         dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2963         dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2964         dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2965         dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2966         dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2967         dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2968         dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2969         dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2970         dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2971         dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2972         dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2973         dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2974         dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2975         dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2976
2977         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2978         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2979         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
2980
2981         dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2982         dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2983         dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
2984
2985         dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
2986         dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2987
2988         dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2989         dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2990         dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2991
2992         dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2993         dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2994         dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2995         dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2996         dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2997
2998         dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2999         dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3000
3001         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3002         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3003                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3004         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3005         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3006                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3007         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3008         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3009                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3010         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3011         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3012                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3013
3014         dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3015         dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3016         dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3017         dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3018
3019         dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3020         dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3021         dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3022         dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3023         dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3024         dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3025         dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3026         dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3027         dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3028         dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3029         dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3030
3031         dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3032         dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3033         dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3034         dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3035         dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3036         dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3037         dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3038         dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3039 }
3040
3041 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
3042 {
3043         struct smu_table_context *table_context = &smu->smu_table;
3044         PPTable_t *pptable = table_context->driver_pptable;
3045         int i;
3046
3047         if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) {
3048                 beige_goby_dump_pptable(smu);
3049                 return;
3050         }
3051
3052         dev_info(smu->adev->dev, "Dumped PPTable:\n");
3053
3054         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
3055         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
3056         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
3057
3058         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
3059                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
3060                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
3061                 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
3062                 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
3063         }
3064
3065         for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
3066                 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
3067                 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
3068         }
3069
3070         for (i = 0; i < TEMP_COUNT; i++) {
3071                 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
3072         }
3073
3074         dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
3075         dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
3076         dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
3077         dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
3078         dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
3079
3080         dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
3081         for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
3082                 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
3083                 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
3084         }
3085         dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
3086
3087         dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
3088
3089         dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
3090         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
3091         dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
3092         dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
3093
3094         dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
3095         dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
3096
3097         dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
3098         dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
3099         dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
3100         dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
3101
3102         dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
3103         dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
3104         dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
3105         dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
3106
3107         dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
3108         dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
3109
3110         dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
3111         dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
3112         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
3113         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
3114         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
3115         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
3116         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
3117         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
3118
3119         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
3120                         "  .VoltageMode          = 0x%02x\n"
3121                         "  .SnapToDiscrete       = 0x%02x\n"
3122                         "  .NumDiscreteLevels    = 0x%02x\n"
3123                         "  .padding              = 0x%02x\n"
3124                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3125                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3126                         "  .SsFmin               = 0x%04x\n"
3127                         "  .Padding_16           = 0x%04x\n",
3128                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
3129                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
3130                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
3131                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
3132                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
3133                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
3134                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
3135                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
3136                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
3137                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
3138                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
3139
3140         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
3141                         "  .VoltageMode          = 0x%02x\n"
3142                         "  .SnapToDiscrete       = 0x%02x\n"
3143                         "  .NumDiscreteLevels    = 0x%02x\n"
3144                         "  .padding              = 0x%02x\n"
3145                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3146                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3147                         "  .SsFmin               = 0x%04x\n"
3148                         "  .Padding_16           = 0x%04x\n",
3149                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
3150                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
3151                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
3152                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
3153                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
3154                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
3155                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
3156                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
3157                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
3158                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
3159                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
3160
3161         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
3162                         "  .VoltageMode          = 0x%02x\n"
3163                         "  .SnapToDiscrete       = 0x%02x\n"
3164                         "  .NumDiscreteLevels    = 0x%02x\n"
3165                         "  .padding              = 0x%02x\n"
3166                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3167                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3168                         "  .SsFmin               = 0x%04x\n"
3169                         "  .Padding_16           = 0x%04x\n",
3170                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
3171                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
3172                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
3173                         pptable->DpmDescriptor[PPCLK_UCLK].Padding,
3174                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
3175                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
3176                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
3177                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
3178                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
3179                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
3180                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
3181
3182         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
3183                         "  .VoltageMode          = 0x%02x\n"
3184                         "  .SnapToDiscrete       = 0x%02x\n"
3185                         "  .NumDiscreteLevels    = 0x%02x\n"
3186                         "  .padding              = 0x%02x\n"
3187                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3188                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3189                         "  .SsFmin               = 0x%04x\n"
3190                         "  .Padding_16           = 0x%04x\n",
3191                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
3192                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
3193                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
3194                         pptable->DpmDescriptor[PPCLK_FCLK].Padding,
3195                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
3196                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
3197                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
3198                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
3199                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
3200                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
3201                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
3202
3203         dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
3204                         "  .VoltageMode          = 0x%02x\n"
3205                         "  .SnapToDiscrete       = 0x%02x\n"
3206                         "  .NumDiscreteLevels    = 0x%02x\n"
3207                         "  .padding              = 0x%02x\n"
3208                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3209                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3210                         "  .SsFmin               = 0x%04x\n"
3211                         "  .Padding_16           = 0x%04x\n",
3212                         pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
3213                         pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
3214                         pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
3215                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
3216                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
3217                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
3218                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
3219                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
3220                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
3221                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
3222                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
3223
3224         dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
3225                         "  .VoltageMode          = 0x%02x\n"
3226                         "  .SnapToDiscrete       = 0x%02x\n"
3227                         "  .NumDiscreteLevels    = 0x%02x\n"
3228                         "  .padding              = 0x%02x\n"
3229                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3230                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3231                         "  .SsFmin               = 0x%04x\n"
3232                         "  .Padding_16           = 0x%04x\n",
3233                         pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
3234                         pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3235                         pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3236                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3237                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3238                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3239                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3240                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3241                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3242                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3243                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3244
3245         dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
3246                         "  .VoltageMode          = 0x%02x\n"
3247                         "  .SnapToDiscrete       = 0x%02x\n"
3248                         "  .NumDiscreteLevels    = 0x%02x\n"
3249                         "  .padding              = 0x%02x\n"
3250                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3251                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3252                         "  .SsFmin               = 0x%04x\n"
3253                         "  .Padding_16           = 0x%04x\n",
3254                         pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3255                         pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3256                         pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3257                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3258                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3259                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3260                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3261                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3262                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3263                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3264                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3265
3266         dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
3267                         "  .VoltageMode          = 0x%02x\n"
3268                         "  .SnapToDiscrete       = 0x%02x\n"
3269                         "  .NumDiscreteLevels    = 0x%02x\n"
3270                         "  .padding              = 0x%02x\n"
3271                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3272                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3273                         "  .SsFmin               = 0x%04x\n"
3274                         "  .Padding_16           = 0x%04x\n",
3275                         pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3276                         pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3277                         pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3278                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3279                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3280                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3281                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3282                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3283                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3284                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3285                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3286
3287         dev_info(smu->adev->dev, "FreqTableGfx\n");
3288         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
3289                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
3290
3291         dev_info(smu->adev->dev, "FreqTableVclk\n");
3292         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
3293                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
3294
3295         dev_info(smu->adev->dev, "FreqTableDclk\n");
3296         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
3297                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
3298
3299         dev_info(smu->adev->dev, "FreqTableSocclk\n");
3300         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
3301                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
3302
3303         dev_info(smu->adev->dev, "FreqTableUclk\n");
3304         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3305                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
3306
3307         dev_info(smu->adev->dev, "FreqTableFclk\n");
3308         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
3309                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3310
3311         dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3312         dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3313         dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3314         dev_info(smu->adev->dev, "  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3315         dev_info(smu->adev->dev, "  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3316         dev_info(smu->adev->dev, "  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3317         dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3318         dev_info(smu->adev->dev, "  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3319         dev_info(smu->adev->dev, "  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3320
3321         dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
3322         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3323                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
3324
3325         dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3326         dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
3327
3328         dev_info(smu->adev->dev, "Mp0clkFreq\n");
3329         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3330                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
3331
3332         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
3333         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3334                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
3335
3336         dev_info(smu->adev->dev, "MemVddciVoltage\n");
3337         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3338                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
3339
3340         dev_info(smu->adev->dev, "MemMvddVoltage\n");
3341         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3342                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3343
3344         dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3345         dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3346         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3347         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3348         dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3349
3350         dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3351
3352         dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3353         dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3354         dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3355         dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3356         dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3357         dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3358         dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3359         dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3360         dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3361         dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3362         dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3363
3364         dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3365         dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3366         dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3367         dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3368         dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3369         dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3370
3371         dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3372         dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3373         dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3374         dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3375         dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3376
3377         dev_info(smu->adev->dev, "FlopsPerByteTable\n");
3378         for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
3379                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
3380
3381         dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3382         dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3383         dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3384         dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
3385
3386         dev_info(smu->adev->dev, "UclkDpmPstates\n");
3387         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3388                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
3389
3390         dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3391         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
3392                 pptable->UclkDpmSrcFreqRange.Fmin);
3393         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
3394                 pptable->UclkDpmSrcFreqRange.Fmax);
3395         dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3396         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
3397                 pptable->UclkDpmTargFreqRange.Fmin);
3398         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
3399                 pptable->UclkDpmTargFreqRange.Fmax);
3400         dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3401         dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
3402
3403         dev_info(smu->adev->dev, "PcieGenSpeed\n");
3404         for (i = 0; i < NUM_LINK_LEVELS; i++)
3405                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
3406
3407         dev_info(smu->adev->dev, "PcieLaneCount\n");
3408         for (i = 0; i < NUM_LINK_LEVELS; i++)
3409                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
3410
3411         dev_info(smu->adev->dev, "LclkFreq\n");
3412         for (i = 0; i < NUM_LINK_LEVELS; i++)
3413                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
3414
3415         dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3416         dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
3417
3418         dev_info(smu->adev->dev, "FanGain\n");
3419         for (i = 0; i < TEMP_COUNT; i++)
3420                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3421
3422         dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3423         dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3424         dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3425         dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3426         dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3427         dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3428         dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3429         dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3430         dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3431         dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3432         dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3433         dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3434
3435         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3436         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3437         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3438         dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3439
3440         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3441         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3442         dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3443         dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3444
3445         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3446                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3447                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3448                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
3449         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3450                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3451                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3452                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
3453         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
3454                         pptable->dBtcGbGfxPll.a,
3455                         pptable->dBtcGbGfxPll.b,
3456                         pptable->dBtcGbGfxPll.c);
3457         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
3458                         pptable->dBtcGbGfxDfll.a,
3459                         pptable->dBtcGbGfxDfll.b,
3460                         pptable->dBtcGbGfxDfll.c);
3461         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
3462                         pptable->dBtcGbSoc.a,
3463                         pptable->dBtcGbSoc.b,
3464                         pptable->dBtcGbSoc.c);
3465         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
3466                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3467                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
3468         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
3469                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3470                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3471
3472         dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
3473         for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
3474                 dev_info(smu->adev->dev, "              Fset[%d] = 0x%x\n",
3475                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
3476                 dev_info(smu->adev->dev, "              Vdroop[%d] = 0x%x\n",
3477                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3478         }
3479
3480         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3481                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3482                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3483                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
3484         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3485                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3486                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3487                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3488
3489         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3490         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
3491
3492         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3493         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3494         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3495         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
3496
3497         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3498         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3499         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3500         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
3501
3502         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3503         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
3504
3505         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
3506         for (i = 0; i < NUM_XGMI_LEVELS; i++)
3507                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3508         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3509         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
3510
3511         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3512         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
3513                         pptable->ReservedEquation0.a,
3514                         pptable->ReservedEquation0.b,
3515                         pptable->ReservedEquation0.c);
3516         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
3517                         pptable->ReservedEquation1.a,
3518                         pptable->ReservedEquation1.b,
3519                         pptable->ReservedEquation1.c);
3520         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
3521                         pptable->ReservedEquation2.a,
3522                         pptable->ReservedEquation2.b,
3523                         pptable->ReservedEquation2.c);
3524         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
3525                         pptable->ReservedEquation3.a,
3526                         pptable->ReservedEquation3.b,
3527                         pptable->ReservedEquation3.c);
3528
3529         dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3530         dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3531         dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3532         dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3533         dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3534         dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3535         dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3536         dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
3537
3538         dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3539         dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3540         dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3541         dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3542         dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3543         dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
3544
3545         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
3546                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3547                 dev_info(smu->adev->dev, "                   .Enabled = 0x%x\n",
3548                                 pptable->I2cControllers[i].Enabled);
3549                 dev_info(smu->adev->dev, "                   .Speed = 0x%x\n",
3550                                 pptable->I2cControllers[i].Speed);
3551                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
3552                                 pptable->I2cControllers[i].SlaveAddress);
3553                 dev_info(smu->adev->dev, "                   .ControllerPort = 0x%x\n",
3554                                 pptable->I2cControllers[i].ControllerPort);
3555                 dev_info(smu->adev->dev, "                   .ControllerName = 0x%x\n",
3556                                 pptable->I2cControllers[i].ControllerName);
3557                 dev_info(smu->adev->dev, "                   .ThermalThrottler = 0x%x\n",
3558                                 pptable->I2cControllers[i].ThermalThrotter);
3559                 dev_info(smu->adev->dev, "                   .I2cProtocol = 0x%x\n",
3560                                 pptable->I2cControllers[i].I2cProtocol);
3561                 dev_info(smu->adev->dev, "                   .PaddingConfig = 0x%x\n",
3562                                 pptable->I2cControllers[i].PaddingConfig);
3563         }
3564
3565         dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3566         dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3567         dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3568         dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3569
3570         dev_info(smu->adev->dev, "Board Parameters:\n");
3571         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3572         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3573         dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3574         dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3575         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3576         dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3577         dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3578         dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3579
3580         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3581         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3582         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3583
3584         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3585         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3586         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3587
3588         dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3589         dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3590         dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3591
3592         dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3593         dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3594         dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3595
3596         dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3597
3598         dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3599         dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3600         dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3601         dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3602         dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3603         dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3604         dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3605         dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3606         dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3607         dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3608         dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3609         dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3610         dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3611         dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3612         dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3613         dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3614
3615         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3616         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3617         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
3618
3619         dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3620         dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3621         dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
3622
3623         dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3624         dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3625
3626         dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3627         dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3628         dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3629
3630         dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3631         dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3632         dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3633         dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3634         dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3635
3636         dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3637         dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3638
3639         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3640         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3641                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3642         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3643         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3644                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3645         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3646         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3647                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3648         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3649         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3650                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3651
3652         dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3653         dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3654         dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3655         dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3656
3657         dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3658         dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3659         dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3660         dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3661         dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3662         dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3663         dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3664         dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3665         dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3666         dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3667         dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3668
3669         dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3670         dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3671         dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3672         dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3673         dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3674         dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3675         dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3676         dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3677 }
3678
3679 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
3680                                    struct i2c_msg *msg, int num_msgs)
3681 {
3682         struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
3683         struct amdgpu_device *adev = smu_i2c->adev;
3684         struct smu_context *smu = adev->powerplay.pp_handle;
3685         struct smu_table_context *smu_table = &smu->smu_table;
3686         struct smu_table *table = &smu_table->driver_table;
3687         SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
3688         int i, j, r, c;
3689         u16 dir;
3690
3691         if (!adev->pm.dpm_enabled)
3692                 return -EBUSY;
3693
3694         req = kzalloc(sizeof(*req), GFP_KERNEL);
3695         if (!req)
3696                 return -ENOMEM;
3697
3698         req->I2CcontrollerPort = smu_i2c->port;
3699         req->I2CSpeed = I2C_SPEED_FAST_400K;
3700         req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
3701         dir = msg[0].flags & I2C_M_RD;
3702
3703         for (c = i = 0; i < num_msgs; i++) {
3704                 for (j = 0; j < msg[i].len; j++, c++) {
3705                         SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
3706
3707                         if (!(msg[i].flags & I2C_M_RD)) {
3708                                 /* write */
3709                                 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
3710                                 cmd->ReadWriteData = msg[i].buf[j];
3711                         }
3712
3713                         if ((dir ^ msg[i].flags) & I2C_M_RD) {
3714                                 /* The direction changes.
3715                                  */
3716                                 dir = msg[i].flags & I2C_M_RD;
3717                                 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
3718                         }
3719
3720                         req->NumCmds++;
3721
3722                         /*
3723                          * Insert STOP if we are at the last byte of either last
3724                          * message for the transaction or the client explicitly
3725                          * requires a STOP at this particular message.
3726                          */
3727                         if ((j == msg[i].len - 1) &&
3728                             ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3729                                 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
3730                                 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
3731                         }
3732                 }
3733         }
3734         mutex_lock(&adev->pm.mutex);
3735         r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
3736         mutex_unlock(&adev->pm.mutex);
3737         if (r)
3738                 goto fail;
3739
3740         for (c = i = 0; i < num_msgs; i++) {
3741                 if (!(msg[i].flags & I2C_M_RD)) {
3742                         c += msg[i].len;
3743                         continue;
3744                 }
3745                 for (j = 0; j < msg[i].len; j++, c++) {
3746                         SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
3747
3748                         msg[i].buf[j] = cmd->ReadWriteData;
3749                 }
3750         }
3751         r = num_msgs;
3752 fail:
3753         kfree(req);
3754         return r;
3755 }
3756
3757 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
3758 {
3759         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3760 }
3761
3762
3763 static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
3764         .master_xfer = sienna_cichlid_i2c_xfer,
3765         .functionality = sienna_cichlid_i2c_func,
3766 };
3767
3768 static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
3769         .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
3770         .max_read_len  = MAX_SW_I2C_COMMANDS,
3771         .max_write_len = MAX_SW_I2C_COMMANDS,
3772         .max_comb_1st_msg_len = 2,
3773         .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
3774 };
3775
3776 static int sienna_cichlid_i2c_control_init(struct smu_context *smu)
3777 {
3778         struct amdgpu_device *adev = smu->adev;
3779         int res, i;
3780
3781         for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3782                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3783                 struct i2c_adapter *control = &smu_i2c->adapter;
3784
3785                 smu_i2c->adev = adev;
3786                 smu_i2c->port = i;
3787                 mutex_init(&smu_i2c->mutex);
3788                 control->owner = THIS_MODULE;
3789                 control->class = I2C_CLASS_HWMON;
3790                 control->dev.parent = &adev->pdev->dev;
3791                 control->algo = &sienna_cichlid_i2c_algo;
3792                 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
3793                 control->quirks = &sienna_cichlid_i2c_control_quirks;
3794                 i2c_set_adapdata(control, smu_i2c);
3795
3796                 res = i2c_add_adapter(control);
3797                 if (res) {
3798                         DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3799                         goto Out_err;
3800                 }
3801         }
3802         /* assign the buses used for the FRU EEPROM and RAS EEPROM */
3803         /* XXX ideally this would be something in a vbios data table */
3804         adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
3805         adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
3806
3807         return 0;
3808 Out_err:
3809         for ( ; i >= 0; i--) {
3810                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3811                 struct i2c_adapter *control = &smu_i2c->adapter;
3812
3813                 i2c_del_adapter(control);
3814         }
3815         return res;
3816 }
3817
3818 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu)
3819 {
3820         struct amdgpu_device *adev = smu->adev;
3821         int i;
3822
3823         for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3824                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3825                 struct i2c_adapter *control = &smu_i2c->adapter;
3826
3827                 i2c_del_adapter(control);
3828         }
3829         adev->pm.ras_eeprom_i2c_bus = NULL;
3830         adev->pm.fru_eeprom_i2c_bus = NULL;
3831 }
3832
3833 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3834                                               void **table)
3835 {
3836         struct smu_table_context *smu_table = &smu->smu_table;
3837         struct gpu_metrics_v1_3 *gpu_metrics =
3838                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3839         SmuMetricsExternal_t metrics_external;
3840         SmuMetrics_t *metrics =
3841                 &(metrics_external.SmuMetrics);
3842         SmuMetrics_V2_t *metrics_v2 =
3843                 &(metrics_external.SmuMetrics_V2);
3844         SmuMetrics_V3_t *metrics_v3 =
3845                 &(metrics_external.SmuMetrics_V3);
3846         struct amdgpu_device *adev = smu->adev;
3847         bool use_metrics_v2 = false;
3848         bool use_metrics_v3 = false;
3849         uint16_t average_gfx_activity;
3850         int ret = 0;
3851
3852         switch (smu->adev->ip_versions[MP1_HWIP][0]) {
3853         case IP_VERSION(11, 0, 7):
3854                 if (smu->smc_fw_version >= 0x3A4900)
3855                         use_metrics_v3 = true;
3856                 else if (smu->smc_fw_version >= 0x3A4300)
3857                         use_metrics_v2 = true;
3858                 break;
3859         case IP_VERSION(11, 0, 11):
3860                 if (smu->smc_fw_version >= 0x412D00)
3861                         use_metrics_v2 = true;
3862                 break;
3863         case IP_VERSION(11, 0, 12):
3864                 if (smu->smc_fw_version >= 0x3B2300)
3865                         use_metrics_v2 = true;
3866                 break;
3867         case IP_VERSION(11, 0, 13):
3868                 if (smu->smc_fw_version >= 0x491100)
3869                         use_metrics_v2 = true;
3870                 break;
3871         default:
3872                 break;
3873         }
3874
3875         ret = smu_cmn_get_metrics_table(smu,
3876                                         &metrics_external,
3877                                         true);
3878         if (ret)
3879                 return ret;
3880
3881         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3882
3883         gpu_metrics->temperature_edge = use_metrics_v3 ? metrics_v3->TemperatureEdge :
3884                 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge;
3885         gpu_metrics->temperature_hotspot = use_metrics_v3 ? metrics_v3->TemperatureHotspot :
3886                 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot;
3887         gpu_metrics->temperature_mem = use_metrics_v3 ? metrics_v3->TemperatureMem :
3888                 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem;
3889         gpu_metrics->temperature_vrgfx = use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
3890                 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx;
3891         gpu_metrics->temperature_vrsoc = use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
3892                 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc;
3893         gpu_metrics->temperature_vrmem = use_metrics_v3 ? metrics_v3->TemperatureVrMem0 :
3894                 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0;
3895
3896         gpu_metrics->average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
3897                 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3898         gpu_metrics->average_umc_activity = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
3899                 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity;
3900         gpu_metrics->average_mm_activity = use_metrics_v3 ?
3901                 (metrics_v3->VcnUsagePercentage0 + metrics_v3->VcnUsagePercentage1) / 2 :
3902                 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage;
3903
3904         gpu_metrics->average_socket_power = use_metrics_v3 ? metrics_v3->AverageSocketPower :
3905                 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower;
3906         gpu_metrics->energy_accumulator = use_metrics_v3 ? metrics_v3->EnergyAccumulator :
3907                 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator;
3908
3909         if (metrics->CurrGfxVoltageOffset)
3910                 gpu_metrics->voltage_gfx =
3911                         (155000 - 625 * metrics->CurrGfxVoltageOffset) / 100;
3912         if (metrics->CurrMemVidOffset)
3913                 gpu_metrics->voltage_mem =
3914                         (155000 - 625 * metrics->CurrMemVidOffset) / 100;
3915         if (metrics->CurrSocVoltageOffset)
3916                 gpu_metrics->voltage_soc =
3917                         (155000 - 625 * metrics->CurrSocVoltageOffset) / 100;
3918
3919         average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
3920                 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3921         if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
3922                 gpu_metrics->average_gfxclk_frequency =
3923                         use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
3924                         use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
3925                         metrics->AverageGfxclkFrequencyPostDs;
3926         else
3927                 gpu_metrics->average_gfxclk_frequency =
3928                         use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
3929                         use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
3930                         metrics->AverageGfxclkFrequencyPreDs;
3931
3932         gpu_metrics->average_uclk_frequency =
3933                 use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
3934                 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
3935                 metrics->AverageUclkFrequencyPostDs;
3936         gpu_metrics->average_vclk0_frequency = use_metrics_v3 ? metrics_v3->AverageVclk0Frequency :
3937                 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency;
3938         gpu_metrics->average_dclk0_frequency = use_metrics_v3 ? metrics_v3->AverageDclk0Frequency :
3939                 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency;
3940         gpu_metrics->average_vclk1_frequency = use_metrics_v3 ? metrics_v3->AverageVclk1Frequency :
3941                 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency;
3942         gpu_metrics->average_dclk1_frequency = use_metrics_v3 ? metrics_v3->AverageDclk1Frequency :
3943                 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency;
3944
3945         gpu_metrics->current_gfxclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
3946                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK];
3947         gpu_metrics->current_socclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
3948                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK];
3949         gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
3950                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];
3951         gpu_metrics->current_vclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
3952                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0];
3953         gpu_metrics->current_dclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
3954                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0];
3955         gpu_metrics->current_vclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
3956                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1];
3957         gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
3958                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1];
3959
3960         gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu);
3961         gpu_metrics->indep_throttle_status =
3962                         smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
3963                                                            sienna_cichlid_throttler_map);
3964
3965         gpu_metrics->current_fan_speed = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
3966                 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
3967
3968         if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
3969               ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
3970                 gpu_metrics->pcie_link_width = use_metrics_v3 ? metrics_v3->PcieWidth :
3971                         use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
3972                 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v3 ? metrics_v3->PcieRate :
3973                         use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
3974         } else {
3975                 gpu_metrics->pcie_link_width =
3976                                 smu_v11_0_get_current_pcie_link_width(smu);
3977                 gpu_metrics->pcie_link_speed =
3978                                 smu_v11_0_get_current_pcie_link_speed(smu);
3979         }
3980
3981         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3982
3983         *table = (void *)gpu_metrics;
3984
3985         return sizeof(struct gpu_metrics_v1_3);
3986 }
3987
3988 static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu)
3989 {
3990         uint32_t if_version = 0xff, smu_version = 0xff;
3991         int ret = 0;
3992
3993         ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
3994         if (ret)
3995                 return -EOPNOTSUPP;
3996
3997         if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION)
3998                 ret = -EOPNOTSUPP;
3999
4000         return ret;
4001 }
4002
4003 static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu,
4004                                         void *table)
4005 {
4006         struct smu_table_context *smu_table = &smu->smu_table;
4007         EccInfoTable_t *ecc_table = NULL;
4008         struct ecc_info_per_ch *ecc_info_per_channel = NULL;
4009         int i, ret = 0;
4010         struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
4011
4012         ret = sienna_cichlid_check_ecc_table_support(smu);
4013         if (ret)
4014                 return ret;
4015
4016         ret = smu_cmn_update_table(smu,
4017                                 SMU_TABLE_ECCINFO,
4018                                 0,
4019                                 smu_table->ecc_table,
4020                                 false);
4021         if (ret) {
4022                 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
4023                 return ret;
4024         }
4025
4026         ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
4027
4028         for (i = 0; i < SIENNA_CICHLID_UMC_CHANNEL_NUM; i++) {
4029                 ecc_info_per_channel = &(eccinfo->ecc[i]);
4030                 ecc_info_per_channel->ce_count_lo_chip =
4031                         ecc_table->EccInfo[i].ce_count_lo_chip;
4032                 ecc_info_per_channel->ce_count_hi_chip =
4033                         ecc_table->EccInfo[i].ce_count_hi_chip;
4034                 ecc_info_per_channel->mca_umc_status =
4035                         ecc_table->EccInfo[i].mca_umc_status;
4036                 ecc_info_per_channel->mca_umc_addr =
4037                         ecc_table->EccInfo[i].mca_umc_addr;
4038         }
4039
4040         return ret;
4041 }
4042 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
4043 {
4044         uint16_t *mgpu_fan_boost_limit_rpm;
4045
4046         GET_PPTABLE_MEMBER(MGpuFanBoostLimitRpm, &mgpu_fan_boost_limit_rpm);
4047         /*
4048          * Skip the MGpuFanBoost setting for those ASICs
4049          * which do not support it
4050          */
4051         if (*mgpu_fan_boost_limit_rpm == 0)
4052                 return 0;
4053
4054         return smu_cmn_send_smc_msg_with_param(smu,
4055                                                SMU_MSG_SetMGpuFanBoostLimitRpm,
4056                                                0,
4057                                                NULL);
4058 }
4059
4060 static int sienna_cichlid_gpo_control(struct smu_context *smu,
4061                                       bool enablement)
4062 {
4063         uint32_t smu_version;
4064         int ret = 0;
4065
4066
4067         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
4068                 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
4069                 if (ret)
4070                         return ret;
4071
4072                 if (enablement) {
4073                         if (smu_version < 0x003a2500) {
4074                                 ret = smu_cmn_send_smc_msg_with_param(smu,
4075                                                                       SMU_MSG_SetGpoFeaturePMask,
4076                                                                       GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
4077                                                                       NULL);
4078                         } else {
4079                                 ret = smu_cmn_send_smc_msg_with_param(smu,
4080                                                                       SMU_MSG_DisallowGpo,
4081                                                                       0,
4082                                                                       NULL);
4083                         }
4084                 } else {
4085                         if (smu_version < 0x003a2500) {
4086                                 ret = smu_cmn_send_smc_msg_with_param(smu,
4087                                                                       SMU_MSG_SetGpoFeaturePMask,
4088                                                                       0,
4089                                                                       NULL);
4090                         } else {
4091                                 ret = smu_cmn_send_smc_msg_with_param(smu,
4092                                                                       SMU_MSG_DisallowGpo,
4093                                                                       1,
4094                                                                       NULL);
4095                         }
4096                 }
4097         }
4098
4099         return ret;
4100 }
4101
4102 static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
4103 {
4104         uint32_t smu_version;
4105         int ret = 0;
4106
4107         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
4108         if (ret)
4109                 return ret;
4110
4111         /*
4112          * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
4113          * onwards PMFWs.
4114          */
4115         if (smu_version < 0x003A2D00)
4116                 return 0;
4117
4118         return smu_cmn_send_smc_msg_with_param(smu,
4119                                                SMU_MSG_Enable2ndUSB20Port,
4120                                                smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
4121                                                1 : 0,
4122                                                NULL);
4123 }
4124
4125 static int sienna_cichlid_system_features_control(struct smu_context *smu,
4126                                                   bool en)
4127 {
4128         int ret = 0;
4129
4130         if (en) {
4131                 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
4132                 if (ret)
4133                         return ret;
4134         }
4135
4136         return smu_v11_0_system_features_control(smu, en);
4137 }
4138
4139 static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
4140                                         enum pp_mp1_state mp1_state)
4141 {
4142         int ret;
4143
4144         switch (mp1_state) {
4145         case PP_MP1_STATE_UNLOAD:
4146                 ret = smu_cmn_set_mp1_state(smu, mp1_state);
4147                 break;
4148         default:
4149                 /* Ignore others */
4150                 ret = 0;
4151         }
4152
4153         return ret;
4154 }
4155
4156 static void sienna_cichlid_stb_init(struct smu_context *smu)
4157 {
4158         struct amdgpu_device *adev = smu->adev;
4159         uint32_t reg;
4160
4161         reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START);
4162         smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE);
4163
4164         /* STB is disabled */
4165         if (!smu->stb_context.enabled)
4166                 return;
4167
4168         spin_lock_init(&smu->stb_context.lock);
4169
4170         /* STB buffer size in bytes as function of FIFO depth */
4171         reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO);
4172         smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH);
4173         smu->stb_context.stb_buf_size *=  SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES;
4174
4175         dev_info(smu->adev->dev, "STB initialized to %d entries",
4176                  smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES);
4177
4178 }
4179
4180 static int sienna_cichlid_get_default_config_table_settings(struct smu_context *smu,
4181                                                             struct config_table_setting *table)
4182 {
4183         struct amdgpu_device *adev = smu->adev;
4184
4185         if (!table)
4186                 return -EINVAL;
4187
4188         table->gfxclk_average_tau = 10;
4189         table->socclk_average_tau = 10;
4190         table->fclk_average_tau = 10;
4191         table->uclk_average_tau = 10;
4192         table->gfx_activity_average_tau = 10;
4193         table->mem_activity_average_tau = 10;
4194         table->socket_power_average_tau = 100;
4195         if (adev->asic_type != CHIP_SIENNA_CICHLID)
4196                 table->apu_socket_power_average_tau = 100;
4197
4198         return 0;
4199 }
4200
4201 static int sienna_cichlid_set_config_table(struct smu_context *smu,
4202                                            struct config_table_setting *table)
4203 {
4204         DriverSmuConfigExternal_t driver_smu_config_table;
4205
4206         if (!table)
4207                 return -EINVAL;
4208
4209         memset(&driver_smu_config_table,
4210                0,
4211                sizeof(driver_smu_config_table));
4212         driver_smu_config_table.DriverSmuConfig.GfxclkAverageLpfTau =
4213                                 table->gfxclk_average_tau;
4214         driver_smu_config_table.DriverSmuConfig.FclkAverageLpfTau =
4215                                 table->fclk_average_tau;
4216         driver_smu_config_table.DriverSmuConfig.UclkAverageLpfTau =
4217                                 table->uclk_average_tau;
4218         driver_smu_config_table.DriverSmuConfig.GfxActivityLpfTau =
4219                                 table->gfx_activity_average_tau;
4220         driver_smu_config_table.DriverSmuConfig.UclkActivityLpfTau =
4221                                 table->mem_activity_average_tau;
4222         driver_smu_config_table.DriverSmuConfig.SocketPowerLpfTau =
4223                                 table->socket_power_average_tau;
4224
4225         return smu_cmn_update_table(smu,
4226                                     SMU_TABLE_DRIVER_SMU_CONFIG,
4227                                     0,
4228                                     (void *)&driver_smu_config_table,
4229                                     true);
4230 }
4231
4232 static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu,
4233                                               void *buf,
4234                                               uint32_t size)
4235 {
4236         uint32_t *p = buf;
4237         struct amdgpu_device *adev = smu->adev;
4238
4239         /* No need to disable interrupts for now as we don't lock it yet from ISR */
4240         spin_lock(&smu->stb_context.lock);
4241
4242         /*
4243          * Read the STB FIFO in units of 32bit since this is the accessor window
4244          * (register width) we have.
4245          */
4246         buf = ((char *) buf) + size;
4247         while ((void *)p < buf)
4248                 *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3));
4249
4250         spin_unlock(&smu->stb_context.lock);
4251
4252         return 0;
4253 }
4254
4255 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
4256         .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
4257         .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
4258         .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
4259         .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
4260         .i2c_init = sienna_cichlid_i2c_control_init,
4261         .i2c_fini = sienna_cichlid_i2c_control_fini,
4262         .print_clk_levels = sienna_cichlid_print_clk_levels,
4263         .force_clk_levels = sienna_cichlid_force_clk_levels,
4264         .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
4265         .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
4266         .display_config_changed = sienna_cichlid_display_config_changed,
4267         .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
4268         .is_dpm_running = sienna_cichlid_is_dpm_running,
4269         .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
4270         .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
4271         .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
4272         .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
4273         .set_watermarks_table = sienna_cichlid_set_watermarks_table,
4274         .read_sensor = sienna_cichlid_read_sensor,
4275         .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
4276         .set_performance_level = smu_v11_0_set_performance_level,
4277         .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
4278         .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
4279         .get_power_limit = sienna_cichlid_get_power_limit,
4280         .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
4281         .dump_pptable = sienna_cichlid_dump_pptable,
4282         .init_microcode = smu_v11_0_init_microcode,
4283         .load_microcode = smu_v11_0_load_microcode,
4284         .fini_microcode = smu_v11_0_fini_microcode,
4285         .init_smc_tables = sienna_cichlid_init_smc_tables,
4286         .fini_smc_tables = smu_v11_0_fini_smc_tables,
4287         .init_power = smu_v11_0_init_power,
4288         .fini_power = smu_v11_0_fini_power,
4289         .check_fw_status = smu_v11_0_check_fw_status,
4290         .setup_pptable = sienna_cichlid_setup_pptable,
4291         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
4292         .check_fw_version = smu_v11_0_check_fw_version,
4293         .write_pptable = smu_cmn_write_pptable,
4294         .set_driver_table_location = smu_v11_0_set_driver_table_location,
4295         .set_tool_table_location = smu_v11_0_set_tool_table_location,
4296         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
4297         .system_features_control = sienna_cichlid_system_features_control,
4298         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
4299         .send_smc_msg = smu_cmn_send_smc_msg,
4300         .init_display_count = NULL,
4301         .set_allowed_mask = smu_v11_0_set_allowed_mask,
4302         .get_enabled_mask = smu_cmn_get_enabled_mask,
4303         .feature_is_enabled = smu_cmn_feature_is_enabled,
4304         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
4305         .notify_display_change = NULL,
4306         .set_power_limit = smu_v11_0_set_power_limit,
4307         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
4308         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
4309         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
4310         .set_min_dcef_deep_sleep = NULL,
4311         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
4312         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
4313         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
4314         .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
4315         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
4316         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
4317         .gfx_off_control = smu_v11_0_gfx_off_control,
4318         .register_irq_handler = smu_v11_0_register_irq_handler,
4319         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
4320         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
4321         .baco_is_support = smu_v11_0_baco_is_support,
4322         .baco_get_state = smu_v11_0_baco_get_state,
4323         .baco_set_state = smu_v11_0_baco_set_state,
4324         .baco_enter = sienna_cichlid_baco_enter,
4325         .baco_exit = sienna_cichlid_baco_exit,
4326         .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
4327         .mode1_reset = smu_v11_0_mode1_reset,
4328         .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
4329         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
4330         .set_default_od_settings = sienna_cichlid_set_default_od_settings,
4331         .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
4332         .restore_user_od_settings = smu_v11_0_restore_user_od_settings,
4333         .run_btc = sienna_cichlid_run_btc,
4334         .set_power_source = smu_v11_0_set_power_source,
4335         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
4336         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
4337         .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
4338         .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
4339         .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
4340         .deep_sleep_control = smu_v11_0_deep_sleep_control,
4341         .get_fan_parameters = sienna_cichlid_get_fan_parameters,
4342         .interrupt_work = smu_v11_0_interrupt_work,
4343         .gpo_control = sienna_cichlid_gpo_control,
4344         .set_mp1_state = sienna_cichlid_set_mp1_state,
4345         .stb_collect_info = sienna_cichlid_stb_get_data_direct,
4346         .get_ecc_info = sienna_cichlid_get_ecc_info,
4347         .get_default_config_table_settings = sienna_cichlid_get_default_config_table_settings,
4348         .set_config_table = sienna_cichlid_set_config_table,
4349         .get_unique_id = sienna_cichlid_get_unique_id,
4350 };
4351
4352 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
4353 {
4354         smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
4355         smu->message_map = sienna_cichlid_message_map;
4356         smu->clock_map = sienna_cichlid_clk_map;
4357         smu->feature_map = sienna_cichlid_feature_mask_map;
4358         smu->table_map = sienna_cichlid_table_map;
4359         smu->pwr_src_map = sienna_cichlid_pwr_src_map;
4360         smu->workload_map = sienna_cichlid_workload_map;
4361 }