git.itanic.dy.fi Git - linux-stable/blob - drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include <linux/pci.h>
  28 #include <linux/i2c.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_dpm.h"
  31 #include "amdgpu_smu.h"
  32 #include "atomfirmware.h"
  33 #include "amdgpu_atomfirmware.h"
  34 #include "amdgpu_atombios.h"
  35 #include "smu_v11_0.h"
  36 #include "smu11_driver_if_sienna_cichlid.h"
  37 #include "soc15_common.h"
  38 #include "atom.h"
  39 #include "sienna_cichlid_ppt.h"
  40 #include "smu_v11_0_7_pptable.h"
  41 #include "smu_v11_0_7_ppsmc.h"
  42 #include "nbio/nbio_2_3_offset.h"
  43 #include "nbio/nbio_2_3_sh_mask.h"
  44 #include "thm/thm_11_0_2_offset.h"
  45 #include "thm/thm_11_0_2_sh_mask.h"
  46 #include "mp/mp_11_0_offset.h"
  47 #include "mp/mp_11_0_sh_mask.h"
  48
  49 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  50 #include "amdgpu_ras.h"
  51 #include "smu_cmn.h"
  52
  53 /*
  54  * DO NOT use these for err/warn/info/debug messages.
  55  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  56  * They are more MGPU friendly.
  57  */
  58 #undef pr_err
  59 #undef pr_warn
  60 #undef pr_info
  61 #undef pr_debug
  62
  63 #define FEATURE_MASK(feature) (1ULL << feature)
  64 #define SMC_DPM_FEATURE ( \
  65         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  66         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  67         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  68         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  69         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  70         FEATURE_MASK(FEATURE_DPM_FCLK_BIT)       | \
  71         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)    | \
  72         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
  73
  74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
  75
  76 #define GET_PPTABLE_MEMBER(field, member) do {\
  77         if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\
  78                 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
  79         else\
  80                 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
  81 } while(0)
  82
  83 /* STB FIFO depth is in 64bit units */
  84 #define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8
  85
  86 /*
  87  * SMU support ECCTABLE since version 58.70.0,
  88  * use this to check whether ECCTABLE feature is supported.
  89  */
  90 #define SUPPORT_ECCTABLE_SMU_VERSION 0x003a4600
  91
  92 static int get_table_size(struct smu_context *smu)
  93 {
  94         if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
  95                 return sizeof(PPTable_beige_goby_t);
  96         else
  97                 return sizeof(PPTable_t);
  98 }
  99
 100 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
 101         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                 1),
 102         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,               1),
 103         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,          1),
 104         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow,   0),
 105         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh,  0),
 106         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures,        0),
 107         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures,       0),
 108         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow,        1),
 109         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh,       1),
 110         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow,       1),
 111         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh,      1),
 112         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetRunningSmuFeaturesLow,    1),
 113         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetRunningSmuFeaturesHigh,   1),
 114         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,             1),
 115         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                 0),
 116         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,       1),
 117         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,        1),
 118         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,        0),
 119         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,         0),
 120         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,       1),
 121         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,       0),
 122         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,           0),
 123         MSG_MAP(RunDcBtc,                       PPSMC_MSG_RunDcBtc,                    0),
 124         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                   0),
 125         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,            1),
 126         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,            1),
 127         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,            1),
 128         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,            0),
 129         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,               1),
 130         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq,               1),
 131         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex,           1),
 132         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode,               0),
 133         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh,       0),
 134         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow,        0),
 135         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters,      0),
 136         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt,       0),
 137         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource,           0),
 138         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch,           0),
 139         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps,                 0),
 140         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,         1),
 141         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                 0),
 142         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,              0),
 143         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit,                 0),
 144         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq,         1),
 145         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco,                    0),
 146         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                  0),
 147         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                0),
 148         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                 0),
 149         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,               0),
 150         MSG_MAP(BacoAudioD3PME,                 PPSMC_MSG_BacoAudioD3PME,              0),
 151         MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3,                       0),
 152         MSG_MAP(Mode1Reset,                     PPSMC_MSG_Mode1Reset,                  0),
 153         MSG_MAP(SetMGpuFanBoostLimitRpm,        PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),
 154         MSG_MAP(SetGpoFeaturePMask,             PPSMC_MSG_SetGpoFeaturePMask,          0),
 155         MSG_MAP(DisallowGpo,                    PPSMC_MSG_DisallowGpo,                 0),
 156         MSG_MAP(Enable2ndUSB20Port,             PPSMC_MSG_Enable2ndUSB20Port,          0),
 157 };
 158
 159 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
 160         CLK_MAP(GFXCLK,         PPCLK_GFXCLK),
 161         CLK_MAP(SCLK,           PPCLK_GFXCLK),
 162         CLK_MAP(SOCCLK,         PPCLK_SOCCLK),
 163         CLK_MAP(FCLK,           PPCLK_FCLK),
 164         CLK_MAP(UCLK,           PPCLK_UCLK),
 165         CLK_MAP(MCLK,           PPCLK_UCLK),
 166         CLK_MAP(DCLK,           PPCLK_DCLK_0),
 167         CLK_MAP(DCLK1,          PPCLK_DCLK_1),
 168         CLK_MAP(VCLK,           PPCLK_VCLK_0),
 169         CLK_MAP(VCLK1,          PPCLK_VCLK_1),
 170         CLK_MAP(DCEFCLK,        PPCLK_DCEFCLK),
 171         CLK_MAP(DISPCLK,        PPCLK_DISPCLK),
 172         CLK_MAP(PIXCLK,         PPCLK_PIXCLK),
 173         CLK_MAP(PHYCLK,         PPCLK_PHYCLK),
 174 };
 175
 176 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
 177         FEA_MAP(DPM_PREFETCHER),
 178         FEA_MAP(DPM_GFXCLK),
 179         FEA_MAP(DPM_GFX_GPO),
 180         FEA_MAP(DPM_UCLK),
 181         FEA_MAP(DPM_FCLK),
 182         FEA_MAP(DPM_SOCCLK),
 183         FEA_MAP(DPM_MP0CLK),
 184         FEA_MAP(DPM_LINK),
 185         FEA_MAP(DPM_DCEFCLK),
 186         FEA_MAP(DPM_XGMI),
 187         FEA_MAP(MEM_VDDCI_SCALING),
 188         FEA_MAP(MEM_MVDD_SCALING),
 189         FEA_MAP(DS_GFXCLK),
 190         FEA_MAP(DS_SOCCLK),
 191         FEA_MAP(DS_FCLK),
 192         FEA_MAP(DS_LCLK),
 193         FEA_MAP(DS_DCEFCLK),
 194         FEA_MAP(DS_UCLK),
 195         FEA_MAP(GFX_ULV),
 196         FEA_MAP(FW_DSTATE),
 197         FEA_MAP(GFXOFF),
 198         FEA_MAP(BACO),
 199         FEA_MAP(MM_DPM_PG),
 200         FEA_MAP(RSMU_SMN_CG),
 201         FEA_MAP(PPT),
 202         FEA_MAP(TDC),
 203         FEA_MAP(APCC_PLUS),
 204         FEA_MAP(GTHR),
 205         FEA_MAP(ACDC),
 206         FEA_MAP(VR0HOT),
 207         FEA_MAP(VR1HOT),
 208         FEA_MAP(FW_CTF),
 209         FEA_MAP(FAN_CONTROL),
 210         FEA_MAP(THERMAL),
 211         FEA_MAP(GFX_DCS),
 212         FEA_MAP(RM),
 213         FEA_MAP(LED_DISPLAY),
 214         FEA_MAP(GFX_SS),
 215         FEA_MAP(OUT_OF_BAND_MONITOR),
 216         FEA_MAP(TEMP_DEPENDENT_VMIN),
 217         FEA_MAP(MMHUB_PG),
 218         FEA_MAP(ATHUB_PG),
 219         FEA_MAP(APCC_DFLL),
 220 };
 221
 222 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
 223         TAB_MAP(PPTABLE),
 224         TAB_MAP(WATERMARKS),
 225         TAB_MAP(AVFS_PSM_DEBUG),
 226         TAB_MAP(AVFS_FUSE_OVERRIDE),
 227         TAB_MAP(PMSTATUSLOG),
 228         TAB_MAP(SMU_METRICS),
 229         TAB_MAP(DRIVER_SMU_CONFIG),
 230         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 231         TAB_MAP(OVERDRIVE),
 232         TAB_MAP(I2C_COMMANDS),
 233         TAB_MAP(PACE),
 234         TAB_MAP(ECCINFO),
 235 };
 236
 237 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 238         PWR_MAP(AC),
 239         PWR_MAP(DC),
 240 };
 241
 242 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 243         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 244         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 245         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 246         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 247         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 248         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 249         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 250 };
 251
 252 static const uint8_t sienna_cichlid_throttler_map[] = {
 253         [THROTTLER_TEMP_EDGE_BIT]       = (SMU_THROTTLER_TEMP_EDGE_BIT),
 254         [THROTTLER_TEMP_HOTSPOT_BIT]    = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
 255         [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 256         [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 257         [THROTTLER_TEMP_VR_MEM0_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 258         [THROTTLER_TEMP_VR_MEM1_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
 259         [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 260         [THROTTLER_TEMP_LIQUID0_BIT]    = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
 261         [THROTTLER_TEMP_LIQUID1_BIT]    = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
 262         [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 263         [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 264         [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 265         [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 266         [THROTTLER_PPT2_BIT]            = (SMU_THROTTLER_PPT2_BIT),
 267         [THROTTLER_PPT3_BIT]            = (SMU_THROTTLER_PPT3_BIT),
 268         [THROTTLER_FIT_BIT]             = (SMU_THROTTLER_FIT_BIT),
 269         [THROTTLER_PPM_BIT]             = (SMU_THROTTLER_PPM_BIT),
 270         [THROTTLER_APCC_BIT]            = (SMU_THROTTLER_APCC_BIT),
 271 };
 272
 273 static int
 274 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 275                                   uint32_t *feature_mask, uint32_t num)
 276 {
 277         struct amdgpu_device *adev = smu->adev;
 278
 279         if (num > 2)
 280                 return -EINVAL;
 281
 282         memset(feature_mask, 0, sizeof(uint32_t) * num);
 283
 284         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 285                                 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
 286                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 287                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 288                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 289                                 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
 290                                 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
 291                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 292                                 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
 293                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 294                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 295                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 296                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 297                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 298                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 299                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 300                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 301                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 302                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 303                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 304
 305         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
 306                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 307                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
 308         }
 309
 310         if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
 311             (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) &&
 312             !(adev->flags & AMD_IS_APU))
 313                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
 314
 315         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 316                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 317                                         | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 318                                         | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 319
 320         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 321                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 322
 323         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 324                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 325
 326         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 327                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 328
 329         if (adev->pm.pp_feature & PP_ULV_MASK)
 330                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 331
 332         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 333                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 334
 335         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 336                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 337
 338         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 339                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 340
 341         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 342                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 343
 344         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
 345             smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 346                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
 347
 348         if (smu->dc_controlled_by_gpio)
 349        *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
 350
 351         if (amdgpu_device_should_use_aspm(adev))
 352                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
 353
 354         return 0;
 355 }
 356
 357 static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
 358 {
 359         struct smu_table_context *table_context = &smu->smu_table;
 360         struct smu_11_0_7_powerplay_table *powerplay_table =
 361                 table_context->power_play_table;
 362         struct smu_baco_context *smu_baco = &smu->smu_baco;
 363         struct amdgpu_device *adev = smu->adev;
 364         uint32_t val;
 365
 366         if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) {
 367                 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
 368                 smu_baco->platform_support =
 369                         (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
 370                                                                         false;
 371
 372                 /*
 373                  * Disable BACO entry/exit completely on below SKUs to
 374                  * avoid hardware intermittent failures.
 375                  */
 376                 if (((adev->pdev->device == 0x73A1) &&
 377                     (adev->pdev->revision == 0x00)) ||
 378                     ((adev->pdev->device == 0x73BF) &&
 379                     (adev->pdev->revision == 0xCF)))
 380                         smu_baco->platform_support = false;
 381
 382         }
 383 }
 384
 385 static void sienna_cichlid_check_fan_support(struct smu_context *smu)
 386 {
 387         struct smu_table_context *table_context = &smu->smu_table;
 388         PPTable_t *pptable = table_context->driver_pptable;
 389         uint64_t features = *(uint64_t *) pptable->FeaturesToRun;
 390
 391         /* Fan control is not possible if PPTable has it disabled */
 392         smu->adev->pm.no_fan =
 393                 !(features & (1ULL << FEATURE_FAN_CONTROL_BIT));
 394         if (smu->adev->pm.no_fan)
 395                 dev_info_once(smu->adev->dev,
 396                               "PMFW based fan control disabled");
 397 }
 398
 399 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
 400 {
 401         struct smu_table_context *table_context = &smu->smu_table;
 402         struct smu_11_0_7_powerplay_table *powerplay_table =
 403                 table_context->power_play_table;
 404
 405         if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
 406                 smu->dc_controlled_by_gpio = true;
 407
 408         sienna_cichlid_check_bxco_support(smu);
 409         sienna_cichlid_check_fan_support(smu);
 410
 411         table_context->thermal_controller_type =
 412                 powerplay_table->thermal_controller_type;
 413
 414         /*
 415          * Instead of having its own buffer space and get overdrive_table copied,
 416          * smu->od_settings just points to the actual overdrive_table
 417          */
 418         smu->od_settings = &powerplay_table->overdrive_table;
 419
 420         return 0;
 421 }
 422
 423 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
 424 {
 425         struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
 426         int index, ret;
 427         I2cControllerConfig_t *table_member;
 428
 429         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 430                                             smc_dpm_info);
 431
 432         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 433                                       (uint8_t **)&smc_dpm_table);
 434         if (ret)
 435                 return ret;
 436         GET_PPTABLE_MEMBER(I2cControllers, &table_member);
 437         memcpy(table_member, smc_dpm_table->I2cControllers,
 438                         sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
 439
 440         return 0;
 441 }
 442
 443 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
 444 {
 445         struct smu_table_context *table_context = &smu->smu_table;
 446         struct smu_11_0_7_powerplay_table *powerplay_table =
 447                 table_context->power_play_table;
 448         int table_size;
 449
 450         table_size = get_table_size(smu);
 451         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 452                table_size);
 453
 454         return 0;
 455 }
 456
 457 static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu)
 458 {
 459         struct amdgpu_device *adev = smu->adev;
 460         uint32_t *board_reserved;
 461         uint16_t *freq_table_gfx;
 462         uint32_t i;
 463
 464         /* Fix some OEM SKU specific stability issues */
 465         GET_PPTABLE_MEMBER(BoardReserved, &board_reserved);
 466         if ((adev->pdev->device == 0x73DF) &&
 467             (adev->pdev->revision == 0XC3) &&
 468             (adev->pdev->subsystem_device == 0x16C2) &&
 469             (adev->pdev->subsystem_vendor == 0x1043))
 470                 board_reserved[0] = 1387;
 471
 472         GET_PPTABLE_MEMBER(FreqTableGfx, &freq_table_gfx);
 473         if ((adev->pdev->device == 0x73DF) &&
 474             (adev->pdev->revision == 0XC3) &&
 475             ((adev->pdev->subsystem_device == 0x16C2) ||
 476             (adev->pdev->subsystem_device == 0x133C)) &&
 477             (adev->pdev->subsystem_vendor == 0x1043)) {
 478                 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) {
 479                         if (freq_table_gfx[i] > 2500)
 480                                 freq_table_gfx[i] = 2500;
 481                 }
 482         }
 483
 484         return 0;
 485 }
 486
 487 static int sienna_cichlid_setup_pptable(struct smu_context *smu)
 488 {
 489         int ret = 0;
 490
 491         ret = smu_v11_0_setup_pptable(smu);
 492         if (ret)
 493                 return ret;
 494
 495         ret = sienna_cichlid_store_powerplay_table(smu);
 496         if (ret)
 497                 return ret;
 498
 499         ret = sienna_cichlid_append_powerplay_table(smu);
 500         if (ret)
 501                 return ret;
 502
 503         ret = sienna_cichlid_check_powerplay_table(smu);
 504         if (ret)
 505                 return ret;
 506
 507         return sienna_cichlid_patch_pptable_quirk(smu);
 508 }
 509
 510 static int sienna_cichlid_tables_init(struct smu_context *smu)
 511 {
 512         struct smu_table_context *smu_table = &smu->smu_table;
 513         struct smu_table *tables = smu_table->tables;
 514         int table_size;
 515
 516         table_size = get_table_size(smu);
 517         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
 518                                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 519         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 520                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 521         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
 522                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 523         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 524                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 525         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 526                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 527         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 528                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 529         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 530                        sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
 531                        AMDGPU_GEM_DOMAIN_VRAM);
 532         SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
 533                         PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 534         SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfigExternal_t),
 535                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 536
 537         smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
 538         if (!smu_table->metrics_table)
 539                 goto err0_out;
 540         smu_table->metrics_time = 0;
 541
 542         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 543         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 544         if (!smu_table->gpu_metrics_table)
 545                 goto err1_out;
 546
 547         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 548         if (!smu_table->watermarks_table)
 549                 goto err2_out;
 550
 551         smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
 552         if (!smu_table->ecc_table)
 553                 goto err3_out;
 554
 555         smu_table->driver_smu_config_table =
 556                 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL);
 557         if (!smu_table->driver_smu_config_table)
 558                 goto err4_out;
 559
 560         return 0;
 561
 562 err4_out:
 563         kfree(smu_table->ecc_table);
 564 err3_out:
 565         kfree(smu_table->watermarks_table);
 566 err2_out:
 567         kfree(smu_table->gpu_metrics_table);
 568 err1_out:
 569         kfree(smu_table->metrics_table);
 570 err0_out:
 571         return -ENOMEM;
 572 }
 573
 574 static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu)
 575 {
 576         struct smu_table_context *smu_table= &smu->smu_table;
 577         SmuMetricsExternal_t *metrics_ext =
 578                 (SmuMetricsExternal_t *)(smu_table->metrics_table);
 579         uint32_t throttler_status = 0;
 580         int i;
 581
 582         if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
 583              (smu->smc_fw_version >= 0x3A4900)) {
 584                 for (i = 0; i < THROTTLER_COUNT; i++)
 585                         throttler_status |=
 586                                 (metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0);
 587         } else if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
 588              (smu->smc_fw_version >= 0x3A4300)) {
 589                 for (i = 0; i < THROTTLER_COUNT; i++)
 590                         throttler_status |=
 591                                 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
 592         } else {
 593                 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus;
 594         }
 595
 596         return throttler_status;
 597 }
 598
 599 static int sienna_cichlid_get_power_limit(struct smu_context *smu,
 600                                           uint32_t *current_power_limit,
 601                                           uint32_t *default_power_limit,
 602                                           uint32_t *max_power_limit)
 603 {
 604         struct smu_11_0_7_powerplay_table *powerplay_table =
 605                 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
 606         uint32_t power_limit, od_percent;
 607         uint16_t *table_member;
 608
 609         GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
 610
 611         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
 612                 power_limit =
 613                         table_member[PPT_THROTTLER_PPT0];
 614         }
 615
 616         if (current_power_limit)
 617                 *current_power_limit = power_limit;
 618         if (default_power_limit)
 619                 *default_power_limit = power_limit;
 620
 621         if (max_power_limit) {
 622                 if (smu->od_enabled) {
 623                         od_percent =
 624                                 le32_to_cpu(powerplay_table->overdrive_table.max[
 625                                                         SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
 626
 627                         dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n",
 628                                         od_percent, power_limit);
 629
 630                         power_limit *= (100 + od_percent);
 631                         power_limit /= 100;
 632                 }
 633                 *max_power_limit = power_limit;
 634         }
 635
 636         return 0;
 637 }
 638
 639 static void sienna_cichlid_get_smartshift_power_percentage(struct smu_context *smu,
 640                                         uint32_t *apu_percent,
 641                                         uint32_t *dgpu_percent)
 642 {
 643         struct smu_table_context *smu_table = &smu->smu_table;
 644         SmuMetrics_V4_t *metrics_v4 =
 645                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V4);
 646         uint16_t powerRatio = 0;
 647         uint16_t apu_power_limit = 0;
 648         uint16_t dgpu_power_limit = 0;
 649         uint32_t apu_boost = 0;
 650         uint32_t dgpu_boost = 0;
 651         uint32_t cur_power_limit;
 652
 653         if (metrics_v4->ApuSTAPMSmartShiftLimit != 0) {
 654                 sienna_cichlid_get_power_limit(smu, &cur_power_limit, NULL, NULL);
 655                 apu_power_limit = metrics_v4->ApuSTAPMLimit;
 656                 dgpu_power_limit = cur_power_limit;
 657                 powerRatio = (((apu_power_limit +
 658                                                   dgpu_power_limit) * 100) /
 659                                                   metrics_v4->ApuSTAPMSmartShiftLimit);
 660                 if (powerRatio > 100) {
 661                         apu_power_limit = (apu_power_limit * 100) /
 662                                                                          powerRatio;
 663                         dgpu_power_limit = (dgpu_power_limit * 100) /
 664                                                                           powerRatio;
 665                 }
 666                 if (metrics_v4->AverageApuSocketPower > apu_power_limit &&
 667                          apu_power_limit != 0) {
 668                         apu_boost = ((metrics_v4->AverageApuSocketPower -
 669                                                         apu_power_limit) * 100) /
 670                                                         apu_power_limit;
 671                         if (apu_boost > 100)
 672                                 apu_boost = 100;
 673                 }
 674
 675                 if (metrics_v4->AverageSocketPower > dgpu_power_limit &&
 676                          dgpu_power_limit != 0) {
 677                         dgpu_boost = ((metrics_v4->AverageSocketPower -
 678                                                          dgpu_power_limit) * 100) /
 679                                                          dgpu_power_limit;
 680                         if (dgpu_boost > 100)
 681                                 dgpu_boost = 100;
 682                 }
 683
 684                 if (dgpu_boost >= apu_boost)
 685                         apu_boost = 0;
 686                 else
 687                         dgpu_boost = 0;
 688         }
 689         *apu_percent = apu_boost;
 690         *dgpu_percent = dgpu_boost;
 691 }
 692
 693 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
 694                                                MetricsMember_t member,
 695                                                uint32_t *value)
 696 {
 697         struct smu_table_context *smu_table= &smu->smu_table;
 698         SmuMetrics_t *metrics =
 699                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
 700         SmuMetrics_V2_t *metrics_v2 =
 701                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
 702         SmuMetrics_V3_t *metrics_v3 =
 703                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V3);
 704         bool use_metrics_v2 = false;
 705         bool use_metrics_v3 = false;
 706         uint16_t average_gfx_activity;
 707         int ret = 0;
 708         uint32_t apu_percent = 0;
 709         uint32_t dgpu_percent = 0;
 710
 711         switch (smu->adev->ip_versions[MP1_HWIP][0]) {
 712         case IP_VERSION(11, 0, 7):
 713                 if (smu->smc_fw_version >= 0x3A4900)
 714                         use_metrics_v3 = true;
 715                 else if (smu->smc_fw_version >= 0x3A4300)
 716                         use_metrics_v2 = true;
 717                 break;
 718         case IP_VERSION(11, 0, 11):
 719                 if (smu->smc_fw_version >= 0x412D00)
 720                         use_metrics_v2 = true;
 721                 break;
 722         case IP_VERSION(11, 0, 12):
 723                 if (smu->smc_fw_version >= 0x3B2300)
 724                         use_metrics_v2 = true;
 725                 break;
 726         case IP_VERSION(11, 0, 13):
 727                 if (smu->smc_fw_version >= 0x491100)
 728                         use_metrics_v2 = true;
 729                 break;
 730         default:
 731                 break;
 732         }
 733
 734         ret = smu_cmn_get_metrics_table(smu,
 735                                         NULL,
 736                                         false);
 737         if (ret)
 738                 return ret;
 739
 740         switch (member) {
 741         case METRICS_CURR_GFXCLK:
 742                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
 743                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] :
 744                         metrics->CurrClock[PPCLK_GFXCLK];
 745                 break;
 746         case METRICS_CURR_SOCCLK:
 747                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
 748                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] :
 749                         metrics->CurrClock[PPCLK_SOCCLK];
 750                 break;
 751         case METRICS_CURR_UCLK:
 752                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
 753                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :
 754                         metrics->CurrClock[PPCLK_UCLK];
 755                 break;
 756         case METRICS_CURR_VCLK:
 757                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
 758                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] :
 759                         metrics->CurrClock[PPCLK_VCLK_0];
 760                 break;
 761         case METRICS_CURR_VCLK1:
 762                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
 763                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] :
 764                         metrics->CurrClock[PPCLK_VCLK_1];
 765                 break;
 766         case METRICS_CURR_DCLK:
 767                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
 768                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] :
 769                         metrics->CurrClock[PPCLK_DCLK_0];
 770                 break;
 771         case METRICS_CURR_DCLK1:
 772                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
 773                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
 774                         metrics->CurrClock[PPCLK_DCLK_1];
 775                 break;
 776         case METRICS_CURR_DCEFCLK:
 777                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCEFCLK] :
 778                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] :
 779                         metrics->CurrClock[PPCLK_DCEFCLK];
 780                 break;
 781         case METRICS_CURR_FCLK:
 782                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_FCLK] :
 783                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] :
 784                         metrics->CurrClock[PPCLK_FCLK];
 785                 break;
 786         case METRICS_AVERAGE_GFXCLK:
 787                 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
 788                         use_metrics_v2 ? metrics_v2->AverageGfxActivity :
 789                         metrics->AverageGfxActivity;
 790                 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
 791                         *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
 792                                 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
 793                                 metrics->AverageGfxclkFrequencyPostDs;
 794                 else
 795                         *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
 796                                 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
 797                                 metrics->AverageGfxclkFrequencyPreDs;
 798                 break;
 799         case METRICS_AVERAGE_FCLK:
 800                 *value = use_metrics_v3 ? metrics_v3->AverageFclkFrequencyPostDs :
 801                         use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs :
 802                         metrics->AverageFclkFrequencyPostDs;
 803                 break;
 804         case METRICS_AVERAGE_UCLK:
 805                 *value = use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
 806                         use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
 807                         metrics->AverageUclkFrequencyPostDs;
 808                 break;
 809         case METRICS_AVERAGE_GFXACTIVITY:
 810                 *value = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
 811                         use_metrics_v2 ? metrics_v2->AverageGfxActivity :
 812                         metrics->AverageGfxActivity;
 813                 break;
 814         case METRICS_AVERAGE_MEMACTIVITY:
 815                 *value = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
 816                         use_metrics_v2 ? metrics_v2->AverageUclkActivity :
 817                         metrics->AverageUclkActivity;
 818                 break;
 819         case METRICS_AVERAGE_SOCKETPOWER:
 820                 *value = use_metrics_v3 ? metrics_v3->AverageSocketPower << 8 :
 821                         use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 :
 822                         metrics->AverageSocketPower << 8;
 823                 break;
 824         case METRICS_TEMPERATURE_EDGE:
 825                 *value = (use_metrics_v3 ? metrics_v3->TemperatureEdge :
 826                         use_metrics_v2 ? metrics_v2->TemperatureEdge :
 827                         metrics->TemperatureEdge) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 828                 break;
 829         case METRICS_TEMPERATURE_HOTSPOT:
 830                 *value = (use_metrics_v3 ? metrics_v3->TemperatureHotspot :
 831                         use_metrics_v2 ? metrics_v2->TemperatureHotspot :
 832                         metrics->TemperatureHotspot) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 833                 break;
 834         case METRICS_TEMPERATURE_MEM:
 835                 *value = (use_metrics_v3 ? metrics_v3->TemperatureMem :
 836                         use_metrics_v2 ? metrics_v2->TemperatureMem :
 837                         metrics->TemperatureMem) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 838                 break;
 839         case METRICS_TEMPERATURE_VRGFX:
 840                 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
 841                         use_metrics_v2 ? metrics_v2->TemperatureVrGfx :
 842                         metrics->TemperatureVrGfx) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 843                 break;
 844         case METRICS_TEMPERATURE_VRSOC:
 845                 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
 846                         use_metrics_v2 ? metrics_v2->TemperatureVrSoc :
 847                         metrics->TemperatureVrSoc) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 848                 break;
 849         case METRICS_THROTTLER_STATUS:
 850                 *value = sienna_cichlid_get_throttler_status_locked(smu);
 851                 break;
 852         case METRICS_CURR_FANSPEED:
 853                 *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
 854                         use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
 855                 break;
 856         case METRICS_UNIQUE_ID_UPPER32:
 857                 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
 858                 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumUpper32 : 0;
 859                 break;
 860         case METRICS_UNIQUE_ID_LOWER32:
 861                 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
 862                 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumLower32 : 0;
 863                 break;
 864         case METRICS_SS_APU_SHARE:
 865                 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
 866                 *value = apu_percent;
 867                 break;
 868         case METRICS_SS_DGPU_SHARE:
 869                 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
 870                 *value = dgpu_percent;
 871                 break;
 872
 873         default:
 874                 *value = UINT_MAX;
 875                 break;
 876         }
 877
 878         return ret;
 879
 880 }
 881
 882 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
 883 {
 884         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 885
 886         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 887                                        GFP_KERNEL);
 888         if (!smu_dpm->dpm_context)
 889                 return -ENOMEM;
 890
 891         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 892
 893         return 0;
 894 }
 895
 896 static void sienna_cichlid_stb_init(struct smu_context *smu);
 897
 898 static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
 899 {
 900         int ret = 0;
 901
 902         ret = sienna_cichlid_tables_init(smu);
 903         if (ret)
 904                 return ret;
 905
 906         ret = sienna_cichlid_allocate_dpm_context(smu);
 907         if (ret)
 908                 return ret;
 909
 910         sienna_cichlid_stb_init(smu);
 911
 912         return smu_v11_0_init_smc_tables(smu);
 913 }
 914
 915 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 916 {
 917         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 918         struct smu_11_0_dpm_table *dpm_table;
 919         struct amdgpu_device *adev = smu->adev;
 920         int i, ret = 0;
 921         DpmDescriptor_t *table_member;
 922
 923         /* socclk dpm table setup */
 924         dpm_table = &dpm_context->dpm_tables.soc_table;
 925         GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
 926         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 927                 ret = smu_v11_0_set_single_dpm_table(smu,
 928                                                      SMU_SOCCLK,
 929                                                      dpm_table);
 930                 if (ret)
 931                         return ret;
 932                 dpm_table->is_fine_grained =
 933                         !table_member[PPCLK_SOCCLK].SnapToDiscrete;
 934         } else {
 935                 dpm_table->count = 1;
 936                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 937                 dpm_table->dpm_levels[0].enabled = true;
 938                 dpm_table->min = dpm_table->dpm_levels[0].value;
 939                 dpm_table->max = dpm_table->dpm_levels[0].value;
 940         }
 941
 942         /* gfxclk dpm table setup */
 943         dpm_table = &dpm_context->dpm_tables.gfx_table;
 944         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 945                 ret = smu_v11_0_set_single_dpm_table(smu,
 946                                                      SMU_GFXCLK,
 947                                                      dpm_table);
 948                 if (ret)
 949                         return ret;
 950                 dpm_table->is_fine_grained =
 951                         !table_member[PPCLK_GFXCLK].SnapToDiscrete;
 952         } else {
 953                 dpm_table->count = 1;
 954                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 955                 dpm_table->dpm_levels[0].enabled = true;
 956                 dpm_table->min = dpm_table->dpm_levels[0].value;
 957                 dpm_table->max = dpm_table->dpm_levels[0].value;
 958         }
 959
 960         /* uclk dpm table setup */
 961         dpm_table = &dpm_context->dpm_tables.uclk_table;
 962         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 963                 ret = smu_v11_0_set_single_dpm_table(smu,
 964                                                      SMU_UCLK,
 965                                                      dpm_table);
 966                 if (ret)
 967                         return ret;
 968                 dpm_table->is_fine_grained =
 969                         !table_member[PPCLK_UCLK].SnapToDiscrete;
 970         } else {
 971                 dpm_table->count = 1;
 972                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 973                 dpm_table->dpm_levels[0].enabled = true;
 974                 dpm_table->min = dpm_table->dpm_levels[0].value;
 975                 dpm_table->max = dpm_table->dpm_levels[0].value;
 976         }
 977
 978         /* fclk dpm table setup */
 979         dpm_table = &dpm_context->dpm_tables.fclk_table;
 980         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 981                 ret = smu_v11_0_set_single_dpm_table(smu,
 982                                                      SMU_FCLK,
 983                                                      dpm_table);
 984                 if (ret)
 985                         return ret;
 986                 dpm_table->is_fine_grained =
 987                         !table_member[PPCLK_FCLK].SnapToDiscrete;
 988         } else {
 989                 dpm_table->count = 1;
 990                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 991                 dpm_table->dpm_levels[0].enabled = true;
 992                 dpm_table->min = dpm_table->dpm_levels[0].value;
 993                 dpm_table->max = dpm_table->dpm_levels[0].value;
 994         }
 995
 996         /* vclk0/1 dpm table setup */
 997         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 998                 if (adev->vcn.harvest_config & (1 << i))
 999                         continue;
1000
1001                 dpm_table = &dpm_context->dpm_tables.vclk_table;
1002                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1003                         ret = smu_v11_0_set_single_dpm_table(smu,
1004                                                              i ? SMU_VCLK1 : SMU_VCLK,
1005                                                              dpm_table);
1006                         if (ret)
1007                                 return ret;
1008                         dpm_table->is_fine_grained =
1009                                 !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete;
1010                 } else {
1011                         dpm_table->count = 1;
1012                         dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
1013                         dpm_table->dpm_levels[0].enabled = true;
1014                         dpm_table->min = dpm_table->dpm_levels[0].value;
1015                         dpm_table->max = dpm_table->dpm_levels[0].value;
1016                 }
1017         }
1018
1019         /* dclk0/1 dpm table setup */
1020         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1021                 if (adev->vcn.harvest_config & (1 << i))
1022                         continue;
1023                 dpm_table = &dpm_context->dpm_tables.dclk_table;
1024                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1025                         ret = smu_v11_0_set_single_dpm_table(smu,
1026                                                              i ? SMU_DCLK1 : SMU_DCLK,
1027                                                              dpm_table);
1028                         if (ret)
1029                                 return ret;
1030                         dpm_table->is_fine_grained =
1031                                 !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete;
1032                 } else {
1033                         dpm_table->count = 1;
1034                         dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
1035                         dpm_table->dpm_levels[0].enabled = true;
1036                         dpm_table->min = dpm_table->dpm_levels[0].value;
1037                         dpm_table->max = dpm_table->dpm_levels[0].value;
1038                 }
1039         }
1040
1041         /* dcefclk dpm table setup */
1042         dpm_table = &dpm_context->dpm_tables.dcef_table;
1043         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1044                 ret = smu_v11_0_set_single_dpm_table(smu,
1045                                                      SMU_DCEFCLK,
1046                                                      dpm_table);
1047                 if (ret)
1048                         return ret;
1049                 dpm_table->is_fine_grained =
1050                         !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
1051         } else {
1052                 dpm_table->count = 1;
1053                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1054                 dpm_table->dpm_levels[0].enabled = true;
1055                 dpm_table->min = dpm_table->dpm_levels[0].value;
1056                 dpm_table->max = dpm_table->dpm_levels[0].value;
1057         }
1058
1059         /* pixelclk dpm table setup */
1060         dpm_table = &dpm_context->dpm_tables.pixel_table;
1061         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1062                 ret = smu_v11_0_set_single_dpm_table(smu,
1063                                                      SMU_PIXCLK,
1064                                                      dpm_table);
1065                 if (ret)
1066                         return ret;
1067                 dpm_table->is_fine_grained =
1068                         !table_member[PPCLK_PIXCLK].SnapToDiscrete;
1069         } else {
1070                 dpm_table->count = 1;
1071                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1072                 dpm_table->dpm_levels[0].enabled = true;
1073                 dpm_table->min = dpm_table->dpm_levels[0].value;
1074                 dpm_table->max = dpm_table->dpm_levels[0].value;
1075         }
1076
1077         /* displayclk dpm table setup */
1078         dpm_table = &dpm_context->dpm_tables.display_table;
1079         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1080                 ret = smu_v11_0_set_single_dpm_table(smu,
1081                                                      SMU_DISPCLK,
1082                                                      dpm_table);
1083                 if (ret)
1084                         return ret;
1085                 dpm_table->is_fine_grained =
1086                         !table_member[PPCLK_DISPCLK].SnapToDiscrete;
1087         } else {
1088                 dpm_table->count = 1;
1089                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1090                 dpm_table->dpm_levels[0].enabled = true;
1091                 dpm_table->min = dpm_table->dpm_levels[0].value;
1092                 dpm_table->max = dpm_table->dpm_levels[0].value;
1093         }
1094
1095         /* phyclk dpm table setup */
1096         dpm_table = &dpm_context->dpm_tables.phy_table;
1097         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1098                 ret = smu_v11_0_set_single_dpm_table(smu,
1099                                                      SMU_PHYCLK,
1100                                                      dpm_table);
1101                 if (ret)
1102                         return ret;
1103                 dpm_table->is_fine_grained =
1104                         !table_member[PPCLK_PHYCLK].SnapToDiscrete;
1105         } else {
1106                 dpm_table->count = 1;
1107                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1108                 dpm_table->dpm_levels[0].enabled = true;
1109                 dpm_table->min = dpm_table->dpm_levels[0].value;
1110                 dpm_table->max = dpm_table->dpm_levels[0].value;
1111         }
1112
1113         return 0;
1114 }
1115
1116 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1117 {
1118         struct amdgpu_device *adev = smu->adev;
1119         int i, ret = 0;
1120
1121         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1122                 if (adev->vcn.harvest_config & (1 << i))
1123                         continue;
1124                 /* vcn dpm on is a prerequisite for vcn power gate messages */
1125                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1126                         ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1127                                                               SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
1128                                                               0x10000 * i, NULL);
1129                         if (ret)
1130                                 return ret;
1131                 }
1132         }
1133
1134         return ret;
1135 }
1136
1137 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1138 {
1139         int ret = 0;
1140
1141         if (enable) {
1142                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1143                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
1144                         if (ret)
1145                                 return ret;
1146                 }
1147         } else {
1148                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1149                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
1150                         if (ret)
1151                                 return ret;
1152                 }
1153         }
1154
1155         return ret;
1156 }
1157
1158 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
1159                                        enum smu_clk_type clk_type,
1160                                        uint32_t *value)
1161 {
1162         MetricsMember_t member_type;
1163         int clk_id = 0;
1164
1165         clk_id = smu_cmn_to_asic_specific_index(smu,
1166                                                 CMN2ASIC_MAPPING_CLK,
1167                                                 clk_type);
1168         if (clk_id < 0)
1169                 return clk_id;
1170
1171         switch (clk_id) {
1172         case PPCLK_GFXCLK:
1173                 member_type = METRICS_CURR_GFXCLK;
1174                 break;
1175         case PPCLK_UCLK:
1176                 member_type = METRICS_CURR_UCLK;
1177                 break;
1178         case PPCLK_SOCCLK:
1179                 member_type = METRICS_CURR_SOCCLK;
1180                 break;
1181         case PPCLK_FCLK:
1182                 member_type = METRICS_CURR_FCLK;
1183                 break;
1184         case PPCLK_VCLK_0:
1185                 member_type = METRICS_CURR_VCLK;
1186                 break;
1187         case PPCLK_VCLK_1:
1188                 member_type = METRICS_CURR_VCLK1;
1189                 break;
1190         case PPCLK_DCLK_0:
1191                 member_type = METRICS_CURR_DCLK;
1192                 break;
1193         case PPCLK_DCLK_1:
1194                 member_type = METRICS_CURR_DCLK1;
1195                 break;
1196         case PPCLK_DCEFCLK:
1197                 member_type = METRICS_CURR_DCEFCLK;
1198                 break;
1199         default:
1200                 return -EINVAL;
1201         }
1202
1203         return sienna_cichlid_get_smu_metrics_data(smu,
1204                                                    member_type,
1205                                                    value);
1206
1207 }
1208
1209 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1210 {
1211         DpmDescriptor_t *dpm_desc = NULL;
1212         DpmDescriptor_t *table_member;
1213         uint32_t clk_index = 0;
1214
1215         GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
1216         clk_index = smu_cmn_to_asic_specific_index(smu,
1217                                                    CMN2ASIC_MAPPING_CLK,
1218                                                    clk_type);
1219         dpm_desc = &table_member[clk_index];
1220
1221         /* 0 - Fine grained DPM, 1 - Discrete DPM */
1222         return dpm_desc->SnapToDiscrete == 0;
1223 }
1224
1225 static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
1226                                                    enum SMU_11_0_7_ODFEATURE_CAP cap)
1227 {
1228         return od_table->cap[cap];
1229 }
1230
1231 static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
1232                                                 enum SMU_11_0_7_ODSETTING_ID setting,
1233                                                 uint32_t *min, uint32_t *max)
1234 {
1235         if (min)
1236                 *min = od_table->min[setting];
1237         if (max)
1238                 *max = od_table->max[setting];
1239 }
1240
1241 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1242                         enum smu_clk_type clk_type, char *buf)
1243 {
1244         struct amdgpu_device *adev = smu->adev;
1245         struct smu_table_context *table_context = &smu->smu_table;
1246         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1247         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1248         uint16_t *table_member;
1249
1250         struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1251         OverDriveTable_t *od_table =
1252                 (OverDriveTable_t *)table_context->overdrive_table;
1253         int i, size = 0, ret = 0;
1254         uint32_t cur_value = 0, value = 0, count = 0;
1255         uint32_t freq_values[3] = {0};
1256         uint32_t mark_index = 0;
1257         uint32_t gen_speed, lane_width;
1258         uint32_t min_value, max_value;
1259         uint32_t smu_version;
1260
1261         smu_cmn_get_sysfs_buf(&buf, &size);
1262
1263         switch (clk_type) {
1264         case SMU_GFXCLK:
1265         case SMU_SCLK:
1266         case SMU_SOCCLK:
1267         case SMU_MCLK:
1268         case SMU_UCLK:
1269         case SMU_FCLK:
1270         case SMU_VCLK:
1271         case SMU_VCLK1:
1272         case SMU_DCLK:
1273         case SMU_DCLK1:
1274         case SMU_DCEFCLK:
1275                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1276                 if (ret)
1277                         goto print_clk_out;
1278
1279                 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1280                 if (ret)
1281                         goto print_clk_out;
1282
1283                 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1284                         for (i = 0; i < count; i++) {
1285                                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1286                                 if (ret)
1287                                         goto print_clk_out;
1288
1289                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1290                                                 cur_value == value ? "*" : "");
1291                         }
1292                 } else {
1293                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1294                         if (ret)
1295                                 goto print_clk_out;
1296                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1297                         if (ret)
1298                                 goto print_clk_out;
1299
1300                         freq_values[1] = cur_value;
1301                         mark_index = cur_value == freq_values[0] ? 0 :
1302                                      cur_value == freq_values[2] ? 2 : 1;
1303
1304                         count = 3;
1305                         if (mark_index != 1) {
1306                                 count = 2;
1307                                 freq_values[1] = freq_values[2];
1308                         }
1309
1310                         for (i = 0; i < count; i++) {
1311                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
1312                                                 cur_value  == freq_values[i] ? "*" : "");
1313                         }
1314
1315                 }
1316                 break;
1317         case SMU_PCIE:
1318                 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1319                 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1320                 GET_PPTABLE_MEMBER(LclkFreq, &table_member);
1321                 for (i = 0; i < NUM_LINK_LEVELS; i++)
1322                         size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1323                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1324                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1325                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1326                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1327                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1328                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1329                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1330                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1331                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1332                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1333                                         table_member[i],
1334                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1335                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1336                                         "*" : "");
1337                 break;
1338         case SMU_OD_SCLK:
1339                 if (!smu->od_enabled || !od_table || !od_settings)
1340                         break;
1341
1342                 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1343                         break;
1344
1345                 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1346                 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1347                 break;
1348
1349         case SMU_OD_MCLK:
1350                 if (!smu->od_enabled || !od_table || !od_settings)
1351                         break;
1352
1353                 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1354                         break;
1355
1356                 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1357                 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
1358                 break;
1359
1360         case SMU_OD_VDDGFX_OFFSET:
1361                 if (!smu->od_enabled || !od_table || !od_settings)
1362                         break;
1363
1364                 /*
1365                  * OD GFX Voltage Offset functionality is supported only by 58.41.0
1366                  * and onwards SMU firmwares.
1367                  */
1368                 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1369                 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
1370                      (smu_version < 0x003a2900))
1371                         break;
1372
1373                 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1374                 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset);
1375                 break;
1376
1377         case SMU_OD_RANGE:
1378                 if (!smu->od_enabled || !od_table || !od_settings)
1379                         break;
1380
1381                 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1382
1383                 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1384                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1385                                                             &min_value, NULL);
1386                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1387                                                             NULL, &max_value);
1388                         size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1389                                         min_value, max_value);
1390                 }
1391
1392                 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1393                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1394                                                             &min_value, NULL);
1395                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1396                                                             NULL, &max_value);
1397                         size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1398                                         min_value, max_value);
1399                 }
1400                 break;
1401
1402         default:
1403                 break;
1404         }
1405
1406 print_clk_out:
1407         return size;
1408 }
1409
1410 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1411                                    enum smu_clk_type clk_type, uint32_t mask)
1412 {
1413         int ret = 0;
1414         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1415
1416         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1417         soft_max_level = mask ? (fls(mask) - 1) : 0;
1418
1419         switch (clk_type) {
1420         case SMU_GFXCLK:
1421         case SMU_SCLK:
1422         case SMU_SOCCLK:
1423         case SMU_MCLK:
1424         case SMU_UCLK:
1425         case SMU_FCLK:
1426                 /* There is only 2 levels for fine grained DPM */
1427                 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1428                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1429                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1430                 }
1431
1432                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1433                 if (ret)
1434                         goto forec_level_out;
1435
1436                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1437                 if (ret)
1438                         goto forec_level_out;
1439
1440                 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1441                 if (ret)
1442                         goto forec_level_out;
1443                 break;
1444         case SMU_DCEFCLK:
1445                 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1446                 break;
1447         default:
1448                 break;
1449         }
1450
1451 forec_level_out:
1452         return 0;
1453 }
1454
1455 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1456 {
1457         struct smu_11_0_dpm_context *dpm_context =
1458                                 smu->smu_dpm.dpm_context;
1459         struct smu_11_0_dpm_table *gfx_table =
1460                                 &dpm_context->dpm_tables.gfx_table;
1461         struct smu_11_0_dpm_table *mem_table =
1462                                 &dpm_context->dpm_tables.uclk_table;
1463         struct smu_11_0_dpm_table *soc_table =
1464                                 &dpm_context->dpm_tables.soc_table;
1465         struct smu_umd_pstate_table *pstate_table =
1466                                 &smu->pstate_table;
1467         struct amdgpu_device *adev = smu->adev;
1468
1469         pstate_table->gfxclk_pstate.min = gfx_table->min;
1470         pstate_table->gfxclk_pstate.peak = gfx_table->max;
1471
1472         pstate_table->uclk_pstate.min = mem_table->min;
1473         pstate_table->uclk_pstate.peak = mem_table->max;
1474
1475         pstate_table->socclk_pstate.min = soc_table->min;
1476         pstate_table->socclk_pstate.peak = soc_table->max;
1477
1478         switch (adev->asic_type) {
1479         case CHIP_SIENNA_CICHLID:
1480         case CHIP_NAVY_FLOUNDER:
1481                 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
1482                 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
1483                 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
1484                 break;
1485         case CHIP_DIMGREY_CAVEFISH:
1486                 pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;
1487                 pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;
1488                 pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;
1489                 break;
1490         case CHIP_BEIGE_GOBY:
1491                 pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;
1492                 pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;
1493                 pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;
1494                 break;
1495         default:
1496                 break;
1497         }
1498
1499         return 0;
1500 }
1501
1502 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1503 {
1504         int ret = 0;
1505         uint32_t max_freq = 0;
1506
1507         /* Sienna_Cichlid do not support to change display num currently */
1508         return 0;
1509 #if 0
1510         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1511         if (ret)
1512                 return ret;
1513 #endif
1514
1515         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1516                 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1517                 if (ret)
1518                         return ret;
1519                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1520                 if (ret)
1521                         return ret;
1522         }
1523
1524         return ret;
1525 }
1526
1527 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1528 {
1529         int ret = 0;
1530
1531         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1532             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1533             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1534 #if 0
1535                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1536                                                   smu->display_config->num_display,
1537                                                   NULL);
1538 #endif
1539                 if (ret)
1540                         return ret;
1541         }
1542
1543         return ret;
1544 }
1545
1546 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1547 {
1548         int ret = 0;
1549         uint64_t feature_enabled;
1550
1551         ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1552         if (ret)
1553                 return false;
1554
1555         return !!(feature_enabled & SMC_DPM_FEATURE);
1556 }
1557
1558 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1559                                             uint32_t *speed)
1560 {
1561         if (!speed)
1562                 return -EINVAL;
1563
1564         /*
1565          * For Sienna_Cichlid and later, the fan speed(rpm) reported
1566          * by pmfw is always trustable(even when the fan control feature
1567          * disabled or 0 RPM kicked in).
1568          */
1569         return sienna_cichlid_get_smu_metrics_data(smu,
1570                                                    METRICS_CURR_FANSPEED,
1571                                                    speed);
1572 }
1573
1574 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1575 {
1576         uint16_t *table_member;
1577
1578         GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1579         smu->fan_max_rpm = *table_member;
1580
1581         return 0;
1582 }
1583
1584 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1585 {
1586         DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1587         DpmActivityMonitorCoeffInt_t *activity_monitor =
1588                 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1589         uint32_t i, size = 0;
1590         int16_t workload_type = 0;
1591         static const char *title[] = {
1592                         "PROFILE_INDEX(NAME)",
1593                         "CLOCK_TYPE(NAME)",
1594                         "FPS",
1595                         "MinFreqType",
1596                         "MinActiveFreqType",
1597                         "MinActiveFreq",
1598                         "BoosterFreqType",
1599                         "BoosterFreq",
1600                         "PD_Data_limit_c",
1601                         "PD_Data_error_coeff",
1602                         "PD_Data_error_rate_coeff"};
1603         int result = 0;
1604
1605         if (!buf)
1606                 return -EINVAL;
1607
1608         size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1609                         title[0], title[1], title[2], title[3], title[4], title[5],
1610                         title[6], title[7], title[8], title[9], title[10]);
1611
1612         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1613                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1614                 workload_type = smu_cmn_to_asic_specific_index(smu,
1615                                                                CMN2ASIC_MAPPING_WORKLOAD,
1616                                                                i);
1617                 if (workload_type < 0)
1618                         return -EINVAL;
1619
1620                 result = smu_cmn_update_table(smu,
1621                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1622                                           (void *)(&activity_monitor_external), false);
1623                 if (result) {
1624                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1625                         return result;
1626                 }
1627
1628                 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1629                         i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1630
1631                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1632                         " ",
1633                         0,
1634                         "GFXCLK",
1635                         activity_monitor->Gfx_FPS,
1636                         activity_monitor->Gfx_MinFreqStep,
1637                         activity_monitor->Gfx_MinActiveFreqType,
1638                         activity_monitor->Gfx_MinActiveFreq,
1639                         activity_monitor->Gfx_BoosterFreqType,
1640                         activity_monitor->Gfx_BoosterFreq,
1641                         activity_monitor->Gfx_PD_Data_limit_c,
1642                         activity_monitor->Gfx_PD_Data_error_coeff,
1643                         activity_monitor->Gfx_PD_Data_error_rate_coeff);
1644
1645                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1646                         " ",
1647                         1,
1648                         "SOCCLK",
1649                         activity_monitor->Fclk_FPS,
1650                         activity_monitor->Fclk_MinFreqStep,
1651                         activity_monitor->Fclk_MinActiveFreqType,
1652                         activity_monitor->Fclk_MinActiveFreq,
1653                         activity_monitor->Fclk_BoosterFreqType,
1654                         activity_monitor->Fclk_BoosterFreq,
1655                         activity_monitor->Fclk_PD_Data_limit_c,
1656                         activity_monitor->Fclk_PD_Data_error_coeff,
1657                         activity_monitor->Fclk_PD_Data_error_rate_coeff);
1658
1659                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1660                         " ",
1661                         2,
1662                         "MEMLK",
1663                         activity_monitor->Mem_FPS,
1664                         activity_monitor->Mem_MinFreqStep,
1665                         activity_monitor->Mem_MinActiveFreqType,
1666                         activity_monitor->Mem_MinActiveFreq,
1667                         activity_monitor->Mem_BoosterFreqType,
1668                         activity_monitor->Mem_BoosterFreq,
1669                         activity_monitor->Mem_PD_Data_limit_c,
1670                         activity_monitor->Mem_PD_Data_error_coeff,
1671                         activity_monitor->Mem_PD_Data_error_rate_coeff);
1672         }
1673
1674         return size;
1675 }
1676
1677 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1678 {
1679
1680         DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1681         DpmActivityMonitorCoeffInt_t *activity_monitor =
1682                 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1683         int workload_type, ret = 0;
1684
1685         smu->power_profile_mode = input[size];
1686
1687         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1688                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1689                 return -EINVAL;
1690         }
1691
1692         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1693
1694                 ret = smu_cmn_update_table(smu,
1695                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1696                                        (void *)(&activity_monitor_external), false);
1697                 if (ret) {
1698                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1699                         return ret;
1700                 }
1701
1702                 switch (input[0]) {
1703                 case 0: /* Gfxclk */
1704                         activity_monitor->Gfx_FPS = input[1];
1705                         activity_monitor->Gfx_MinFreqStep = input[2];
1706                         activity_monitor->Gfx_MinActiveFreqType = input[3];
1707                         activity_monitor->Gfx_MinActiveFreq = input[4];
1708                         activity_monitor->Gfx_BoosterFreqType = input[5];
1709                         activity_monitor->Gfx_BoosterFreq = input[6];
1710                         activity_monitor->Gfx_PD_Data_limit_c = input[7];
1711                         activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1712                         activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
1713                         break;
1714                 case 1: /* Socclk */
1715                         activity_monitor->Fclk_FPS = input[1];
1716                         activity_monitor->Fclk_MinFreqStep = input[2];
1717                         activity_monitor->Fclk_MinActiveFreqType = input[3];
1718                         activity_monitor->Fclk_MinActiveFreq = input[4];
1719                         activity_monitor->Fclk_BoosterFreqType = input[5];
1720                         activity_monitor->Fclk_BoosterFreq = input[6];
1721                         activity_monitor->Fclk_PD_Data_limit_c = input[7];
1722                         activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1723                         activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
1724                         break;
1725                 case 2: /* Memlk */
1726                         activity_monitor->Mem_FPS = input[1];
1727                         activity_monitor->Mem_MinFreqStep = input[2];
1728                         activity_monitor->Mem_MinActiveFreqType = input[3];
1729                         activity_monitor->Mem_MinActiveFreq = input[4];
1730                         activity_monitor->Mem_BoosterFreqType = input[5];
1731                         activity_monitor->Mem_BoosterFreq = input[6];
1732                         activity_monitor->Mem_PD_Data_limit_c = input[7];
1733                         activity_monitor->Mem_PD_Data_error_coeff = input[8];
1734                         activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
1735                         break;
1736                 }
1737
1738                 ret = smu_cmn_update_table(smu,
1739                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1740                                        (void *)(&activity_monitor_external), true);
1741                 if (ret) {
1742                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1743                         return ret;
1744                 }
1745         }
1746
1747         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1748         workload_type = smu_cmn_to_asic_specific_index(smu,
1749                                                        CMN2ASIC_MAPPING_WORKLOAD,
1750                                                        smu->power_profile_mode);
1751         if (workload_type < 0)
1752                 return -EINVAL;
1753         smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1754                                     1 << workload_type, NULL);
1755
1756         return ret;
1757 }
1758
1759 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1760 {
1761         struct smu_clocks min_clocks = {0};
1762         struct pp_display_clock_request clock_req;
1763         int ret = 0;
1764
1765         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1766         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1767         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1768
1769         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1770                 clock_req.clock_type = amd_pp_dcef_clock;
1771                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1772
1773                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1774                 if (!ret) {
1775                         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1776                                 ret = smu_cmn_send_smc_msg_with_param(smu,
1777                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1778                                                                   min_clocks.dcef_clock_in_sr/100,
1779                                                                   NULL);
1780                                 if (ret) {
1781                                         dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1782                                         return ret;
1783                                 }
1784                         }
1785                 } else {
1786                         dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1787                 }
1788         }
1789
1790         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1791                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1792                 if (ret) {
1793                         dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1794                         return ret;
1795                 }
1796         }
1797
1798         return 0;
1799 }
1800
1801 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1802                                                struct pp_smu_wm_range_sets *clock_ranges)
1803 {
1804         Watermarks_t *table = smu->smu_table.watermarks_table;
1805         int ret = 0;
1806         int i;
1807
1808         if (clock_ranges) {
1809                 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1810                     clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1811                         return -EINVAL;
1812
1813                 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1814                         table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1815                                 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1816                         table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1817                                 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1818                         table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1819                                 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1820                         table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1821                                 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1822
1823                         table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1824                                 clock_ranges->reader_wm_sets[i].wm_inst;
1825                 }
1826
1827                 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1828                         table->WatermarkRow[WM_SOCCLK][i].MinClock =
1829                                 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1830                         table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1831                                 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1832                         table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1833                                 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1834                         table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1835                                 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1836
1837                         table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1838                                 clock_ranges->writer_wm_sets[i].wm_inst;
1839                 }
1840
1841                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1842         }
1843
1844         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1845              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1846                 ret = smu_cmn_write_watermarks_table(smu);
1847                 if (ret) {
1848                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1849                         return ret;
1850                 }
1851                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1852         }
1853
1854         return 0;
1855 }
1856
1857 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1858                                  enum amd_pp_sensors sensor,
1859                                  void *data, uint32_t *size)
1860 {
1861         int ret = 0;
1862         uint16_t *temp;
1863         struct amdgpu_device *adev = smu->adev;
1864
1865         if(!data || !size)
1866                 return -EINVAL;
1867
1868         switch (sensor) {
1869         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1870                 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1871                 *(uint16_t *)data = *temp;
1872                 *size = 4;
1873                 break;
1874         case AMDGPU_PP_SENSOR_MEM_LOAD:
1875                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1876                                                           METRICS_AVERAGE_MEMACTIVITY,
1877                                                           (uint32_t *)data);
1878                 *size = 4;
1879                 break;
1880         case AMDGPU_PP_SENSOR_GPU_LOAD:
1881                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1882                                                           METRICS_AVERAGE_GFXACTIVITY,
1883                                                           (uint32_t *)data);
1884                 *size = 4;
1885                 break;
1886         case AMDGPU_PP_SENSOR_GPU_POWER:
1887                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1888                                                           METRICS_AVERAGE_SOCKETPOWER,
1889                                                           (uint32_t *)data);
1890                 *size = 4;
1891                 break;
1892         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1893                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1894                                                           METRICS_TEMPERATURE_HOTSPOT,
1895                                                           (uint32_t *)data);
1896                 *size = 4;
1897                 break;
1898         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1899                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1900                                                           METRICS_TEMPERATURE_EDGE,
1901                                                           (uint32_t *)data);
1902                 *size = 4;
1903                 break;
1904         case AMDGPU_PP_SENSOR_MEM_TEMP:
1905                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1906                                                           METRICS_TEMPERATURE_MEM,
1907                                                           (uint32_t *)data);
1908                 *size = 4;
1909                 break;
1910         case AMDGPU_PP_SENSOR_GFX_MCLK:
1911                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1912                 *(uint32_t *)data *= 100;
1913                 *size = 4;
1914                 break;
1915         case AMDGPU_PP_SENSOR_GFX_SCLK:
1916                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1917                 *(uint32_t *)data *= 100;
1918                 *size = 4;
1919                 break;
1920         case AMDGPU_PP_SENSOR_VDDGFX:
1921                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1922                 *size = 4;
1923                 break;
1924         case AMDGPU_PP_SENSOR_SS_APU_SHARE:
1925                 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) {
1926                         ret = sienna_cichlid_get_smu_metrics_data(smu,
1927                                                 METRICS_SS_APU_SHARE, (uint32_t *)data);
1928                         *size = 4;
1929                 } else {
1930                         ret = -EOPNOTSUPP;
1931                 }
1932                 break;
1933         case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
1934                 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) {
1935                         ret = sienna_cichlid_get_smu_metrics_data(smu,
1936                                                 METRICS_SS_DGPU_SHARE, (uint32_t *)data);
1937                         *size = 4;
1938                 } else {
1939                         ret = -EOPNOTSUPP;
1940                 }
1941                 break;
1942         default:
1943                 ret = -EOPNOTSUPP;
1944                 break;
1945         }
1946
1947         return ret;
1948 }
1949
1950 static void sienna_cichlid_get_unique_id(struct smu_context *smu)
1951 {
1952         struct amdgpu_device *adev = smu->adev;
1953         uint32_t upper32 = 0, lower32 = 0;
1954
1955         /* Only supported as of version 0.58.83.0 and only on Sienna Cichlid */
1956         if (smu->smc_fw_version < 0x3A5300 ||
1957             smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7))
1958                 return;
1959
1960         if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32))
1961                 goto out;
1962         if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32))
1963                 goto out;
1964
1965 out:
1966
1967         adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1968         if (adev->serial[0] == '\0')
1969                 sprintf(adev->serial, "%016llx", adev->unique_id);
1970 }
1971
1972 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1973 {
1974         uint32_t num_discrete_levels = 0;
1975         uint16_t *dpm_levels = NULL;
1976         uint16_t i = 0;
1977         struct smu_table_context *table_context = &smu->smu_table;
1978         DpmDescriptor_t *table_member1;
1979         uint16_t *table_member2;
1980
1981         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1982                 return -EINVAL;
1983
1984         GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
1985         num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
1986         GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
1987         dpm_levels = table_member2;
1988
1989         if (num_discrete_levels == 0 || dpm_levels == NULL)
1990                 return -EINVAL;
1991
1992         *num_states = num_discrete_levels;
1993         for (i = 0; i < num_discrete_levels; i++) {
1994                 /* convert to khz */
1995                 *clocks_in_khz = (*dpm_levels) * 1000;
1996                 clocks_in_khz++;
1997                 dpm_levels++;
1998         }
1999
2000         return 0;
2001 }
2002
2003 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
2004                                                 struct smu_temperature_range *range)
2005 {
2006         struct smu_table_context *table_context = &smu->smu_table;
2007         struct smu_11_0_7_powerplay_table *powerplay_table =
2008                                 table_context->power_play_table;
2009         uint16_t *table_member;
2010         uint16_t temp_edge, temp_hotspot, temp_mem;
2011
2012         if (!range)
2013                 return -EINVAL;
2014
2015         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2016
2017         GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
2018         temp_edge = table_member[TEMP_EDGE];
2019         temp_hotspot = table_member[TEMP_HOTSPOT];
2020         temp_mem = table_member[TEMP_MEM];
2021
2022         range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2023         range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
2024                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2025         range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2026         range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
2027                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2028         range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2029         range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
2030                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2031
2032         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2033
2034         return 0;
2035 }
2036
2037 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
2038                                                 bool disable_memory_clock_switch)
2039 {
2040         int ret = 0;
2041         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2042                 (struct smu_11_0_max_sustainable_clocks *)
2043                         smu->smu_table.max_sustainable_clocks;
2044         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2045         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2046
2047         if(smu->disable_uclk_switch == disable_memory_clock_switch)
2048                 return 0;
2049
2050         if(disable_memory_clock_switch)
2051                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
2052         else
2053                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
2054
2055         if(!ret)
2056                 smu->disable_uclk_switch = disable_memory_clock_switch;
2057
2058         return ret;
2059 }
2060
2061 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
2062                                          uint32_t pcie_gen_cap,
2063                                          uint32_t pcie_width_cap)
2064 {
2065         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2066
2067         uint32_t smu_pcie_arg;
2068         uint8_t *table_member1, *table_member2;
2069         int ret, i;
2070
2071         GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
2072         GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
2073
2074         /* lclk dpm table setup */
2075         for (i = 0; i < MAX_PCIE_CONF; i++) {
2076                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = table_member1[i];
2077                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = table_member2[i];
2078         }
2079
2080         for (i = 0; i < NUM_LINK_LEVELS; i++) {
2081                 smu_pcie_arg = (i << 16) |
2082                         ((table_member1[i] <= pcie_gen_cap) ?
2083                          (table_member1[i] << 8) :
2084                          (pcie_gen_cap << 8)) |
2085                         ((table_member2[i] <= pcie_width_cap) ?
2086                          table_member2[i] :
2087                          pcie_width_cap);
2088
2089                 ret = smu_cmn_send_smc_msg_with_param(smu,
2090                                 SMU_MSG_OverridePcieParameters,
2091                                 smu_pcie_arg,
2092                                 NULL);
2093                 if (ret)
2094                         return ret;
2095
2096                 if (table_member1[i] > pcie_gen_cap)
2097                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
2098                 if (table_member2[i] > pcie_width_cap)
2099                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
2100         }
2101
2102         return 0;
2103 }
2104
2105 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
2106                                 enum smu_clk_type clk_type,
2107                                 uint32_t *min, uint32_t *max)
2108 {
2109         return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
2110 }
2111
2112 static void sienna_cichlid_dump_od_table(struct smu_context *smu,
2113                                          OverDriveTable_t *od_table)
2114 {
2115         struct amdgpu_device *adev = smu->adev;
2116         uint32_t smu_version;
2117
2118         dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
2119                                                           od_table->GfxclkFmax);
2120         dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
2121                                                         od_table->UclkFmax);
2122
2123         smu_cmn_get_smc_version(smu, NULL, &smu_version);
2124         if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
2125                (smu_version < 0x003a2900)))
2126                 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
2127 }
2128
2129 static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
2130 {
2131         OverDriveTable_t *od_table =
2132                 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2133         OverDriveTable_t *boot_od_table =
2134                 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2135         OverDriveTable_t *user_od_table =
2136                 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
2137         int ret = 0;
2138
2139         /*
2140          * For S3/S4/Runpm resume, no need to setup those overdrive tables again as
2141          *   - either they already have the default OD settings got during cold bootup
2142          *   - or they have some user customized OD settings which cannot be overwritten
2143          */
2144         if (smu->adev->in_suspend)
2145                 return 0;
2146
2147         ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
2148                                    0, (void *)boot_od_table, false);
2149         if (ret) {
2150                 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2151                 return ret;
2152         }
2153
2154         sienna_cichlid_dump_od_table(smu, boot_od_table);
2155
2156         memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
2157         memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2158
2159         return 0;
2160 }
2161
2162 static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
2163                                                  struct smu_11_0_7_overdrive_table *od_table,
2164                                                  enum SMU_11_0_7_ODSETTING_ID setting,
2165                                                  uint32_t value)
2166 {
2167         if (value < od_table->min[setting]) {
2168                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
2169                                           setting, value, od_table->min[setting]);
2170                 return -EINVAL;
2171         }
2172         if (value > od_table->max[setting]) {
2173                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
2174                                           setting, value, od_table->max[setting]);
2175                 return -EINVAL;
2176         }
2177
2178         return 0;
2179 }
2180
2181 static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
2182                                             enum PP_OD_DPM_TABLE_COMMAND type,
2183                                             long input[], uint32_t size)
2184 {
2185         struct smu_table_context *table_context = &smu->smu_table;
2186         OverDriveTable_t *od_table =
2187                 (OverDriveTable_t *)table_context->overdrive_table;
2188         struct smu_11_0_7_overdrive_table *od_settings =
2189                 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
2190         struct amdgpu_device *adev = smu->adev;
2191         enum SMU_11_0_7_ODSETTING_ID freq_setting;
2192         uint16_t *freq_ptr;
2193         int i, ret = 0;
2194         uint32_t smu_version;
2195
2196         if (!smu->od_enabled) {
2197                 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2198                 return -EINVAL;
2199         }
2200
2201         if (!smu->od_settings) {
2202                 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2203                 return -ENOENT;
2204         }
2205
2206         if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2207                 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2208                 return -EINVAL;
2209         }
2210
2211         switch (type) {
2212         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2213                 if (!sienna_cichlid_is_od_feature_supported(od_settings,
2214                                                             SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
2215                         dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2216                         return -ENOTSUPP;
2217                 }
2218
2219                 for (i = 0; i < size; i += 2) {
2220                         if (i + 2 > size) {
2221                                 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2222                                 return -EINVAL;
2223                         }
2224
2225                         switch (input[i]) {
2226                         case 0:
2227                                 if (input[i + 1] > od_table->GfxclkFmax) {
2228                                         dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2229                                                 input[i + 1], od_table->GfxclkFmax);
2230                                         return -EINVAL;
2231                                 }
2232
2233                                 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
2234                                 freq_ptr = &od_table->GfxclkFmin;
2235                                 break;
2236
2237                         case 1:
2238                                 if (input[i + 1] < od_table->GfxclkFmin) {
2239                                         dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2240                                                 input[i + 1], od_table->GfxclkFmin);
2241                                         return -EINVAL;
2242                                 }
2243
2244                                 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2245                                 freq_ptr = &od_table->GfxclkFmax;
2246                                 break;
2247
2248                         default:
2249                                 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2250                                 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2251                                 return -EINVAL;
2252                         }
2253
2254                         ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2255                                                                     freq_setting, input[i + 1]);
2256                         if (ret)
2257                                 return ret;
2258
2259                         *freq_ptr = (uint16_t)input[i + 1];
2260                 }
2261                 break;
2262
2263         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2264                 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2265                         dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2266                         return -ENOTSUPP;
2267                 }
2268
2269                 for (i = 0; i < size; i += 2) {
2270                         if (i + 2 > size) {
2271                                 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2272                                 return -EINVAL;
2273                         }
2274
2275                         switch (input[i]) {
2276                         case 0:
2277                                 if (input[i + 1] > od_table->UclkFmax) {
2278                                         dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2279                                                 input[i + 1], od_table->UclkFmax);
2280                                         return -EINVAL;
2281                                 }
2282
2283                                 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2284                                 freq_ptr = &od_table->UclkFmin;
2285                                 break;
2286
2287                         case 1:
2288                                 if (input[i + 1] < od_table->UclkFmin) {
2289                                         dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2290                                                 input[i + 1], od_table->UclkFmin);
2291                                         return -EINVAL;
2292                                 }
2293
2294                                 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2295                                 freq_ptr = &od_table->UclkFmax;
2296                                 break;
2297
2298                         default:
2299                                 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2300                                 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2301                                 return -EINVAL;
2302                         }
2303
2304                         ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2305                                                                     freq_setting, input[i + 1]);
2306                         if (ret)
2307                                 return ret;
2308
2309                         *freq_ptr = (uint16_t)input[i + 1];
2310                 }
2311                 break;
2312
2313         case PP_OD_RESTORE_DEFAULT_TABLE:
2314                 memcpy(table_context->overdrive_table,
2315                                 table_context->boot_overdrive_table,
2316                                 sizeof(OverDriveTable_t));
2317                 fallthrough;
2318
2319         case PP_OD_COMMIT_DPM_TABLE:
2320                 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2321                         sienna_cichlid_dump_od_table(smu, od_table);
2322                         ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2323                         if (ret) {
2324                                 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2325                                 return ret;
2326                         }
2327                         memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2328                         smu->user_dpm_profile.user_od = true;
2329
2330                         if (!memcmp(table_context->user_overdrive_table,
2331                                     table_context->boot_overdrive_table,
2332                                     sizeof(OverDriveTable_t)))
2333                                 smu->user_dpm_profile.user_od = false;
2334                 }
2335                 break;
2336
2337         case PP_OD_EDIT_VDDGFX_OFFSET:
2338                 if (size != 1) {
2339                         dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2340                         return -EINVAL;
2341                 }
2342
2343                 /*
2344                  * OD GFX Voltage Offset functionality is supported only by 58.41.0
2345                  * and onwards SMU firmwares.
2346                  */
2347                 smu_cmn_get_smc_version(smu, NULL, &smu_version);
2348                 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
2349                      (smu_version < 0x003a2900)) {
2350                         dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2351                                                 "only by 58.41.0 and onwards SMU firmwares!\n");
2352                         return -EOPNOTSUPP;
2353                 }
2354
2355                 od_table->VddGfxOffset = (int16_t)input[0];
2356
2357                 sienna_cichlid_dump_od_table(smu, od_table);
2358                 break;
2359
2360         default:
2361                 return -ENOSYS;
2362         }
2363
2364         return ret;
2365 }
2366
2367 static int sienna_cichlid_run_btc(struct smu_context *smu)
2368 {
2369         int res;
2370
2371         res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2372         if (res)
2373                 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2374
2375         return res;
2376 }
2377
2378 static int sienna_cichlid_baco_enter(struct smu_context *smu)
2379 {
2380         struct amdgpu_device *adev = smu->adev;
2381
2382         if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
2383                 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2384         else
2385                 return smu_v11_0_baco_enter(smu);
2386 }
2387
2388 static int sienna_cichlid_baco_exit(struct smu_context *smu)
2389 {
2390         struct amdgpu_device *adev = smu->adev;
2391
2392         if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2393                 /* Wait for PMFW handling for the Dstate change */
2394                 msleep(10);
2395                 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2396         } else {
2397                 return smu_v11_0_baco_exit(smu);
2398         }
2399 }
2400
2401 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2402 {
2403         struct amdgpu_device *adev = smu->adev;
2404         uint32_t val;
2405         u32 smu_version;
2406
2407         /**
2408          * SRIOV env will not support SMU mode1 reset
2409          * PM FW support mode1 reset from 58.26
2410          */
2411         smu_cmn_get_smc_version(smu, NULL, &smu_version);
2412         if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2413                 return false;
2414
2415         /**
2416          * mode1 reset relies on PSP, so we should check if
2417          * PSP is alive.
2418          */
2419         val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2420         return val != 0x0;
2421 }
2422
2423 static void beige_goby_dump_pptable(struct smu_context *smu)
2424 {
2425         struct smu_table_context *table_context = &smu->smu_table;
2426         PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2427         int i;
2428
2429         dev_info(smu->adev->dev, "Dumped PPTable:\n");
2430
2431         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2432         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2433         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2434
2435         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2436                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2437                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2438                 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2439                 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2440         }
2441
2442         for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2443                 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2444                 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2445         }
2446
2447         for (i = 0; i < TEMP_COUNT; i++) {
2448                 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2449         }
2450
2451         dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2452         dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2453         dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2454         dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2455         dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2456
2457         dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2458         for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2459                 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2460                 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2461         }
2462         dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2463
2464         dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2465
2466         dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2467         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2468         dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2469         dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2470
2471         dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2472
2473         dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2474
2475         dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2476         dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2477         dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2478         dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2479
2480         dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2481         dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2482
2483         dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2484         dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2485         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2486         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2487         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2488         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2489         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2490         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2491
2492         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2493                         "  .VoltageMode          = 0x%02x\n"
2494                         "  .SnapToDiscrete       = 0x%02x\n"
2495                         "  .NumDiscreteLevels    = 0x%02x\n"
2496                         "  .padding              = 0x%02x\n"
2497                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2498                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2499                         "  .SsFmin               = 0x%04x\n"
2500                         "  .Padding_16           = 0x%04x\n",
2501                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2502                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2503                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2504                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2505                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2506                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2507                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2508                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2509                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2510                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2511                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2512
2513         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2514                         "  .VoltageMode          = 0x%02x\n"
2515                         "  .SnapToDiscrete       = 0x%02x\n"
2516                         "  .NumDiscreteLevels    = 0x%02x\n"
2517                         "  .padding              = 0x%02x\n"
2518                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2519                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2520                         "  .SsFmin               = 0x%04x\n"
2521                         "  .Padding_16           = 0x%04x\n",
2522                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2523                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2524                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2525                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2526                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2527                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2528                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2529                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2530                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2531                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2532                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2533
2534         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2535                         "  .VoltageMode          = 0x%02x\n"
2536                         "  .SnapToDiscrete       = 0x%02x\n"
2537                         "  .NumDiscreteLevels    = 0x%02x\n"
2538                         "  .padding              = 0x%02x\n"
2539                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2540                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2541                         "  .SsFmin               = 0x%04x\n"
2542                         "  .Padding_16           = 0x%04x\n",
2543                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2544                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2545                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2546                         pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2547                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2548                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2549                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2550                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2551                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2552                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2553                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2554
2555         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2556                         "  .VoltageMode          = 0x%02x\n"
2557                         "  .SnapToDiscrete       = 0x%02x\n"
2558                         "  .NumDiscreteLevels    = 0x%02x\n"
2559                         "  .padding              = 0x%02x\n"
2560                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2561                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2562                         "  .SsFmin               = 0x%04x\n"
2563                         "  .Padding_16           = 0x%04x\n",
2564                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2565                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2566                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2567                         pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2568                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2569                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2570                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2571                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2572                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2573                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2574                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2575
2576         dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2577                         "  .VoltageMode          = 0x%02x\n"
2578                         "  .SnapToDiscrete       = 0x%02x\n"
2579                         "  .NumDiscreteLevels    = 0x%02x\n"
2580                         "  .padding              = 0x%02x\n"
2581                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2582                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2583                         "  .SsFmin               = 0x%04x\n"
2584                         "  .Padding_16           = 0x%04x\n",
2585                         pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2586                         pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2587                         pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2588                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2589                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2590                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2591                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2592                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2593                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2594                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2595                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2596
2597         dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2598                         "  .VoltageMode          = 0x%02x\n"
2599                         "  .SnapToDiscrete       = 0x%02x\n"
2600                         "  .NumDiscreteLevels    = 0x%02x\n"
2601                         "  .padding              = 0x%02x\n"
2602                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2603                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2604                         "  .SsFmin               = 0x%04x\n"
2605                         "  .Padding_16           = 0x%04x\n",
2606                         pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2607                         pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2608                         pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2609                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2610                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2611                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2612                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2613                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2614                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2615                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2616                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2617
2618         dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2619                         "  .VoltageMode          = 0x%02x\n"
2620                         "  .SnapToDiscrete       = 0x%02x\n"
2621                         "  .NumDiscreteLevels    = 0x%02x\n"
2622                         "  .padding              = 0x%02x\n"
2623                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2624                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2625                         "  .SsFmin               = 0x%04x\n"
2626                         "  .Padding_16           = 0x%04x\n",
2627                         pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2628                         pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2629                         pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2630                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2631                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2632                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2633                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2634                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2635                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2636                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2637                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2638
2639         dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2640                         "  .VoltageMode          = 0x%02x\n"
2641                         "  .SnapToDiscrete       = 0x%02x\n"
2642                         "  .NumDiscreteLevels    = 0x%02x\n"
2643                         "  .padding              = 0x%02x\n"
2644                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2645                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2646                         "  .SsFmin               = 0x%04x\n"
2647                         "  .Padding_16           = 0x%04x\n",
2648                         pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2649                         pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2650                         pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2651                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2652                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2653                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2654                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2655                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2656                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2657                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2658                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2659
2660         dev_info(smu->adev->dev, "FreqTableGfx\n");
2661         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2662                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2663
2664         dev_info(smu->adev->dev, "FreqTableVclk\n");
2665         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2666                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2667
2668         dev_info(smu->adev->dev, "FreqTableDclk\n");
2669         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2670                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2671
2672         dev_info(smu->adev->dev, "FreqTableSocclk\n");
2673         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2674                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2675
2676         dev_info(smu->adev->dev, "FreqTableUclk\n");
2677         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2678                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2679
2680         dev_info(smu->adev->dev, "FreqTableFclk\n");
2681         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2682                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2683
2684         dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2685         dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2686         dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2687         dev_info(smu->adev->dev, "  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2688         dev_info(smu->adev->dev, "  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2689         dev_info(smu->adev->dev, "  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2690         dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2691         dev_info(smu->adev->dev, "  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2692         dev_info(smu->adev->dev, "  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2693
2694         dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2695         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2696                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2697
2698         dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2699         dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2700
2701         dev_info(smu->adev->dev, "Mp0clkFreq\n");
2702         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2703                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2704
2705         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2706         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2707                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2708
2709         dev_info(smu->adev->dev, "MemVddciVoltage\n");
2710         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2711                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2712
2713         dev_info(smu->adev->dev, "MemMvddVoltage\n");
2714         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2715                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2716
2717         dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2718         dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2719         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2720         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2721         dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2722
2723         dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2724
2725         dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2726         dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2727         dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2728         dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2729         dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2730         dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2731         dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2732         dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2733         dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2734         dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2735         dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2736
2737         dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2738         dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2739         dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2740         dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2741         dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2742         dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2743
2744         dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2745         dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2746         dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2747         dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2748         dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2749
2750         dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2751         for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2752                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2753
2754         dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2755         dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2756         dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2757         dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2758
2759         dev_info(smu->adev->dev, "UclkDpmPstates\n");
2760         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2761                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2762
2763         dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2764         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2765                 pptable->UclkDpmSrcFreqRange.Fmin);
2766         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2767                 pptable->UclkDpmSrcFreqRange.Fmax);
2768         dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2769         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2770                 pptable->UclkDpmTargFreqRange.Fmin);
2771         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2772                 pptable->UclkDpmTargFreqRange.Fmax);
2773         dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2774         dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2775
2776         dev_info(smu->adev->dev, "PcieGenSpeed\n");
2777         for (i = 0; i < NUM_LINK_LEVELS; i++)
2778                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2779
2780         dev_info(smu->adev->dev, "PcieLaneCount\n");
2781         for (i = 0; i < NUM_LINK_LEVELS; i++)
2782                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2783
2784         dev_info(smu->adev->dev, "LclkFreq\n");
2785         for (i = 0; i < NUM_LINK_LEVELS; i++)
2786                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2787
2788         dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2789         dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2790
2791         dev_info(smu->adev->dev, "FanGain\n");
2792         for (i = 0; i < TEMP_COUNT; i++)
2793                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2794
2795         dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2796         dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2797         dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2798         dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2799         dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2800         dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2801         dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2802         dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2803         dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2804         dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2805         dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2806         dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2807
2808         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2809         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2810         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2811         dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2812
2813         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2814         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2815         dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2816         dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2817
2818         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2819                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2820                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2821                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2822         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2823                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2824                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2825                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2826         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2827                         pptable->dBtcGbGfxPll.a,
2828                         pptable->dBtcGbGfxPll.b,
2829                         pptable->dBtcGbGfxPll.c);
2830         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2831                         pptable->dBtcGbGfxDfll.a,
2832                         pptable->dBtcGbGfxDfll.b,
2833                         pptable->dBtcGbGfxDfll.c);
2834         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2835                         pptable->dBtcGbSoc.a,
2836                         pptable->dBtcGbSoc.b,
2837                         pptable->dBtcGbSoc.c);
2838         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2839                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2840                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2841         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2842                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2843                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2844
2845         dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2846         for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2847                 dev_info(smu->adev->dev, "              Fset[%d] = 0x%x\n",
2848                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2849                 dev_info(smu->adev->dev, "              Vdroop[%d] = 0x%x\n",
2850                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2851         }
2852
2853         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2854                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2855                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2856                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2857         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2858                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2859                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2860                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2861
2862         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2863         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2864
2865         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2866         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2867         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2868         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2869
2870         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2871         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2872         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2873         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2874
2875         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2876         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2877
2878         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2879         for (i = 0; i < NUM_XGMI_LEVELS; i++)
2880                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2881         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2882         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2883
2884         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2885         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2886                         pptable->ReservedEquation0.a,
2887                         pptable->ReservedEquation0.b,
2888                         pptable->ReservedEquation0.c);
2889         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2890                         pptable->ReservedEquation1.a,
2891                         pptable->ReservedEquation1.b,
2892                         pptable->ReservedEquation1.c);
2893         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2894                         pptable->ReservedEquation2.a,
2895                         pptable->ReservedEquation2.b,
2896                         pptable->ReservedEquation2.c);
2897         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2898                         pptable->ReservedEquation3.a,
2899                         pptable->ReservedEquation3.b,
2900                         pptable->ReservedEquation3.c);
2901
2902         dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2903         dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2904         dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2905         dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2906         dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2907         dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2908         dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2909         dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2910
2911         dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2912         dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2913         dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2914         dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2915         dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2916         dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2917
2918         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2919                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2920                 dev_info(smu->adev->dev, "                   .Enabled = 0x%x\n",
2921                                 pptable->I2cControllers[i].Enabled);
2922                 dev_info(smu->adev->dev, "                   .Speed = 0x%x\n",
2923                                 pptable->I2cControllers[i].Speed);
2924                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
2925                                 pptable->I2cControllers[i].SlaveAddress);
2926                 dev_info(smu->adev->dev, "                   .ControllerPort = 0x%x\n",
2927                                 pptable->I2cControllers[i].ControllerPort);
2928                 dev_info(smu->adev->dev, "                   .ControllerName = 0x%x\n",
2929                                 pptable->I2cControllers[i].ControllerName);
2930                 dev_info(smu->adev->dev, "                   .ThermalThrottler = 0x%x\n",
2931                                 pptable->I2cControllers[i].ThermalThrotter);
2932                 dev_info(smu->adev->dev, "                   .I2cProtocol = 0x%x\n",
2933                                 pptable->I2cControllers[i].I2cProtocol);
2934                 dev_info(smu->adev->dev, "                   .PaddingConfig = 0x%x\n",
2935                                 pptable->I2cControllers[i].PaddingConfig);
2936         }
2937
2938         dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2939         dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2940         dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2941         dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2942
2943         dev_info(smu->adev->dev, "Board Parameters:\n");
2944         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2945         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2946         dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2947         dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2948         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2949         dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2950         dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2951         dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2952
2953         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2954         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2955         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2956
2957         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2958         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2959         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2960
2961         dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2962         dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2963         dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2964
2965         dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2966         dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2967         dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2968
2969         dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2970
2971         dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2972         dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2973         dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2974         dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2975         dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2976         dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2977         dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2978         dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2979         dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2980         dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2981         dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2982         dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2983         dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2984         dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2985         dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2986         dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2987
2988         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2989         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2990         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
2991
2992         dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2993         dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2994         dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
2995
2996         dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
2997         dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2998
2999         dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3000         dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3001         dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3002
3003         dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3004         dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3005         dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3006         dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3007         dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3008
3009         dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3010         dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3011
3012         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3013         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3014                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3015         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3016         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3017                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3018         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3019         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3020                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3021         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3022         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3023                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3024
3025         dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3026         dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3027         dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3028         dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3029
3030         dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3031         dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3032         dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3033         dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3034         dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3035         dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3036         dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3037         dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3038         dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3039         dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3040         dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3041
3042         dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3043         dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3044         dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3045         dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3046         dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3047         dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3048         dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3049         dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3050 }
3051
3052 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
3053 {
3054         struct smu_table_context *table_context = &smu->smu_table;
3055         PPTable_t *pptable = table_context->driver_pptable;
3056         int i;
3057
3058         if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) {
3059                 beige_goby_dump_pptable(smu);
3060                 return;
3061         }
3062
3063         dev_info(smu->adev->dev, "Dumped PPTable:\n");
3064
3065         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
3066         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
3067         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
3068
3069         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
3070                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
3071                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
3072                 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
3073                 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
3074         }
3075
3076         for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
3077                 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
3078                 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
3079         }
3080
3081         for (i = 0; i < TEMP_COUNT; i++) {
3082                 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
3083         }
3084
3085         dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
3086         dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
3087         dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
3088         dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
3089         dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
3090
3091         dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
3092         for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
3093                 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
3094                 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
3095         }
3096         dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
3097
3098         dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
3099
3100         dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
3101         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
3102         dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
3103         dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
3104
3105         dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
3106         dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
3107
3108         dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
3109         dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
3110         dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
3111         dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
3112
3113         dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
3114         dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
3115         dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
3116         dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
3117
3118         dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
3119         dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
3120
3121         dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
3122         dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
3123         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
3124         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
3125         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
3126         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
3127         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
3128         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
3129
3130         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
3131                         "  .VoltageMode          = 0x%02x\n"
3132                         "  .SnapToDiscrete       = 0x%02x\n"
3133                         "  .NumDiscreteLevels    = 0x%02x\n"
3134                         "  .padding              = 0x%02x\n"
3135                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3136                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3137                         "  .SsFmin               = 0x%04x\n"
3138                         "  .Padding_16           = 0x%04x\n",
3139                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
3140                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
3141                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
3142                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
3143                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
3144                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
3145                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
3146                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
3147                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
3148                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
3149                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
3150
3151         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
3152                         "  .VoltageMode          = 0x%02x\n"
3153                         "  .SnapToDiscrete       = 0x%02x\n"
3154                         "  .NumDiscreteLevels    = 0x%02x\n"
3155                         "  .padding              = 0x%02x\n"
3156                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3157                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3158                         "  .SsFmin               = 0x%04x\n"
3159                         "  .Padding_16           = 0x%04x\n",
3160                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
3161                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
3162                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
3163                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
3164                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
3165                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
3166                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
3167                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
3168                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
3169                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
3170                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
3171
3172         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
3173                         "  .VoltageMode          = 0x%02x\n"
3174                         "  .SnapToDiscrete       = 0x%02x\n"
3175                         "  .NumDiscreteLevels    = 0x%02x\n"
3176                         "  .padding              = 0x%02x\n"
3177                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3178                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3179                         "  .SsFmin               = 0x%04x\n"
3180                         "  .Padding_16           = 0x%04x\n",
3181                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
3182                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
3183                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
3184                         pptable->DpmDescriptor[PPCLK_UCLK].Padding,
3185                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
3186                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
3187                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
3188                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
3189                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
3190                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
3191                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
3192
3193         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
3194                         "  .VoltageMode          = 0x%02x\n"
3195                         "  .SnapToDiscrete       = 0x%02x\n"
3196                         "  .NumDiscreteLevels    = 0x%02x\n"
3197                         "  .padding              = 0x%02x\n"
3198                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3199                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3200                         "  .SsFmin               = 0x%04x\n"
3201                         "  .Padding_16           = 0x%04x\n",
3202                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
3203                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
3204                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
3205                         pptable->DpmDescriptor[PPCLK_FCLK].Padding,
3206                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
3207                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
3208                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
3209                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
3210                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
3211                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
3212                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
3213
3214         dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
3215                         "  .VoltageMode          = 0x%02x\n"
3216                         "  .SnapToDiscrete       = 0x%02x\n"
3217                         "  .NumDiscreteLevels    = 0x%02x\n"
3218                         "  .padding              = 0x%02x\n"
3219                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3220                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3221                         "  .SsFmin               = 0x%04x\n"
3222                         "  .Padding_16           = 0x%04x\n",
3223                         pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
3224                         pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
3225                         pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
3226                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
3227                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
3228                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
3229                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
3230                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
3231                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
3232                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
3233                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
3234
3235         dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
3236                         "  .VoltageMode          = 0x%02x\n"
3237                         "  .SnapToDiscrete       = 0x%02x\n"
3238                         "  .NumDiscreteLevels    = 0x%02x\n"
3239                         "  .padding              = 0x%02x\n"
3240                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3241                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3242                         "  .SsFmin               = 0x%04x\n"
3243                         "  .Padding_16           = 0x%04x\n",
3244                         pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
3245                         pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3246                         pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3247                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3248                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3249                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3250                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3251                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3252                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3253                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3254                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3255
3256         dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
3257                         "  .VoltageMode          = 0x%02x\n"
3258                         "  .SnapToDiscrete       = 0x%02x\n"
3259                         "  .NumDiscreteLevels    = 0x%02x\n"
3260                         "  .padding              = 0x%02x\n"
3261                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3262                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3263                         "  .SsFmin               = 0x%04x\n"
3264                         "  .Padding_16           = 0x%04x\n",
3265                         pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3266                         pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3267                         pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3268                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3269                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3270                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3271                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3272                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3273                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3274                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3275                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3276
3277         dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
3278                         "  .VoltageMode          = 0x%02x\n"
3279                         "  .SnapToDiscrete       = 0x%02x\n"
3280                         "  .NumDiscreteLevels    = 0x%02x\n"
3281                         "  .padding              = 0x%02x\n"
3282                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3283                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3284                         "  .SsFmin               = 0x%04x\n"
3285                         "  .Padding_16           = 0x%04x\n",
3286                         pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3287                         pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3288                         pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3289                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3290                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3291                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3292                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3293                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3294                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3295                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3296                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3297
3298         dev_info(smu->adev->dev, "FreqTableGfx\n");
3299         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
3300                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
3301
3302         dev_info(smu->adev->dev, "FreqTableVclk\n");
3303         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
3304                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
3305
3306         dev_info(smu->adev->dev, "FreqTableDclk\n");
3307         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
3308                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
3309
3310         dev_info(smu->adev->dev, "FreqTableSocclk\n");
3311         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
3312                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
3313
3314         dev_info(smu->adev->dev, "FreqTableUclk\n");
3315         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3316                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
3317
3318         dev_info(smu->adev->dev, "FreqTableFclk\n");
3319         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
3320                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3321
3322         dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3323         dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3324         dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3325         dev_info(smu->adev->dev, "  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3326         dev_info(smu->adev->dev, "  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3327         dev_info(smu->adev->dev, "  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3328         dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3329         dev_info(smu->adev->dev, "  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3330         dev_info(smu->adev->dev, "  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3331
3332         dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
3333         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3334                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
3335
3336         dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3337         dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
3338
3339         dev_info(smu->adev->dev, "Mp0clkFreq\n");
3340         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3341                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
3342
3343         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
3344         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3345                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
3346
3347         dev_info(smu->adev->dev, "MemVddciVoltage\n");
3348         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3349                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
3350
3351         dev_info(smu->adev->dev, "MemMvddVoltage\n");
3352         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3353                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3354
3355         dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3356         dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3357         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3358         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3359         dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3360
3361         dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3362
3363         dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3364         dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3365         dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3366         dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3367         dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3368         dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3369         dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3370         dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3371         dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3372         dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3373         dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3374
3375         dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3376         dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3377         dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3378         dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3379         dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3380         dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3381
3382         dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3383         dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3384         dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3385         dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3386         dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3387
3388         dev_info(smu->adev->dev, "FlopsPerByteTable\n");
3389         for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
3390                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
3391
3392         dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3393         dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3394         dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3395         dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
3396
3397         dev_info(smu->adev->dev, "UclkDpmPstates\n");
3398         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3399                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
3400
3401         dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3402         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
3403                 pptable->UclkDpmSrcFreqRange.Fmin);
3404         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
3405                 pptable->UclkDpmSrcFreqRange.Fmax);
3406         dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3407         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
3408                 pptable->UclkDpmTargFreqRange.Fmin);
3409         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
3410                 pptable->UclkDpmTargFreqRange.Fmax);
3411         dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3412         dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
3413
3414         dev_info(smu->adev->dev, "PcieGenSpeed\n");
3415         for (i = 0; i < NUM_LINK_LEVELS; i++)
3416                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
3417
3418         dev_info(smu->adev->dev, "PcieLaneCount\n");
3419         for (i = 0; i < NUM_LINK_LEVELS; i++)
3420                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
3421
3422         dev_info(smu->adev->dev, "LclkFreq\n");
3423         for (i = 0; i < NUM_LINK_LEVELS; i++)
3424                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
3425
3426         dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3427         dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
3428
3429         dev_info(smu->adev->dev, "FanGain\n");
3430         for (i = 0; i < TEMP_COUNT; i++)
3431                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3432
3433         dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3434         dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3435         dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3436         dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3437         dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3438         dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3439         dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3440         dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3441         dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3442         dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3443         dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3444         dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3445
3446         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3447         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3448         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3449         dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3450
3451         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3452         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3453         dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3454         dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3455
3456         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3457                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3458                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3459                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
3460         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3461                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3462                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3463                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
3464         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
3465                         pptable->dBtcGbGfxPll.a,
3466                         pptable->dBtcGbGfxPll.b,
3467                         pptable->dBtcGbGfxPll.c);
3468         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
3469                         pptable->dBtcGbGfxDfll.a,
3470                         pptable->dBtcGbGfxDfll.b,
3471                         pptable->dBtcGbGfxDfll.c);
3472         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
3473                         pptable->dBtcGbSoc.a,
3474                         pptable->dBtcGbSoc.b,
3475                         pptable->dBtcGbSoc.c);
3476         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
3477                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3478                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
3479         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
3480                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3481                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3482
3483         dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
3484         for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
3485                 dev_info(smu->adev->dev, "              Fset[%d] = 0x%x\n",
3486                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
3487                 dev_info(smu->adev->dev, "              Vdroop[%d] = 0x%x\n",
3488                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3489         }
3490
3491         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3492                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3493                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3494                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
3495         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3496                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3497                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3498                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3499
3500         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3501         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
3502
3503         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3504         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3505         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3506         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
3507
3508         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3509         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3510         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3511         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
3512
3513         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3514         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
3515
3516         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
3517         for (i = 0; i < NUM_XGMI_LEVELS; i++)
3518                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3519         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3520         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
3521
3522         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3523         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
3524                         pptable->ReservedEquation0.a,
3525                         pptable->ReservedEquation0.b,
3526                         pptable->ReservedEquation0.c);
3527         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
3528                         pptable->ReservedEquation1.a,
3529                         pptable->ReservedEquation1.b,
3530                         pptable->ReservedEquation1.c);
3531         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
3532                         pptable->ReservedEquation2.a,
3533                         pptable->ReservedEquation2.b,
3534                         pptable->ReservedEquation2.c);
3535         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
3536                         pptable->ReservedEquation3.a,
3537                         pptable->ReservedEquation3.b,
3538                         pptable->ReservedEquation3.c);
3539
3540         dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3541         dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3542         dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3543         dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3544         dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3545         dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3546         dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3547         dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
3548
3549         dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3550         dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3551         dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3552         dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3553         dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3554         dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
3555
3556         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
3557                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3558                 dev_info(smu->adev->dev, "                   .Enabled = 0x%x\n",
3559                                 pptable->I2cControllers[i].Enabled);
3560                 dev_info(smu->adev->dev, "                   .Speed = 0x%x\n",
3561                                 pptable->I2cControllers[i].Speed);
3562                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
3563                                 pptable->I2cControllers[i].SlaveAddress);
3564                 dev_info(smu->adev->dev, "                   .ControllerPort = 0x%x\n",
3565                                 pptable->I2cControllers[i].ControllerPort);
3566                 dev_info(smu->adev->dev, "                   .ControllerName = 0x%x\n",
3567                                 pptable->I2cControllers[i].ControllerName);
3568                 dev_info(smu->adev->dev, "                   .ThermalThrottler = 0x%x\n",
3569                                 pptable->I2cControllers[i].ThermalThrotter);
3570                 dev_info(smu->adev->dev, "                   .I2cProtocol = 0x%x\n",
3571                                 pptable->I2cControllers[i].I2cProtocol);
3572                 dev_info(smu->adev->dev, "                   .PaddingConfig = 0x%x\n",
3573                                 pptable->I2cControllers[i].PaddingConfig);
3574         }
3575
3576         dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3577         dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3578         dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3579         dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3580
3581         dev_info(smu->adev->dev, "Board Parameters:\n");
3582         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3583         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3584         dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3585         dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3586         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3587         dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3588         dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3589         dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3590
3591         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3592         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3593         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3594
3595         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3596         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3597         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3598
3599         dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3600         dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3601         dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3602
3603         dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3604         dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3605         dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3606
3607         dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3608
3609         dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3610         dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3611         dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3612         dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3613         dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3614         dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3615         dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3616         dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3617         dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3618         dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3619         dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3620         dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3621         dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3622         dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3623         dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3624         dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3625
3626         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3627         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3628         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
3629
3630         dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3631         dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3632         dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
3633
3634         dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3635         dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3636
3637         dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3638         dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3639         dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3640
3641         dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3642         dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3643         dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3644         dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3645         dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3646
3647         dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3648         dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3649
3650         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3651         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3652                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3653         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3654         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3655                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3656         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3657         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3658                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3659         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3660         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3661                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3662
3663         dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3664         dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3665         dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3666         dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3667
3668         dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3669         dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3670         dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3671         dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3672         dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3673         dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3674         dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3675         dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3676         dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3677         dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3678         dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3679
3680         dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3681         dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3682         dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3683         dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3684         dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3685         dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3686         dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3687         dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3688 }
3689
3690 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
3691                                    struct i2c_msg *msg, int num_msgs)
3692 {
3693         struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
3694         struct amdgpu_device *adev = smu_i2c->adev;
3695         struct smu_context *smu = adev->powerplay.pp_handle;
3696         struct smu_table_context *smu_table = &smu->smu_table;
3697         struct smu_table *table = &smu_table->driver_table;
3698         SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
3699         int i, j, r, c;
3700         u16 dir;
3701
3702         if (!adev->pm.dpm_enabled)
3703                 return -EBUSY;
3704
3705         req = kzalloc(sizeof(*req), GFP_KERNEL);
3706         if (!req)
3707                 return -ENOMEM;
3708
3709         req->I2CcontrollerPort = smu_i2c->port;
3710         req->I2CSpeed = I2C_SPEED_FAST_400K;
3711         req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
3712         dir = msg[0].flags & I2C_M_RD;
3713
3714         for (c = i = 0; i < num_msgs; i++) {
3715                 for (j = 0; j < msg[i].len; j++, c++) {
3716                         SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
3717
3718                         if (!(msg[i].flags & I2C_M_RD)) {
3719                                 /* write */
3720                                 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
3721                                 cmd->ReadWriteData = msg[i].buf[j];
3722                         }
3723
3724                         if ((dir ^ msg[i].flags) & I2C_M_RD) {
3725                                 /* The direction changes.
3726                                  */
3727                                 dir = msg[i].flags & I2C_M_RD;
3728                                 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
3729                         }
3730
3731                         req->NumCmds++;
3732
3733                         /*
3734                          * Insert STOP if we are at the last byte of either last
3735                          * message for the transaction or the client explicitly
3736                          * requires a STOP at this particular message.
3737                          */
3738                         if ((j == msg[i].len - 1) &&
3739                             ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3740                                 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
3741                                 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
3742                         }
3743                 }
3744         }
3745         mutex_lock(&adev->pm.mutex);
3746         r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
3747         mutex_unlock(&adev->pm.mutex);
3748         if (r)
3749                 goto fail;
3750
3751         for (c = i = 0; i < num_msgs; i++) {
3752                 if (!(msg[i].flags & I2C_M_RD)) {
3753                         c += msg[i].len;
3754                         continue;
3755                 }
3756                 for (j = 0; j < msg[i].len; j++, c++) {
3757                         SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
3758
3759                         msg[i].buf[j] = cmd->ReadWriteData;
3760                 }
3761         }
3762         r = num_msgs;
3763 fail:
3764         kfree(req);
3765         return r;
3766 }
3767
3768 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
3769 {
3770         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3771 }
3772
3773
3774 static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
3775         .master_xfer = sienna_cichlid_i2c_xfer,
3776         .functionality = sienna_cichlid_i2c_func,
3777 };
3778
3779 static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
3780         .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
3781         .max_read_len  = MAX_SW_I2C_COMMANDS,
3782         .max_write_len = MAX_SW_I2C_COMMANDS,
3783         .max_comb_1st_msg_len = 2,
3784         .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
3785 };
3786
3787 static int sienna_cichlid_i2c_control_init(struct smu_context *smu)
3788 {
3789         struct amdgpu_device *adev = smu->adev;
3790         int res, i;
3791
3792         for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3793                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3794                 struct i2c_adapter *control = &smu_i2c->adapter;
3795
3796                 smu_i2c->adev = adev;
3797                 smu_i2c->port = i;
3798                 mutex_init(&smu_i2c->mutex);
3799                 control->owner = THIS_MODULE;
3800                 control->class = I2C_CLASS_HWMON;
3801                 control->dev.parent = &adev->pdev->dev;
3802                 control->algo = &sienna_cichlid_i2c_algo;
3803                 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
3804                 control->quirks = &sienna_cichlid_i2c_control_quirks;
3805                 i2c_set_adapdata(control, smu_i2c);
3806
3807                 res = i2c_add_adapter(control);
3808                 if (res) {
3809                         DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3810                         goto Out_err;
3811                 }
3812         }
3813         /* assign the buses used for the FRU EEPROM and RAS EEPROM */
3814         /* XXX ideally this would be something in a vbios data table */
3815         adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
3816         adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
3817
3818         return 0;
3819 Out_err:
3820         for ( ; i >= 0; i--) {
3821                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3822                 struct i2c_adapter *control = &smu_i2c->adapter;
3823
3824                 i2c_del_adapter(control);
3825         }
3826         return res;
3827 }
3828
3829 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu)
3830 {
3831         struct amdgpu_device *adev = smu->adev;
3832         int i;
3833
3834         for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3835                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3836                 struct i2c_adapter *control = &smu_i2c->adapter;
3837
3838                 i2c_del_adapter(control);
3839         }
3840         adev->pm.ras_eeprom_i2c_bus = NULL;
3841         adev->pm.fru_eeprom_i2c_bus = NULL;
3842 }
3843
3844 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3845                                               void **table)
3846 {
3847         struct smu_table_context *smu_table = &smu->smu_table;
3848         struct gpu_metrics_v1_3 *gpu_metrics =
3849                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3850         SmuMetricsExternal_t metrics_external;
3851         SmuMetrics_t *metrics =
3852                 &(metrics_external.SmuMetrics);
3853         SmuMetrics_V2_t *metrics_v2 =
3854                 &(metrics_external.SmuMetrics_V2);
3855         SmuMetrics_V3_t *metrics_v3 =
3856                 &(metrics_external.SmuMetrics_V3);
3857         struct amdgpu_device *adev = smu->adev;
3858         bool use_metrics_v2 = false;
3859         bool use_metrics_v3 = false;
3860         uint16_t average_gfx_activity;
3861         int ret = 0;
3862
3863         switch (smu->adev->ip_versions[MP1_HWIP][0]) {
3864         case IP_VERSION(11, 0, 7):
3865                 if (smu->smc_fw_version >= 0x3A4900)
3866                         use_metrics_v3 = true;
3867                 else if (smu->smc_fw_version >= 0x3A4300)
3868                         use_metrics_v2 = true;
3869                 break;
3870         case IP_VERSION(11, 0, 11):
3871                 if (smu->smc_fw_version >= 0x412D00)
3872                         use_metrics_v2 = true;
3873                 break;
3874         case IP_VERSION(11, 0, 12):
3875                 if (smu->smc_fw_version >= 0x3B2300)
3876                         use_metrics_v2 = true;
3877                 break;
3878         case IP_VERSION(11, 0, 13):
3879                 if (smu->smc_fw_version >= 0x491100)
3880                         use_metrics_v2 = true;
3881                 break;
3882         default:
3883                 break;
3884         }
3885
3886         ret = smu_cmn_get_metrics_table(smu,
3887                                         &metrics_external,
3888                                         true);
3889         if (ret)
3890                 return ret;
3891
3892         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3893
3894         gpu_metrics->temperature_edge = use_metrics_v3 ? metrics_v3->TemperatureEdge :
3895                 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge;
3896         gpu_metrics->temperature_hotspot = use_metrics_v3 ? metrics_v3->TemperatureHotspot :
3897                 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot;
3898         gpu_metrics->temperature_mem = use_metrics_v3 ? metrics_v3->TemperatureMem :
3899                 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem;
3900         gpu_metrics->temperature_vrgfx = use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
3901                 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx;
3902         gpu_metrics->temperature_vrsoc = use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
3903                 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc;
3904         gpu_metrics->temperature_vrmem = use_metrics_v3 ? metrics_v3->TemperatureVrMem0 :
3905                 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0;
3906
3907         gpu_metrics->average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
3908                 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3909         gpu_metrics->average_umc_activity = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
3910                 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity;
3911         gpu_metrics->average_mm_activity = use_metrics_v3 ?
3912                 (metrics_v3->VcnUsagePercentage0 + metrics_v3->VcnUsagePercentage1) / 2 :
3913                 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage;
3914
3915         gpu_metrics->average_socket_power = use_metrics_v3 ? metrics_v3->AverageSocketPower :
3916                 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower;
3917         gpu_metrics->energy_accumulator = use_metrics_v3 ? metrics_v3->EnergyAccumulator :
3918                 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator;
3919
3920         if (metrics->CurrGfxVoltageOffset)
3921                 gpu_metrics->voltage_gfx =
3922                         (155000 - 625 * metrics->CurrGfxVoltageOffset) / 100;
3923         if (metrics->CurrMemVidOffset)
3924                 gpu_metrics->voltage_mem =
3925                         (155000 - 625 * metrics->CurrMemVidOffset) / 100;
3926         if (metrics->CurrSocVoltageOffset)
3927                 gpu_metrics->voltage_soc =
3928                         (155000 - 625 * metrics->CurrSocVoltageOffset) / 100;
3929
3930         average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
3931                 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3932         if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
3933                 gpu_metrics->average_gfxclk_frequency =
3934                         use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
3935                         use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
3936                         metrics->AverageGfxclkFrequencyPostDs;
3937         else
3938                 gpu_metrics->average_gfxclk_frequency =
3939                         use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
3940                         use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
3941                         metrics->AverageGfxclkFrequencyPreDs;
3942
3943         gpu_metrics->average_uclk_frequency =
3944                 use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
3945                 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
3946                 metrics->AverageUclkFrequencyPostDs;
3947         gpu_metrics->average_vclk0_frequency = use_metrics_v3 ? metrics_v3->AverageVclk0Frequency :
3948                 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency;
3949         gpu_metrics->average_dclk0_frequency = use_metrics_v3 ? metrics_v3->AverageDclk0Frequency :
3950                 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency;
3951         gpu_metrics->average_vclk1_frequency = use_metrics_v3 ? metrics_v3->AverageVclk1Frequency :
3952                 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency;
3953         gpu_metrics->average_dclk1_frequency = use_metrics_v3 ? metrics_v3->AverageDclk1Frequency :
3954                 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency;
3955
3956         gpu_metrics->current_gfxclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
3957                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK];
3958         gpu_metrics->current_socclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
3959                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK];
3960         gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
3961                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];
3962         gpu_metrics->current_vclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
3963                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0];
3964         gpu_metrics->current_dclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
3965                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0];
3966         gpu_metrics->current_vclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
3967                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1];
3968         gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
3969                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1];
3970
3971         gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu);
3972         gpu_metrics->indep_throttle_status =
3973                         smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
3974                                                            sienna_cichlid_throttler_map);
3975
3976         gpu_metrics->current_fan_speed = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
3977                 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
3978
3979         if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
3980               ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
3981                 gpu_metrics->pcie_link_width = use_metrics_v3 ? metrics_v3->PcieWidth :
3982                         use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
3983                 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v3 ? metrics_v3->PcieRate :
3984                         use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
3985         } else {
3986                 gpu_metrics->pcie_link_width =
3987                                 smu_v11_0_get_current_pcie_link_width(smu);
3988                 gpu_metrics->pcie_link_speed =
3989                                 smu_v11_0_get_current_pcie_link_speed(smu);
3990         }
3991
3992         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3993
3994         *table = (void *)gpu_metrics;
3995
3996         return sizeof(struct gpu_metrics_v1_3);
3997 }
3998
3999 static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu)
4000 {
4001         uint32_t if_version = 0xff, smu_version = 0xff;
4002         int ret = 0;
4003
4004         ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
4005         if (ret)
4006                 return -EOPNOTSUPP;
4007
4008         if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION)
4009                 ret = -EOPNOTSUPP;
4010
4011         return ret;
4012 }
4013
4014 static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu,
4015                                         void *table)
4016 {
4017         struct smu_table_context *smu_table = &smu->smu_table;
4018         EccInfoTable_t *ecc_table = NULL;
4019         struct ecc_info_per_ch *ecc_info_per_channel = NULL;
4020         int i, ret = 0;
4021         struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
4022
4023         ret = sienna_cichlid_check_ecc_table_support(smu);
4024         if (ret)
4025                 return ret;
4026
4027         ret = smu_cmn_update_table(smu,
4028                                 SMU_TABLE_ECCINFO,
4029                                 0,
4030                                 smu_table->ecc_table,
4031                                 false);
4032         if (ret) {
4033                 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
4034                 return ret;
4035         }
4036
4037         ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
4038
4039         for (i = 0; i < SIENNA_CICHLID_UMC_CHANNEL_NUM; i++) {
4040                 ecc_info_per_channel = &(eccinfo->ecc[i]);
4041                 ecc_info_per_channel->ce_count_lo_chip =
4042                         ecc_table->EccInfo[i].ce_count_lo_chip;
4043                 ecc_info_per_channel->ce_count_hi_chip =
4044                         ecc_table->EccInfo[i].ce_count_hi_chip;
4045                 ecc_info_per_channel->mca_umc_status =
4046                         ecc_table->EccInfo[i].mca_umc_status;
4047                 ecc_info_per_channel->mca_umc_addr =
4048                         ecc_table->EccInfo[i].mca_umc_addr;
4049         }
4050
4051         return ret;
4052 }
4053 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
4054 {
4055         uint16_t *mgpu_fan_boost_limit_rpm;
4056
4057         GET_PPTABLE_MEMBER(MGpuFanBoostLimitRpm, &mgpu_fan_boost_limit_rpm);
4058         /*
4059          * Skip the MGpuFanBoost setting for those ASICs
4060          * which do not support it
4061          */
4062         if (*mgpu_fan_boost_limit_rpm == 0)
4063                 return 0;
4064
4065         return smu_cmn_send_smc_msg_with_param(smu,
4066                                                SMU_MSG_SetMGpuFanBoostLimitRpm,
4067                                                0,
4068                                                NULL);
4069 }
4070
4071 static int sienna_cichlid_gpo_control(struct smu_context *smu,
4072                                       bool enablement)
4073 {
4074         uint32_t smu_version;
4075         int ret = 0;
4076
4077
4078         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
4079                 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
4080                 if (ret)
4081                         return ret;
4082
4083                 if (enablement) {
4084                         if (smu_version < 0x003a2500) {
4085                                 ret = smu_cmn_send_smc_msg_with_param(smu,
4086                                                                       SMU_MSG_SetGpoFeaturePMask,
4087                                                                       GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
4088                                                                       NULL);
4089                         } else {
4090                                 ret = smu_cmn_send_smc_msg_with_param(smu,
4091                                                                       SMU_MSG_DisallowGpo,
4092                                                                       0,
4093                                                                       NULL);
4094                         }
4095                 } else {
4096                         if (smu_version < 0x003a2500) {
4097                                 ret = smu_cmn_send_smc_msg_with_param(smu,
4098                                                                       SMU_MSG_SetGpoFeaturePMask,
4099                                                                       0,
4100                                                                       NULL);
4101                         } else {
4102                                 ret = smu_cmn_send_smc_msg_with_param(smu,
4103                                                                       SMU_MSG_DisallowGpo,
4104                                                                       1,
4105                                                                       NULL);
4106                         }
4107                 }
4108         }
4109
4110         return ret;
4111 }
4112
4113 static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
4114 {
4115         uint32_t smu_version;
4116         int ret = 0;
4117
4118         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
4119         if (ret)
4120                 return ret;
4121
4122         /*
4123          * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
4124          * onwards PMFWs.
4125          */
4126         if (smu_version < 0x003A2D00)
4127                 return 0;
4128
4129         return smu_cmn_send_smc_msg_with_param(smu,
4130                                                SMU_MSG_Enable2ndUSB20Port,
4131                                                smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
4132                                                1 : 0,
4133                                                NULL);
4134 }
4135
4136 static int sienna_cichlid_system_features_control(struct smu_context *smu,
4137                                                   bool en)
4138 {
4139         int ret = 0;
4140
4141         if (en) {
4142                 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
4143                 if (ret)
4144                         return ret;
4145         }
4146
4147         return smu_v11_0_system_features_control(smu, en);
4148 }
4149
4150 static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
4151                                         enum pp_mp1_state mp1_state)
4152 {
4153         int ret;
4154
4155         switch (mp1_state) {
4156         case PP_MP1_STATE_UNLOAD:
4157                 ret = smu_cmn_set_mp1_state(smu, mp1_state);
4158                 break;
4159         default:
4160                 /* Ignore others */
4161                 ret = 0;
4162         }
4163
4164         return ret;
4165 }
4166
4167 static void sienna_cichlid_stb_init(struct smu_context *smu)
4168 {
4169         struct amdgpu_device *adev = smu->adev;
4170         uint32_t reg;
4171
4172         reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START);
4173         smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE);
4174
4175         /* STB is disabled */
4176         if (!smu->stb_context.enabled)
4177                 return;
4178
4179         spin_lock_init(&smu->stb_context.lock);
4180
4181         /* STB buffer size in bytes as function of FIFO depth */
4182         reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO);
4183         smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH);
4184         smu->stb_context.stb_buf_size *=  SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES;
4185
4186         dev_info(smu->adev->dev, "STB initialized to %d entries",
4187                  smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES);
4188
4189 }
4190
4191 static int sienna_cichlid_get_default_config_table_settings(struct smu_context *smu,
4192                                                             struct config_table_setting *table)
4193 {
4194         struct amdgpu_device *adev = smu->adev;
4195
4196         if (!table)
4197                 return -EINVAL;
4198
4199         table->gfxclk_average_tau = 10;
4200         table->socclk_average_tau = 10;
4201         table->fclk_average_tau = 10;
4202         table->uclk_average_tau = 10;
4203         table->gfx_activity_average_tau = 10;
4204         table->mem_activity_average_tau = 10;
4205         table->socket_power_average_tau = 100;
4206         if (adev->asic_type != CHIP_SIENNA_CICHLID)
4207                 table->apu_socket_power_average_tau = 100;
4208
4209         return 0;
4210 }
4211
4212 static int sienna_cichlid_set_config_table(struct smu_context *smu,
4213                                            struct config_table_setting *table)
4214 {
4215         DriverSmuConfigExternal_t driver_smu_config_table;
4216
4217         if (!table)
4218                 return -EINVAL;
4219
4220         memset(&driver_smu_config_table,
4221                0,
4222                sizeof(driver_smu_config_table));
4223         driver_smu_config_table.DriverSmuConfig.GfxclkAverageLpfTau =
4224                                 table->gfxclk_average_tau;
4225         driver_smu_config_table.DriverSmuConfig.FclkAverageLpfTau =
4226                                 table->fclk_average_tau;
4227         driver_smu_config_table.DriverSmuConfig.UclkAverageLpfTau =
4228                                 table->uclk_average_tau;
4229         driver_smu_config_table.DriverSmuConfig.GfxActivityLpfTau =
4230                                 table->gfx_activity_average_tau;
4231         driver_smu_config_table.DriverSmuConfig.UclkActivityLpfTau =
4232                                 table->mem_activity_average_tau;
4233         driver_smu_config_table.DriverSmuConfig.SocketPowerLpfTau =
4234                                 table->socket_power_average_tau;
4235
4236         return smu_cmn_update_table(smu,
4237                                     SMU_TABLE_DRIVER_SMU_CONFIG,
4238                                     0,
4239                                     (void *)&driver_smu_config_table,
4240                                     true);
4241 }
4242
4243 static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu,
4244                                               void *buf,
4245                                               uint32_t size)
4246 {
4247         uint32_t *p = buf;
4248         struct amdgpu_device *adev = smu->adev;
4249
4250         /* No need to disable interrupts for now as we don't lock it yet from ISR */
4251         spin_lock(&smu->stb_context.lock);
4252
4253         /*
4254          * Read the STB FIFO in units of 32bit since this is the accessor window
4255          * (register width) we have.
4256          */
4257         buf = ((char *) buf) + size;
4258         while ((void *)p < buf)
4259                 *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3));
4260
4261         spin_unlock(&smu->stb_context.lock);
4262
4263         return 0;
4264 }
4265
4266 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
4267         .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
4268         .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
4269         .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
4270         .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
4271         .i2c_init = sienna_cichlid_i2c_control_init,
4272         .i2c_fini = sienna_cichlid_i2c_control_fini,
4273         .print_clk_levels = sienna_cichlid_print_clk_levels,
4274         .force_clk_levels = sienna_cichlid_force_clk_levels,
4275         .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
4276         .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
4277         .display_config_changed = sienna_cichlid_display_config_changed,
4278         .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
4279         .is_dpm_running = sienna_cichlid_is_dpm_running,
4280         .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
4281         .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
4282         .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
4283         .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
4284         .set_watermarks_table = sienna_cichlid_set_watermarks_table,
4285         .read_sensor = sienna_cichlid_read_sensor,
4286         .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
4287         .set_performance_level = smu_v11_0_set_performance_level,
4288         .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
4289         .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
4290         .get_power_limit = sienna_cichlid_get_power_limit,
4291         .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
4292         .dump_pptable = sienna_cichlid_dump_pptable,
4293         .init_microcode = smu_v11_0_init_microcode,
4294         .load_microcode = smu_v11_0_load_microcode,
4295         .fini_microcode = smu_v11_0_fini_microcode,
4296         .init_smc_tables = sienna_cichlid_init_smc_tables,
4297         .fini_smc_tables = smu_v11_0_fini_smc_tables,
4298         .init_power = smu_v11_0_init_power,
4299         .fini_power = smu_v11_0_fini_power,
4300         .check_fw_status = smu_v11_0_check_fw_status,
4301         .setup_pptable = sienna_cichlid_setup_pptable,
4302         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
4303         .check_fw_version = smu_v11_0_check_fw_version,
4304         .write_pptable = smu_cmn_write_pptable,
4305         .set_driver_table_location = smu_v11_0_set_driver_table_location,
4306         .set_tool_table_location = smu_v11_0_set_tool_table_location,
4307         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
4308         .system_features_control = sienna_cichlid_system_features_control,
4309         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
4310         .send_smc_msg = smu_cmn_send_smc_msg,
4311         .init_display_count = NULL,
4312         .set_allowed_mask = smu_v11_0_set_allowed_mask,
4313         .get_enabled_mask = smu_cmn_get_enabled_mask,
4314         .feature_is_enabled = smu_cmn_feature_is_enabled,
4315         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
4316         .notify_display_change = NULL,
4317         .set_power_limit = smu_v11_0_set_power_limit,
4318         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
4319         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
4320         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
4321         .set_min_dcef_deep_sleep = NULL,
4322         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
4323         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
4324         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
4325         .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
4326         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
4327         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
4328         .gfx_off_control = smu_v11_0_gfx_off_control,
4329         .register_irq_handler = smu_v11_0_register_irq_handler,
4330         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
4331         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
4332         .baco_is_support = smu_v11_0_baco_is_support,
4333         .baco_get_state = smu_v11_0_baco_get_state,
4334         .baco_set_state = smu_v11_0_baco_set_state,
4335         .baco_enter = sienna_cichlid_baco_enter,
4336         .baco_exit = sienna_cichlid_baco_exit,
4337         .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
4338         .mode1_reset = smu_v11_0_mode1_reset,
4339         .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
4340         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
4341         .set_default_od_settings = sienna_cichlid_set_default_od_settings,
4342         .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
4343         .restore_user_od_settings = smu_v11_0_restore_user_od_settings,
4344         .run_btc = sienna_cichlid_run_btc,
4345         .set_power_source = smu_v11_0_set_power_source,
4346         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
4347         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
4348         .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
4349         .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
4350         .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
4351         .deep_sleep_control = smu_v11_0_deep_sleep_control,
4352         .get_fan_parameters = sienna_cichlid_get_fan_parameters,
4353         .interrupt_work = smu_v11_0_interrupt_work,
4354         .gpo_control = sienna_cichlid_gpo_control,
4355         .set_mp1_state = sienna_cichlid_set_mp1_state,
4356         .stb_collect_info = sienna_cichlid_stb_get_data_direct,
4357         .get_ecc_info = sienna_cichlid_get_ecc_info,
4358         .get_default_config_table_settings = sienna_cichlid_get_default_config_table_settings,
4359         .set_config_table = sienna_cichlid_set_config_table,
4360         .get_unique_id = sienna_cichlid_get_unique_id,
4361 };
4362
4363 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
4364 {
4365         smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
4366         smu->message_map = sienna_cichlid_message_map;
4367         smu->clock_map = sienna_cichlid_clk_map;
4368         smu->feature_map = sienna_cichlid_feature_mask_map;
4369         smu->table_map = sienna_cichlid_table_map;
4370         smu->pwr_src_map = sienna_cichlid_pwr_src_map;
4371         smu->workload_map = sienna_cichlid_workload_map;
4372 }