git.itanic.dy.fi Git - linux-stable/blob - drivers/gpu/drm/i915/display/intel_psr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <drm/drm_atomic_helper.h>
  25 #include <drm/drm_damage_helper.h>
  26
  27 #include "display/intel_dp.h"
  28
  29 #include "i915_drv.h"
  30 #include "intel_atomic.h"
  31 #include "intel_crtc.h"
  32 #include "intel_de.h"
  33 #include "intel_display_types.h"
  34 #include "intel_dp_aux.h"
  35 #include "intel_hdmi.h"
  36 #include "intel_psr.h"
  37 #include "intel_snps_phy.h"
  38 #include "skl_universal_plane.h"
  39
  40 /**
  41  * DOC: Panel Self Refresh (PSR/SRD)
  42  *
  43  * Since Haswell Display controller supports Panel Self-Refresh on display
  44  * panels witch have a remote frame buffer (RFB) implemented according to PSR
  45  * spec in eDP1.3. PSR feature allows the display to go to lower standby states
  46  * when system is idle but display is on as it eliminates display refresh
  47  * request to DDR memory completely as long as the frame buffer for that
  48  * display is unchanged.
  49  *
  50  * Panel Self Refresh must be supported by both Hardware (source) and
  51  * Panel (sink).
  52  *
  53  * PSR saves power by caching the framebuffer in the panel RFB, which allows us
  54  * to power down the link and memory controller. For DSI panels the same idea
  55  * is called "manual mode".
  56  *
  57  * The implementation uses the hardware-based PSR support which automatically
  58  * enters/exits self-refresh mode. The hardware takes care of sending the
  59  * required DP aux message and could even retrain the link (that part isn't
  60  * enabled yet though). The hardware also keeps track of any frontbuffer
  61  * changes to know when to exit self-refresh mode again. Unfortunately that
  62  * part doesn't work too well, hence why the i915 PSR support uses the
  63  * software frontbuffer tracking to make sure it doesn't miss a screen
  64  * update. For this integration intel_psr_invalidate() and intel_psr_flush()
  65  * get called by the frontbuffer tracking code. Note that because of locking
  66  * issues the self-refresh re-enable code is done from a work queue, which
  67  * must be correctly synchronized/cancelled when shutting down the pipe."
  68  *
  69  * DC3CO (DC3 clock off)
  70  *
  71  * On top of PSR2, GEN12 adds a intermediate power savings state that turns
  72  * clock off automatically during PSR2 idle state.
  73  * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep
  74  * entry/exit allows the HW to enter a low-power state even when page flipping
  75  * periodically (for instance a 30fps video playback scenario).
  76  *
  77  * Every time a flips occurs PSR2 will get out of deep sleep state(if it was),
  78  * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6
  79  * frames, if no other flip occurs and the function above is executed, DC3CO is
  80  * disabled and PSR2 is configured to enter deep sleep, resetting again in case
  81  * of another flip.
  82  * Front buffer modifications do not trigger DC3CO activation on purpose as it
  83  * would bring a lot of complexity and most of the moderns systems will only
  84  * use page flips.
  85  */
  86
  87 static bool psr_global_enabled(struct intel_dp *intel_dp)
  88 {
  89         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
  90
  91         switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
  92         case I915_PSR_DEBUG_DEFAULT:
  93                 return i915->params.enable_psr;
  94         case I915_PSR_DEBUG_DISABLE:
  95                 return false;
  96         default:
  97                 return true;
  98         }
  99 }
 100
 101 static bool psr2_global_enabled(struct intel_dp *intel_dp)
 102 {
 103         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 104
 105         switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
 106         case I915_PSR_DEBUG_DISABLE:
 107         case I915_PSR_DEBUG_FORCE_PSR1:
 108                 return false;
 109         default:
 110                 if (i915->params.enable_psr == 1)
 111                         return false;
 112                 return true;
 113         }
 114 }
 115
 116 static void psr_irq_control(struct intel_dp *intel_dp)
 117 {
 118         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 119         enum transcoder trans_shift;
 120         i915_reg_t imr_reg;
 121         u32 mask, val;
 122
 123         /*
 124          * gen12+ has registers relative to transcoder and one per transcoder
 125          * using the same bit definition: handle it as TRANSCODER_EDP to force
 126          * 0 shift in bit definition
 127          */
 128         if (DISPLAY_VER(dev_priv) >= 12) {
 129                 trans_shift = 0;
 130                 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
 131         } else {
 132                 trans_shift = intel_dp->psr.transcoder;
 133                 imr_reg = EDP_PSR_IMR;
 134         }
 135
 136         mask = EDP_PSR_ERROR(trans_shift);
 137         if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
 138                 mask |= EDP_PSR_POST_EXIT(trans_shift) |
 139                         EDP_PSR_PRE_ENTRY(trans_shift);
 140
 141         /* Warning: it is masking/setting reserved bits too */
 142         val = intel_de_read(dev_priv, imr_reg);
 143         val &= ~EDP_PSR_TRANS_MASK(trans_shift);
 144         val |= ~mask;
 145         intel_de_write(dev_priv, imr_reg, val);
 146 }
 147
 148 static void psr_event_print(struct drm_i915_private *i915,
 149                             u32 val, bool psr2_enabled)
 150 {
 151         drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val);
 152         if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE)
 153                 drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n");
 154         if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled)
 155                 drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n");
 156         if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN)
 157                 drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n");
 158         if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN)
 159                 drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n");
 160         if (val & PSR_EVENT_GRAPHICS_RESET)
 161                 drm_dbg_kms(&i915->drm, "\tGraphics reset\n");
 162         if (val & PSR_EVENT_PCH_INTERRUPT)
 163                 drm_dbg_kms(&i915->drm, "\tPCH interrupt\n");
 164         if (val & PSR_EVENT_MEMORY_UP)
 165                 drm_dbg_kms(&i915->drm, "\tMemory up\n");
 166         if (val & PSR_EVENT_FRONT_BUFFER_MODIFY)
 167                 drm_dbg_kms(&i915->drm, "\tFront buffer modification\n");
 168         if (val & PSR_EVENT_WD_TIMER_EXPIRE)
 169                 drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n");
 170         if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE)
 171                 drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n");
 172         if (val & PSR_EVENT_REGISTER_UPDATE)
 173                 drm_dbg_kms(&i915->drm, "\tRegister updated\n");
 174         if (val & PSR_EVENT_HDCP_ENABLE)
 175                 drm_dbg_kms(&i915->drm, "\tHDCP enabled\n");
 176         if (val & PSR_EVENT_KVMR_SESSION_ENABLE)
 177                 drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n");
 178         if (val & PSR_EVENT_VBI_ENABLE)
 179                 drm_dbg_kms(&i915->drm, "\tVBI enabled\n");
 180         if (val & PSR_EVENT_LPSP_MODE_EXIT)
 181                 drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n");
 182         if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled)
 183                 drm_dbg_kms(&i915->drm, "\tPSR disabled\n");
 184 }
 185
 186 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
 187 {
 188         enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
 189         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 190         ktime_t time_ns =  ktime_get();
 191         enum transcoder trans_shift;
 192         i915_reg_t imr_reg;
 193
 194         if (DISPLAY_VER(dev_priv) >= 12) {
 195                 trans_shift = 0;
 196                 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
 197         } else {
 198                 trans_shift = intel_dp->psr.transcoder;
 199                 imr_reg = EDP_PSR_IMR;
 200         }
 201
 202         if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) {
 203                 intel_dp->psr.last_entry_attempt = time_ns;
 204                 drm_dbg_kms(&dev_priv->drm,
 205                             "[transcoder %s] PSR entry attempt in 2 vblanks\n",
 206                             transcoder_name(cpu_transcoder));
 207         }
 208
 209         if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) {
 210                 intel_dp->psr.last_exit = time_ns;
 211                 drm_dbg_kms(&dev_priv->drm,
 212                             "[transcoder %s] PSR exit completed\n",
 213                             transcoder_name(cpu_transcoder));
 214
 215                 if (DISPLAY_VER(dev_priv) >= 9) {
 216                         u32 val = intel_de_read(dev_priv,
 217                                                 PSR_EVENT(cpu_transcoder));
 218                         bool psr2_enabled = intel_dp->psr.psr2_enabled;
 219
 220                         intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder),
 221                                        val);
 222                         psr_event_print(dev_priv, val, psr2_enabled);
 223                 }
 224         }
 225
 226         if (psr_iir & EDP_PSR_ERROR(trans_shift)) {
 227                 u32 val;
 228
 229                 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n",
 230                          transcoder_name(cpu_transcoder));
 231
 232                 intel_dp->psr.irq_aux_error = true;
 233
 234                 /*
 235                  * If this interruption is not masked it will keep
 236                  * interrupting so fast that it prevents the scheduled
 237                  * work to run.
 238                  * Also after a PSR error, we don't want to arm PSR
 239                  * again so we don't care about unmask the interruption
 240                  * or unset irq_aux_error.
 241                  */
 242                 val = intel_de_read(dev_priv, imr_reg);
 243                 val |= EDP_PSR_ERROR(trans_shift);
 244                 intel_de_write(dev_priv, imr_reg, val);
 245
 246                 schedule_work(&intel_dp->psr.work);
 247         }
 248 }
 249
 250 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
 251 {
 252         u8 alpm_caps = 0;
 253
 254         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
 255                               &alpm_caps) != 1)
 256                 return false;
 257         return alpm_caps & DP_ALPM_CAP;
 258 }
 259
 260 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
 261 {
 262         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 263         u8 val = 8; /* assume the worst if we can't read the value */
 264
 265         if (drm_dp_dpcd_readb(&intel_dp->aux,
 266                               DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1)
 267                 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
 268         else
 269                 drm_dbg_kms(&i915->drm,
 270                             "Unable to get sink synchronization latency, assuming 8 frames\n");
 271         return val;
 272 }
 273
 274 static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
 275 {
 276         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 277         ssize_t r;
 278         u16 w;
 279         u8 y;
 280
 281         /* If sink don't have specific granularity requirements set legacy ones */
 282         if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
 283                 /* As PSR2 HW sends full lines, we do not care about x granularity */
 284                 w = 4;
 285                 y = 4;
 286                 goto exit;
 287         }
 288
 289         r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2);
 290         if (r != 2)
 291                 drm_dbg_kms(&i915->drm,
 292                             "Unable to read DP_PSR2_SU_X_GRANULARITY\n");
 293         /*
 294          * Spec says that if the value read is 0 the default granularity should
 295          * be used instead.
 296          */
 297         if (r != 2 || w == 0)
 298                 w = 4;
 299
 300         r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1);
 301         if (r != 1) {
 302                 drm_dbg_kms(&i915->drm,
 303                             "Unable to read DP_PSR2_SU_Y_GRANULARITY\n");
 304                 y = 4;
 305         }
 306         if (y == 0)
 307                 y = 1;
 308
 309 exit:
 310         intel_dp->psr.su_w_granularity = w;
 311         intel_dp->psr.su_y_granularity = y;
 312 }
 313
 314 void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 315 {
 316         struct drm_i915_private *dev_priv =
 317                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
 318
 319         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
 320                          sizeof(intel_dp->psr_dpcd));
 321
 322         if (!intel_dp->psr_dpcd[0])
 323                 return;
 324         drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n",
 325                     intel_dp->psr_dpcd[0]);
 326
 327         if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
 328                 drm_dbg_kms(&dev_priv->drm,
 329                             "PSR support not currently available for this panel\n");
 330                 return;
 331         }
 332
 333         if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
 334                 drm_dbg_kms(&dev_priv->drm,
 335                             "Panel lacks power state control, PSR cannot be enabled\n");
 336                 return;
 337         }
 338
 339         intel_dp->psr.sink_support = true;
 340         intel_dp->psr.sink_sync_latency =
 341                 intel_dp_get_sink_sync_latency(intel_dp);
 342
 343         if (DISPLAY_VER(dev_priv) >= 9 &&
 344             (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
 345                 bool y_req = intel_dp->psr_dpcd[1] &
 346                              DP_PSR2_SU_Y_COORDINATE_REQUIRED;
 347                 bool alpm = intel_dp_get_alpm_status(intel_dp);
 348
 349                 /*
 350                  * All panels that supports PSR version 03h (PSR2 +
 351                  * Y-coordinate) can handle Y-coordinates in VSC but we are
 352                  * only sure that it is going to be used when required by the
 353                  * panel. This way panel is capable to do selective update
 354                  * without a aux frame sync.
 355                  *
 356                  * To support PSR version 02h and PSR version 03h without
 357                  * Y-coordinate requirement panels we would need to enable
 358                  * GTC first.
 359                  */
 360                 intel_dp->psr.sink_psr2_support = y_req && alpm;
 361                 drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n",
 362                             intel_dp->psr.sink_psr2_support ? "" : "not ");
 363
 364                 if (intel_dp->psr.sink_psr2_support) {
 365                         intel_dp->psr.colorimetry_support =
 366                                 intel_dp_get_colorimetry_status(intel_dp);
 367                         intel_dp_get_su_granularity(intel_dp);
 368                 }
 369         }
 370 }
 371
 372 static void intel_psr_enable_sink(struct intel_dp *intel_dp)
 373 {
 374         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 375         u8 dpcd_val = DP_PSR_ENABLE;
 376
 377         /* Enable ALPM at sink for psr2 */
 378         if (intel_dp->psr.psr2_enabled) {
 379                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
 380                                    DP_ALPM_ENABLE |
 381                                    DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
 382
 383                 dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
 384         } else {
 385                 if (intel_dp->psr.link_standby)
 386                         dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
 387
 388                 if (DISPLAY_VER(dev_priv) >= 8)
 389                         dpcd_val |= DP_PSR_CRC_VERIFICATION;
 390         }
 391
 392         if (intel_dp->psr.req_psr2_sdp_prior_scanline)
 393                 dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE;
 394
 395         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
 396
 397         drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
 398 }
 399
 400 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
 401 {
 402         struct intel_connector *connector = intel_dp->attached_connector;
 403         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 404         u32 val = 0;
 405
 406         if (DISPLAY_VER(dev_priv) >= 11)
 407                 val |= EDP_PSR_TP4_TIME_0US;
 408
 409         if (dev_priv->params.psr_safest_params) {
 410                 val |= EDP_PSR_TP1_TIME_2500us;
 411                 val |= EDP_PSR_TP2_TP3_TIME_2500us;
 412                 goto check_tp3_sel;
 413         }
 414
 415         if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0)
 416                 val |= EDP_PSR_TP1_TIME_0us;
 417         else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100)
 418                 val |= EDP_PSR_TP1_TIME_100us;
 419         else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500)
 420                 val |= EDP_PSR_TP1_TIME_500us;
 421         else
 422                 val |= EDP_PSR_TP1_TIME_2500us;
 423
 424         if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0)
 425                 val |= EDP_PSR_TP2_TP3_TIME_0us;
 426         else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100)
 427                 val |= EDP_PSR_TP2_TP3_TIME_100us;
 428         else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500)
 429                 val |= EDP_PSR_TP2_TP3_TIME_500us;
 430         else
 431                 val |= EDP_PSR_TP2_TP3_TIME_2500us;
 432
 433 check_tp3_sel:
 434         if (intel_dp_source_supports_tps3(dev_priv) &&
 435             drm_dp_tps3_supported(intel_dp->dpcd))
 436                 val |= EDP_PSR_TP1_TP3_SEL;
 437         else
 438                 val |= EDP_PSR_TP1_TP2_SEL;
 439
 440         return val;
 441 }
 442
 443 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
 444 {
 445         struct intel_connector *connector = intel_dp->attached_connector;
 446         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 447         int idle_frames;
 448
 449         /* Let's use 6 as the minimum to cover all known cases including the
 450          * off-by-one issue that HW has in some cases.
 451          */
 452         idle_frames = max(6, connector->panel.vbt.psr.idle_frames);
 453         idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1);
 454
 455         if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf))
 456                 idle_frames = 0xf;
 457
 458         return idle_frames;
 459 }
 460
 461 static void hsw_activate_psr1(struct intel_dp *intel_dp)
 462 {
 463         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 464         u32 max_sleep_time = 0x1f;
 465         u32 val = EDP_PSR_ENABLE;
 466
 467         val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT;
 468
 469         val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
 470         if (IS_HASWELL(dev_priv))
 471                 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 472
 473         if (intel_dp->psr.link_standby)
 474                 val |= EDP_PSR_LINK_STANDBY;
 475
 476         val |= intel_psr1_get_tp_time(intel_dp);
 477
 478         if (DISPLAY_VER(dev_priv) >= 8)
 479                 val |= EDP_PSR_CRC_ENABLE;
 480
 481         val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) &
 482                 EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK);
 483         intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val);
 484 }
 485
 486 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
 487 {
 488         struct intel_connector *connector = intel_dp->attached_connector;
 489         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 490         u32 val = 0;
 491
 492         if (dev_priv->params.psr_safest_params)
 493                 return EDP_PSR2_TP2_TIME_2500us;
 494
 495         if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
 496             connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
 497                 val |= EDP_PSR2_TP2_TIME_50us;
 498         else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
 499                 val |= EDP_PSR2_TP2_TIME_100us;
 500         else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
 501                 val |= EDP_PSR2_TP2_TIME_500us;
 502         else
 503                 val |= EDP_PSR2_TP2_TIME_2500us;
 504
 505         return val;
 506 }
 507
 508 static void hsw_activate_psr2(struct intel_dp *intel_dp)
 509 {
 510         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 511         u32 val = EDP_PSR2_ENABLE;
 512
 513         val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
 514
 515         if (!IS_ALDERLAKE_P(dev_priv))
 516                 val |= EDP_SU_TRACK_ENABLE;
 517
 518         if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
 519                 val |= EDP_Y_COORDINATE_ENABLE;
 520
 521         val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp->psr.sink_sync_latency + 1, 2));
 522         val |= intel_psr2_get_tp_time(intel_dp);
 523
 524         /* Wa_22012278275:adl-p */
 525         if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
 526                 static const u8 map[] = {
 527                         2, /* 5 lines */
 528                         1, /* 6 lines */
 529                         0, /* 7 lines */
 530                         3, /* 8 lines */
 531                         6, /* 9 lines */
 532                         5, /* 10 lines */
 533                         4, /* 11 lines */
 534                         7, /* 12 lines */
 535                 };
 536                 /*
 537                  * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see
 538                  * comments bellow for more information
 539                  */
 540                 u32 tmp, lines = 7;
 541
 542                 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
 543
 544                 tmp = map[lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES];
 545                 tmp = tmp << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT;
 546                 val |= tmp;
 547
 548                 tmp = map[lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
 549                 tmp = tmp << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT;
 550                 val |= tmp;
 551         } else if (DISPLAY_VER(dev_priv) >= 12) {
 552                 /*
 553                  * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default
 554                  * values from BSpec. In order to setting an optimal power
 555                  * consumption, lower than 4k resoluition mode needs to decrese
 556                  * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution
 557                  * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE.
 558                  */
 559                 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
 560                 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7);
 561                 val |= TGL_EDP_PSR2_FAST_WAKE(7);
 562         } else if (DISPLAY_VER(dev_priv) >= 9) {
 563                 val |= EDP_PSR2_IO_BUFFER_WAKE(7);
 564                 val |= EDP_PSR2_FAST_WAKE(7);
 565         }
 566
 567         if (intel_dp->psr.req_psr2_sdp_prior_scanline)
 568                 val |= EDP_PSR2_SU_SDP_SCANLINE;
 569
 570         if (intel_dp->psr.psr2_sel_fetch_enabled) {
 571                 u32 tmp;
 572
 573                 /* Wa_1408330847 */
 574                 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 575                         intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
 576                                      DIS_RAM_BYPASS_PSR2_MAN_TRACK,
 577                                      DIS_RAM_BYPASS_PSR2_MAN_TRACK);
 578
 579                 tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
 580                 drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));
 581         } else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
 582                 intel_de_write(dev_priv,
 583                                PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0);
 584         }
 585
 586         /*
 587          * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is
 588          * recommending keep this bit unset while PSR2 is enabled.
 589          */
 590         intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0);
 591
 592         intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
 593 }
 594
 595 static bool
 596 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans)
 597 {
 598         if (IS_ALDERLAKE_P(dev_priv))
 599                 return trans == TRANSCODER_A || trans == TRANSCODER_B;
 600         else if (DISPLAY_VER(dev_priv) >= 12)
 601                 return trans == TRANSCODER_A;
 602         else
 603                 return trans == TRANSCODER_EDP;
 604 }
 605
 606 static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)
 607 {
 608         if (!cstate || !cstate->hw.active)
 609                 return 0;
 610
 611         return DIV_ROUND_UP(1000 * 1000,
 612                             drm_mode_vrefresh(&cstate->hw.adjusted_mode));
 613 }
 614
 615 static void psr2_program_idle_frames(struct intel_dp *intel_dp,
 616                                      u32 idle_frames)
 617 {
 618         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 619         u32 val;
 620
 621         idle_frames <<=  EDP_PSR2_IDLE_FRAME_SHIFT;
 622         val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder));
 623         val &= ~EDP_PSR2_IDLE_FRAME_MASK;
 624         val |= idle_frames;
 625         intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
 626 }
 627
 628 static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp)
 629 {
 630         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 631
 632         psr2_program_idle_frames(intel_dp, 0);
 633         intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO);
 634 }
 635
 636 static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp)
 637 {
 638         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 639
 640         intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 641         psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp));
 642 }
 643
 644 static void tgl_dc3co_disable_work(struct work_struct *work)
 645 {
 646         struct intel_dp *intel_dp =
 647                 container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
 648
 649         mutex_lock(&intel_dp->psr.lock);
 650         /* If delayed work is pending, it is not idle */
 651         if (delayed_work_pending(&intel_dp->psr.dc3co_work))
 652                 goto unlock;
 653
 654         tgl_psr2_disable_dc3co(intel_dp);
 655 unlock:
 656         mutex_unlock(&intel_dp->psr.lock);
 657 }
 658
 659 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp)
 660 {
 661         if (!intel_dp->psr.dc3co_exitline)
 662                 return;
 663
 664         cancel_delayed_work(&intel_dp->psr.dc3co_work);
 665         /* Before PSR2 exit disallow dc3co*/
 666         tgl_psr2_disable_dc3co(intel_dp);
 667 }
 668
 669 static bool
 670 dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp,
 671                               struct intel_crtc_state *crtc_state)
 672 {
 673         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 674         enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
 675         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 676         enum port port = dig_port->base.port;
 677
 678         if (IS_ALDERLAKE_P(dev_priv))
 679                 return pipe <= PIPE_B && port <= PORT_B;
 680         else
 681                 return pipe == PIPE_A && port == PORT_A;
 682 }
 683
 684 static void
 685 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
 686                                   struct intel_crtc_state *crtc_state)
 687 {
 688         const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay;
 689         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 690         u32 exit_scanlines;
 691
 692         /*
 693          * FIXME: Due to the changed sequence of activating/deactivating DC3CO,
 694          * disable DC3CO until the changed dc3co activating/deactivating sequence
 695          * is applied. B.Specs:49196
 696          */
 697         return;
 698
 699         /*
 700          * DMC's DC3CO exit mechanism has an issue with Selective Fecth
 701          * TODO: when the issue is addressed, this restriction should be removed.
 702          */
 703         if (crtc_state->enable_psr2_sel_fetch)
 704                 return;
 705
 706         if (!(dev_priv->dmc.allowed_dc_mask & DC_STATE_EN_DC3CO))
 707                 return;
 708
 709         if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
 710                 return;
 711
 712         /* Wa_16011303918:adl-p */
 713         if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 714                 return;
 715
 716         /*
 717          * DC3CO Exit time 200us B.Spec 49196
 718          * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
 719          */
 720         exit_scanlines =
 721                 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1;
 722
 723         if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay))
 724                 return;
 725
 726         crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;
 727 }
 728
 729 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
 730                                               struct intel_crtc_state *crtc_state)
 731 {
 732         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 733
 734         if (!dev_priv->params.enable_psr2_sel_fetch &&
 735             intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
 736                 drm_dbg_kms(&dev_priv->drm,
 737                             "PSR2 sel fetch not enabled, disabled by parameter\n");
 738                 return false;
 739         }
 740
 741         if (crtc_state->uapi.async_flip) {
 742                 drm_dbg_kms(&dev_priv->drm,
 743                             "PSR2 sel fetch not enabled, async flip enabled\n");
 744                 return false;
 745         }
 746
 747         /* Wa_14010254185 Wa_14010103792 */
 748         if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
 749                 drm_dbg_kms(&dev_priv->drm,
 750                             "PSR2 sel fetch not enabled, missing the implementation of WAs\n");
 751                 return false;
 752         }
 753
 754         return crtc_state->enable_psr2_sel_fetch = true;
 755 }
 756
 757 static bool psr2_granularity_check(struct intel_dp *intel_dp,
 758                                    struct intel_crtc_state *crtc_state)
 759 {
 760         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 761         const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 762         const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
 763         u16 y_granularity = 0;
 764
 765         /* PSR2 HW only send full lines so we only need to validate the width */
 766         if (crtc_hdisplay % intel_dp->psr.su_w_granularity)
 767                 return false;
 768
 769         if (crtc_vdisplay % intel_dp->psr.su_y_granularity)
 770                 return false;
 771
 772         /* HW tracking is only aligned to 4 lines */
 773         if (!crtc_state->enable_psr2_sel_fetch)
 774                 return intel_dp->psr.su_y_granularity == 4;
 775
 776         /*
 777          * adl_p has 1 line granularity. For other platforms with SW tracking we
 778          * can adjust the y coordinates to match sink requirement if multiple of
 779          * 4.
 780          */
 781         if (IS_ALDERLAKE_P(dev_priv))
 782                 y_granularity = intel_dp->psr.su_y_granularity;
 783         else if (intel_dp->psr.su_y_granularity <= 2)
 784                 y_granularity = 4;
 785         else if ((intel_dp->psr.su_y_granularity % 4) == 0)
 786                 y_granularity = intel_dp->psr.su_y_granularity;
 787
 788         if (y_granularity == 0 || crtc_vdisplay % y_granularity)
 789                 return false;
 790
 791         crtc_state->su_y_granularity = y_granularity;
 792         return true;
 793 }
 794
 795 static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp,
 796                                                         struct intel_crtc_state *crtc_state)
 797 {
 798         const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode;
 799         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 800         u32 hblank_total, hblank_ns, req_ns;
 801
 802         hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start;
 803         hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock);
 804
 805         /* From spec: (72 / number of lanes) * 1000 / symbol clock frequency MHz */
 806         req_ns = (72 / crtc_state->lane_count) * 1000 / (crtc_state->port_clock / 1000);
 807
 808         if ((hblank_ns - req_ns) > 100)
 809                 return true;
 810
 811         if (DISPLAY_VER(dev_priv) < 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b)
 812                 return false;
 813
 814         crtc_state->req_psr2_sdp_prior_scanline = true;
 815         return true;
 816 }
 817
 818 static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 819                                     struct intel_crtc_state *crtc_state)
 820 {
 821         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 822         int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 823         int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
 824         int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
 825
 826         if (!intel_dp->psr.sink_psr2_support)
 827                 return false;
 828
 829         /* JSL and EHL only supports eDP 1.3 */
 830         if (IS_JSL_EHL(dev_priv)) {
 831                 drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n");
 832                 return false;
 833         }
 834
 835         /* Wa_16011181250 */
 836         if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 837             IS_DG2(dev_priv)) {
 838                 drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this platform\n");
 839                 return false;
 840         }
 841
 842         if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
 843                 drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n");
 844                 return false;
 845         }
 846
 847         if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) {
 848                 drm_dbg_kms(&dev_priv->drm,
 849                             "PSR2 not supported in transcoder %s\n",
 850                             transcoder_name(crtc_state->cpu_transcoder));
 851                 return false;
 852         }
 853
 854         if (!psr2_global_enabled(intel_dp)) {
 855                 drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n");
 856                 return false;
 857         }
 858
 859         /*
 860          * DSC and PSR2 cannot be enabled simultaneously. If a requested
 861          * resolution requires DSC to be enabled, priority is given to DSC
 862          * over PSR2.
 863          */
 864         if (crtc_state->dsc.compression_enable) {
 865                 drm_dbg_kms(&dev_priv->drm,
 866                             "PSR2 cannot be enabled since DSC is enabled\n");
 867                 return false;
 868         }
 869
 870         if (crtc_state->crc_enabled) {
 871                 drm_dbg_kms(&dev_priv->drm,
 872                             "PSR2 not enabled because it would inhibit pipe CRC calculation\n");
 873                 return false;
 874         }
 875
 876         if (DISPLAY_VER(dev_priv) >= 12) {
 877                 psr_max_h = 5120;
 878                 psr_max_v = 3200;
 879                 max_bpp = 30;
 880         } else if (DISPLAY_VER(dev_priv) >= 10) {
 881                 psr_max_h = 4096;
 882                 psr_max_v = 2304;
 883                 max_bpp = 24;
 884         } else if (DISPLAY_VER(dev_priv) == 9) {
 885                 psr_max_h = 3640;
 886                 psr_max_v = 2304;
 887                 max_bpp = 24;
 888         }
 889
 890         if (crtc_state->pipe_bpp > max_bpp) {
 891                 drm_dbg_kms(&dev_priv->drm,
 892                             "PSR2 not enabled, pipe bpp %d > max supported %d\n",
 893                             crtc_state->pipe_bpp, max_bpp);
 894                 return false;
 895         }
 896
 897         /* Wa_16011303918:adl-p */
 898         if (crtc_state->vrr.enable &&
 899             IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
 900                 drm_dbg_kms(&dev_priv->drm,
 901                             "PSR2 not enabled, not compatible with HW stepping + VRR\n");
 902                 return false;
 903         }
 904
 905         if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) {
 906                 drm_dbg_kms(&dev_priv->drm,
 907                             "PSR2 not enabled, PSR2 SDP indication do not fit in hblank\n");
 908                 return false;
 909         }
 910
 911         if (HAS_PSR2_SEL_FETCH(dev_priv)) {
 912                 if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
 913                     !HAS_PSR_HW_TRACKING(dev_priv)) {
 914                         drm_dbg_kms(&dev_priv->drm,
 915                                     "PSR2 not enabled, selective fetch not valid and no HW tracking available\n");
 916                         return false;
 917                 }
 918         }
 919
 920         /* Wa_2209313811 */
 921         if (!crtc_state->enable_psr2_sel_fetch &&
 922             IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
 923                 drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n");
 924                 goto unsupported;
 925         }
 926
 927         if (!psr2_granularity_check(intel_dp, crtc_state)) {
 928                 drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n");
 929                 goto unsupported;
 930         }
 931
 932         if (!crtc_state->enable_psr2_sel_fetch &&
 933             (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) {
 934                 drm_dbg_kms(&dev_priv->drm,
 935                             "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n",
 936                             crtc_hdisplay, crtc_vdisplay,
 937                             psr_max_h, psr_max_v);
 938                 goto unsupported;
 939         }
 940
 941         tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
 942         return true;
 943
 944 unsupported:
 945         crtc_state->enable_psr2_sel_fetch = false;
 946         return false;
 947 }
 948
 949 void intel_psr_compute_config(struct intel_dp *intel_dp,
 950                               struct intel_crtc_state *crtc_state,
 951                               struct drm_connector_state *conn_state)
 952 {
 953         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 954         const struct drm_display_mode *adjusted_mode =
 955                 &crtc_state->hw.adjusted_mode;
 956         int psr_setup_time;
 957
 958         /*
 959          * Current PSR panels dont work reliably with VRR enabled
 960          * So if VRR is enabled, do not enable PSR.
 961          */
 962         if (crtc_state->vrr.enable)
 963                 return;
 964
 965         if (!CAN_PSR(intel_dp))
 966                 return;
 967
 968         if (!psr_global_enabled(intel_dp)) {
 969                 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
 970                 return;
 971         }
 972
 973         if (intel_dp->psr.sink_not_reliable) {
 974                 drm_dbg_kms(&dev_priv->drm,
 975                             "PSR sink implementation is not reliable\n");
 976                 return;
 977         }
 978
 979         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
 980                 drm_dbg_kms(&dev_priv->drm,
 981                             "PSR condition failed: Interlaced mode enabled\n");
 982                 return;
 983         }
 984
 985         psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
 986         if (psr_setup_time < 0) {
 987                 drm_dbg_kms(&dev_priv->drm,
 988                             "PSR condition failed: Invalid PSR setup time (0x%02x)\n",
 989                             intel_dp->psr_dpcd[1]);
 990                 return;
 991         }
 992
 993         if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
 994             adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
 995                 drm_dbg_kms(&dev_priv->drm,
 996                             "PSR condition failed: PSR setup time (%d us) too long\n",
 997                             psr_setup_time);
 998                 return;
 999         }
1000
1001         crtc_state->has_psr = true;
1002         crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
1003
1004         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1005         intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
1006                                      &crtc_state->psr_vsc);
1007 }
1008
1009 void intel_psr_get_config(struct intel_encoder *encoder,
1010                           struct intel_crtc_state *pipe_config)
1011 {
1012         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1013         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1014         struct intel_dp *intel_dp;
1015         u32 val;
1016
1017         if (!dig_port)
1018                 return;
1019
1020         intel_dp = &dig_port->dp;
1021         if (!CAN_PSR(intel_dp))
1022                 return;
1023
1024         mutex_lock(&intel_dp->psr.lock);
1025         if (!intel_dp->psr.enabled)
1026                 goto unlock;
1027
1028         /*
1029          * Not possible to read EDP_PSR/PSR2_CTL registers as it is
1030          * enabled/disabled because of frontbuffer tracking and others.
1031          */
1032         pipe_config->has_psr = true;
1033         pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
1034         pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1035
1036         if (!intel_dp->psr.psr2_enabled)
1037                 goto unlock;
1038
1039         if (HAS_PSR2_SEL_FETCH(dev_priv)) {
1040                 val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
1041                 if (val & PSR2_MAN_TRK_CTL_ENABLE)
1042                         pipe_config->enable_psr2_sel_fetch = true;
1043         }
1044
1045         if (DISPLAY_VER(dev_priv) >= 12) {
1046                 val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder));
1047                 val &= EXITLINE_MASK;
1048                 pipe_config->dc3co_exitline = val;
1049         }
1050 unlock:
1051         mutex_unlock(&intel_dp->psr.lock);
1052 }
1053
1054 static void intel_psr_activate(struct intel_dp *intel_dp)
1055 {
1056         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1057         enum transcoder transcoder = intel_dp->psr.transcoder;
1058
1059         if (transcoder_has_psr2(dev_priv, transcoder))
1060                 drm_WARN_ON(&dev_priv->drm,
1061                             intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE);
1062
1063         drm_WARN_ON(&dev_priv->drm,
1064                     intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE);
1065         drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active);
1066         lockdep_assert_held(&intel_dp->psr.lock);
1067
1068         /* psr1 and psr2 are mutually exclusive.*/
1069         if (intel_dp->psr.psr2_enabled)
1070                 hsw_activate_psr2(intel_dp);
1071         else
1072                 hsw_activate_psr1(intel_dp);
1073
1074         intel_dp->psr.active = true;
1075 }
1076
1077 static u32 wa_16013835468_bit_get(struct intel_dp *intel_dp)
1078 {
1079         switch (intel_dp->psr.pipe) {
1080         case PIPE_A:
1081                 return LATENCY_REPORTING_REMOVED_PIPE_A;
1082         case PIPE_B:
1083                 return LATENCY_REPORTING_REMOVED_PIPE_B;
1084         case PIPE_C:
1085                 return LATENCY_REPORTING_REMOVED_PIPE_C;
1086         default:
1087                 MISSING_CASE(intel_dp->psr.pipe);
1088                 return 0;
1089         }
1090 }
1091
1092 static void intel_psr_enable_source(struct intel_dp *intel_dp,
1093                                     const struct intel_crtc_state *crtc_state)
1094 {
1095         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1096         enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1097         u32 mask;
1098
1099         /*
1100          * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
1101          * mask LPSP to avoid dependency on other drivers that might block
1102          * runtime_pm besides preventing  other hw tracking issues now we
1103          * can rely on frontbuffer tracking.
1104          */
1105         mask = EDP_PSR_DEBUG_MASK_MEMUP |
1106                EDP_PSR_DEBUG_MASK_HPD |
1107                EDP_PSR_DEBUG_MASK_LPSP |
1108                EDP_PSR_DEBUG_MASK_MAX_SLEEP;
1109
1110         if (DISPLAY_VER(dev_priv) < 11)
1111                 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
1112
1113         intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder),
1114                        mask);
1115
1116         psr_irq_control(intel_dp);
1117
1118         if (intel_dp->psr.dc3co_exitline) {
1119                 u32 val;
1120
1121                 /*
1122                  * TODO: if future platforms supports DC3CO in more than one
1123                  * transcoder, EXITLINE will need to be unset when disabling PSR
1124                  */
1125                 val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder));
1126                 val &= ~EXITLINE_MASK;
1127                 val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT;
1128                 val |= EXITLINE_ENABLE;
1129                 intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val);
1130         }
1131
1132         if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv))
1133                 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,
1134                              intel_dp->psr.psr2_sel_fetch_enabled ?
1135                              IGNORE_PSR2_HW_TRACKING : 0);
1136
1137         if (intel_dp->psr.psr2_enabled) {
1138                 if (DISPLAY_VER(dev_priv) == 9)
1139                         intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
1140                                      PSR2_VSC_ENABLE_PROG_HEADER |
1141                                      PSR2_ADD_VERTICAL_LINE_COUNT);
1142
1143                 /*
1144                  * Wa_16014451276:adlp
1145                  * All supported adlp panels have 1-based X granularity, this may
1146                  * cause issues if non-supported panels are used.
1147                  */
1148                 if (IS_ALDERLAKE_P(dev_priv))
1149                         intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
1150                                      ADLP_1_BASED_X_GRANULARITY);
1151
1152                 /* Wa_16011168373:adl-p */
1153                 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
1154                         intel_de_rmw(dev_priv,
1155                                      TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
1156                                      TRANS_SET_CONTEXT_LATENCY_MASK,
1157                                      TRANS_SET_CONTEXT_LATENCY_VALUE(1));
1158
1159                 /* Wa_16012604467:adlp */
1160                 if (IS_ALDERLAKE_P(dev_priv))
1161                         intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0,
1162                                      CLKGATE_DIS_MISC_DMASC_GATING_DIS);
1163
1164                 /* Wa_16013835468:tgl[b0+], dg1 */
1165                 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) ||
1166                     IS_DG1(dev_priv)) {
1167                         u16 vtotal, vblank;
1168
1169                         vtotal = crtc_state->uapi.adjusted_mode.crtc_vtotal -
1170                                  crtc_state->uapi.adjusted_mode.crtc_vdisplay;
1171                         vblank = crtc_state->uapi.adjusted_mode.crtc_vblank_end -
1172                                  crtc_state->uapi.adjusted_mode.crtc_vblank_start;
1173                         if (vblank > vtotal)
1174                                 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0,
1175                                              wa_16013835468_bit_get(intel_dp));
1176                 }
1177         }
1178 }
1179
1180 static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
1181 {
1182         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1183         u32 val;
1184
1185         /*
1186          * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
1187          * will still keep the error set even after the reset done in the
1188          * irq_preinstall and irq_uninstall hooks.
1189          * And enabling in this situation cause the screen to freeze in the
1190          * first time that PSR HW tries to activate so lets keep PSR disabled
1191          * to avoid any rendering problems.
1192          */
1193         if (DISPLAY_VER(dev_priv) >= 12) {
1194                 val = intel_de_read(dev_priv,
1195                                     TRANS_PSR_IIR(intel_dp->psr.transcoder));
1196                 val &= EDP_PSR_ERROR(0);
1197         } else {
1198                 val = intel_de_read(dev_priv, EDP_PSR_IIR);
1199                 val &= EDP_PSR_ERROR(intel_dp->psr.transcoder);
1200         }
1201         if (val) {
1202                 intel_dp->psr.sink_not_reliable = true;
1203                 drm_dbg_kms(&dev_priv->drm,
1204                             "PSR interruption error set, not enabling PSR\n");
1205                 return false;
1206         }
1207
1208         return true;
1209 }
1210
1211 static void intel_psr_enable_locked(struct intel_dp *intel_dp,
1212                                     const struct intel_crtc_state *crtc_state)
1213 {
1214         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1215         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1216         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
1217         struct intel_encoder *encoder = &dig_port->base;
1218         u32 val;
1219
1220         drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
1221
1222         intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
1223         intel_dp->psr.busy_frontbuffer_bits = 0;
1224         intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
1225         intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
1226         /* DC5/DC6 requires at least 6 idle frames */
1227         val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
1228         intel_dp->psr.dc3co_exit_delay = val;
1229         intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
1230         intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
1231         intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
1232         intel_dp->psr.req_psr2_sdp_prior_scanline =
1233                 crtc_state->req_psr2_sdp_prior_scanline;
1234
1235         if (!psr_interrupt_error_check(intel_dp))
1236                 return;
1237
1238         drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
1239                     intel_dp->psr.psr2_enabled ? "2" : "1");
1240         intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc);
1241         intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
1242         intel_psr_enable_sink(intel_dp);
1243         intel_psr_enable_source(intel_dp, crtc_state);
1244         intel_dp->psr.enabled = true;
1245         intel_dp->psr.paused = false;
1246
1247         intel_psr_activate(intel_dp);
1248 }
1249
1250 static void intel_psr_exit(struct intel_dp *intel_dp)
1251 {
1252         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1253         u32 val;
1254
1255         if (!intel_dp->psr.active) {
1256                 if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) {
1257                         val = intel_de_read(dev_priv,
1258                                             EDP_PSR2_CTL(intel_dp->psr.transcoder));
1259                         drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE);
1260                 }
1261
1262                 val = intel_de_read(dev_priv,
1263                                     EDP_PSR_CTL(intel_dp->psr.transcoder));
1264                 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE);
1265
1266                 return;
1267         }
1268
1269         if (intel_dp->psr.psr2_enabled) {
1270                 tgl_disallow_dc3co_on_psr2_exit(intel_dp);
1271                 val = intel_de_read(dev_priv,
1272                                     EDP_PSR2_CTL(intel_dp->psr.transcoder));
1273                 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE));
1274                 val &= ~EDP_PSR2_ENABLE;
1275                 intel_de_write(dev_priv,
1276                                EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
1277         } else {
1278                 val = intel_de_read(dev_priv,
1279                                     EDP_PSR_CTL(intel_dp->psr.transcoder));
1280                 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE));
1281                 val &= ~EDP_PSR_ENABLE;
1282                 intel_de_write(dev_priv,
1283                                EDP_PSR_CTL(intel_dp->psr.transcoder), val);
1284         }
1285         intel_dp->psr.active = false;
1286 }
1287
1288 static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)
1289 {
1290         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1291         i915_reg_t psr_status;
1292         u32 psr_status_mask;
1293
1294         if (intel_dp->psr.psr2_enabled) {
1295                 psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
1296                 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
1297         } else {
1298                 psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder);
1299                 psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
1300         }
1301
1302         /* Wait till PSR is idle */
1303         if (intel_de_wait_for_clear(dev_priv, psr_status,
1304                                     psr_status_mask, 2000))
1305                 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n");
1306 }
1307
1308 static void intel_psr_disable_locked(struct intel_dp *intel_dp)
1309 {
1310         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1311         enum phy phy = intel_port_to_phy(dev_priv,
1312                                          dp_to_dig_port(intel_dp)->base.port);
1313
1314         lockdep_assert_held(&intel_dp->psr.lock);
1315
1316         if (!intel_dp->psr.enabled)
1317                 return;
1318
1319         drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
1320                     intel_dp->psr.psr2_enabled ? "2" : "1");
1321
1322         intel_psr_exit(intel_dp);
1323         intel_psr_wait_exit_locked(intel_dp);
1324
1325         /* Wa_1408330847 */
1326         if (intel_dp->psr.psr2_sel_fetch_enabled &&
1327             IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
1328                 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
1329                              DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
1330
1331         if (intel_dp->psr.psr2_enabled) {
1332                 /* Wa_16011168373:adl-p */
1333                 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
1334                         intel_de_rmw(dev_priv,
1335                                      TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
1336                                      TRANS_SET_CONTEXT_LATENCY_MASK, 0);
1337
1338                 /* Wa_16012604467:adlp */
1339                 if (IS_ALDERLAKE_P(dev_priv))
1340                         intel_de_rmw(dev_priv, CLKGATE_DIS_MISC,
1341                                      CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0);
1342
1343                 /* Wa_16013835468:tgl[b0+], dg1 */
1344                 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) ||
1345                     IS_DG1(dev_priv))
1346                         intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
1347                                      wa_16013835468_bit_get(intel_dp), 0);
1348         }
1349
1350         intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
1351
1352         /* Disable PSR on Sink */
1353         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
1354
1355         if (intel_dp->psr.psr2_enabled)
1356                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0);
1357
1358         intel_dp->psr.enabled = false;
1359         intel_dp->psr.psr2_enabled = false;
1360         intel_dp->psr.psr2_sel_fetch_enabled = false;
1361         intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
1362 }
1363
1364 /**
1365  * intel_psr_disable - Disable PSR
1366  * @intel_dp: Intel DP
1367  * @old_crtc_state: old CRTC state
1368  *
1369  * This function needs to be called before disabling pipe.
1370  */
1371 void intel_psr_disable(struct intel_dp *intel_dp,
1372                        const struct intel_crtc_state *old_crtc_state)
1373 {
1374         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1375
1376         if (!old_crtc_state->has_psr)
1377                 return;
1378
1379         if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp)))
1380                 return;
1381
1382         mutex_lock(&intel_dp->psr.lock);
1383
1384         intel_psr_disable_locked(intel_dp);
1385
1386         mutex_unlock(&intel_dp->psr.lock);
1387         cancel_work_sync(&intel_dp->psr.work);
1388         cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
1389 }
1390
1391 /**
1392  * intel_psr_pause - Pause PSR
1393  * @intel_dp: Intel DP
1394  *
1395  * This function need to be called after enabling psr.
1396  */
1397 void intel_psr_pause(struct intel_dp *intel_dp)
1398 {
1399         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1400         struct intel_psr *psr = &intel_dp->psr;
1401
1402         if (!CAN_PSR(intel_dp))
1403                 return;
1404
1405         mutex_lock(&psr->lock);
1406
1407         if (!psr->enabled) {
1408                 mutex_unlock(&psr->lock);
1409                 return;
1410         }
1411
1412         /* If we ever hit this, we will need to add refcount to pause/resume */
1413         drm_WARN_ON(&dev_priv->drm, psr->paused);
1414
1415         intel_psr_exit(intel_dp);
1416         intel_psr_wait_exit_locked(intel_dp);
1417         psr->paused = true;
1418
1419         mutex_unlock(&psr->lock);
1420
1421         cancel_work_sync(&psr->work);
1422         cancel_delayed_work_sync(&psr->dc3co_work);
1423 }
1424
1425 /**
1426  * intel_psr_resume - Resume PSR
1427  * @intel_dp: Intel DP
1428  *
1429  * This function need to be called after pausing psr.
1430  */
1431 void intel_psr_resume(struct intel_dp *intel_dp)
1432 {
1433         struct intel_psr *psr = &intel_dp->psr;
1434
1435         if (!CAN_PSR(intel_dp))
1436                 return;
1437
1438         mutex_lock(&psr->lock);
1439
1440         if (!psr->paused)
1441                 goto unlock;
1442
1443         psr->paused = false;
1444         intel_psr_activate(intel_dp);
1445
1446 unlock:
1447         mutex_unlock(&psr->lock);
1448 }
1449
1450 static u32 man_trk_ctl_enable_bit_get(struct drm_i915_private *dev_priv)
1451 {
1452         return IS_ALDERLAKE_P(dev_priv) ? 0 : PSR2_MAN_TRK_CTL_ENABLE;
1453 }
1454
1455 static u32 man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private *dev_priv)
1456 {
1457         return IS_ALDERLAKE_P(dev_priv) ?
1458                ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME :
1459                PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
1460 }
1461
1462 static u32 man_trk_ctl_partial_frame_bit_get(struct drm_i915_private *dev_priv)
1463 {
1464         return IS_ALDERLAKE_P(dev_priv) ?
1465                ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE :
1466                PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
1467 }
1468
1469 static u32 man_trk_ctl_continuos_full_frame(struct drm_i915_private *dev_priv)
1470 {
1471         return IS_ALDERLAKE_P(dev_priv) ?
1472                ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME :
1473                PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME;
1474 }
1475
1476 static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
1477 {
1478         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1479
1480         if (intel_dp->psr.psr2_sel_fetch_enabled)
1481                 intel_de_write(dev_priv,
1482                                PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
1483                                man_trk_ctl_enable_bit_get(dev_priv) |
1484                                man_trk_ctl_partial_frame_bit_get(dev_priv) |
1485                                man_trk_ctl_single_full_frame_bit_get(dev_priv));
1486
1487         /*
1488          * Display WA #0884: skl+
1489          * This documented WA for bxt can be safely applied
1490          * broadly so we can force HW tracking to exit PSR
1491          * instead of disabling and re-enabling.
1492          * Workaround tells us to write 0 to CUR_SURFLIVE_A,
1493          * but it makes more sense write to the current active
1494          * pipe.
1495          *
1496          * This workaround do not exist for platforms with display 10 or newer
1497          * but testing proved that it works for up display 13, for newer
1498          * than that testing will be needed.
1499          */
1500         intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
1501 }
1502
1503 void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
1504                                         const struct intel_crtc_state *crtc_state)
1505 {
1506         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1507         enum pipe pipe = plane->pipe;
1508
1509         if (!crtc_state->enable_psr2_sel_fetch)
1510                 return;
1511
1512         intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
1513 }
1514
1515 void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
1516                                         const struct intel_crtc_state *crtc_state,
1517                                         const struct intel_plane_state *plane_state,
1518                                         int color_plane)
1519 {
1520         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1521         enum pipe pipe = plane->pipe;
1522         const struct drm_rect *clip;
1523         u32 val;
1524         int x, y;
1525
1526         if (!crtc_state->enable_psr2_sel_fetch)
1527                 return;
1528
1529         if (plane->id == PLANE_CURSOR) {
1530                 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
1531                                   plane_state->ctl);
1532                 return;
1533         }
1534
1535         clip = &plane_state->psr2_sel_fetch_area;
1536
1537         val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
1538         val |= plane_state->uapi.dst.x1;
1539         intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
1540
1541         x = plane_state->view.color_plane[color_plane].x;
1542
1543         /*
1544          * From Bspec: UV surface Start Y Position = half of Y plane Y
1545          * start position.
1546          */
1547         if (!color_plane)
1548                 y = plane_state->view.color_plane[color_plane].y + clip->y1;
1549         else
1550                 y = plane_state->view.color_plane[color_plane].y + clip->y1 / 2;
1551
1552         val = y << 16 | x;
1553
1554         intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
1555                           val);
1556
1557         /* Sizes are 0 based */
1558         val = (drm_rect_height(clip) - 1) << 16;
1559         val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
1560         intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
1561
1562         intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
1563                           PLANE_SEL_FETCH_CTL_ENABLE);
1564 }
1565
1566 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
1567 {
1568         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1569         struct intel_encoder *encoder;
1570
1571         if (!crtc_state->enable_psr2_sel_fetch)
1572                 return;
1573
1574         for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
1575                                              crtc_state->uapi.encoder_mask) {
1576                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1577
1578                 lockdep_assert_held(&intel_dp->psr.lock);
1579                 if (intel_dp->psr.psr2_sel_fetch_cff_enabled)
1580                         return;
1581                 break;
1582         }
1583
1584         intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder),
1585                        crtc_state->psr2_man_track_ctl);
1586 }
1587
1588 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
1589                                   struct drm_rect *clip, bool full_update)
1590 {
1591         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1592         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1593         u32 val = man_trk_ctl_enable_bit_get(dev_priv);
1594
1595         /* SF partial frame enable has to be set even on full update */
1596         val |= man_trk_ctl_partial_frame_bit_get(dev_priv);
1597
1598         if (full_update) {
1599                 /*
1600                  * Not applying Wa_14014971508:adlp as we do not support the
1601                  * feature that requires this workaround.
1602                  */
1603                 val |= man_trk_ctl_single_full_frame_bit_get(dev_priv);
1604                 goto exit;
1605         }
1606
1607         if (clip->y1 == -1)
1608                 goto exit;
1609
1610         if (IS_ALDERLAKE_P(dev_priv)) {
1611                 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1);
1612                 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 - 1);
1613         } else {
1614                 drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
1615
1616                 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
1617                 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
1618         }
1619 exit:
1620         crtc_state->psr2_man_track_ctl = val;
1621 }
1622
1623 static void clip_area_update(struct drm_rect *overlap_damage_area,
1624                              struct drm_rect *damage_area)
1625 {
1626         if (overlap_damage_area->y1 == -1) {
1627                 overlap_damage_area->y1 = damage_area->y1;
1628                 overlap_damage_area->y2 = damage_area->y2;
1629                 return;
1630         }
1631
1632         if (damage_area->y1 < overlap_damage_area->y1)
1633                 overlap_damage_area->y1 = damage_area->y1;
1634
1635         if (damage_area->y2 > overlap_damage_area->y2)
1636                 overlap_damage_area->y2 = damage_area->y2;
1637 }
1638
1639 static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state,
1640                                                 struct drm_rect *pipe_clip)
1641 {
1642         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1643         const u16 y_alignment = crtc_state->su_y_granularity;
1644
1645         pipe_clip->y1 -= pipe_clip->y1 % y_alignment;
1646         if (pipe_clip->y2 % y_alignment)
1647                 pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment;
1648
1649         if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable)
1650                 drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n");
1651 }
1652
1653 /*
1654  * TODO: Not clear how to handle planes with negative position,
1655  * also planes are not updated if they have a negative X
1656  * position so for now doing a full update in this cases
1657  *
1658  * Plane scaling and rotation is not supported by selective fetch and both
1659  * properties can change without a modeset, so need to be check at every
1660  * atomic commmit.
1661  */
1662 static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state)
1663 {
1664         if (plane_state->uapi.dst.y1 < 0 ||
1665             plane_state->uapi.dst.x1 < 0 ||
1666             plane_state->scaler_id >= 0 ||
1667             plane_state->uapi.rotation != DRM_MODE_ROTATE_0)
1668                 return false;
1669
1670         return true;
1671 }
1672
1673 /*
1674  * Check for pipe properties that is not supported by selective fetch.
1675  *
1676  * TODO: pipe scaling causes a modeset but skl_update_scaler_crtc() is executed
1677  * after intel_psr_compute_config(), so for now keeping PSR2 selective fetch
1678  * enabled and going to the full update path.
1679  */
1680 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state)
1681 {
1682         if (crtc_state->scaler_state.scaler_id >= 0)
1683                 return false;
1684
1685         return true;
1686 }
1687
1688 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
1689                                 struct intel_crtc *crtc)
1690 {
1691         struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1692         struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 };
1693         struct intel_plane_state *new_plane_state, *old_plane_state;
1694         struct intel_plane *plane;
1695         bool full_update = false;
1696         int i, ret;
1697
1698         if (!crtc_state->enable_psr2_sel_fetch)
1699                 return 0;
1700
1701         if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) {
1702                 full_update = true;
1703                 goto skip_sel_fetch_set_loop;
1704         }
1705
1706         /*
1707          * Calculate minimal selective fetch area of each plane and calculate
1708          * the pipe damaged area.
1709          * In the next loop the plane selective fetch area will actually be set
1710          * using whole pipe damaged area.
1711          */
1712         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
1713                                              new_plane_state, i) {
1714                 struct drm_rect src, damaged_area = { .y1 = -1 };
1715                 struct drm_atomic_helper_damage_iter iter;
1716                 struct drm_rect clip;
1717
1718                 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
1719                         continue;
1720
1721                 if (!new_plane_state->uapi.visible &&
1722                     !old_plane_state->uapi.visible)
1723                         continue;
1724
1725                 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
1726                         full_update = true;
1727                         break;
1728                 }
1729
1730                 /*
1731                  * If visibility or plane moved, mark the whole plane area as
1732                  * damaged as it needs to be complete redraw in the new and old
1733                  * position.
1734                  */
1735                 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible ||
1736                     !drm_rect_equals(&new_plane_state->uapi.dst,
1737                                      &old_plane_state->uapi.dst)) {
1738                         if (old_plane_state->uapi.visible) {
1739                                 damaged_area.y1 = old_plane_state->uapi.dst.y1;
1740                                 damaged_area.y2 = old_plane_state->uapi.dst.y2;
1741                                 clip_area_update(&pipe_clip, &damaged_area);
1742                         }
1743
1744                         if (new_plane_state->uapi.visible) {
1745                                 damaged_area.y1 = new_plane_state->uapi.dst.y1;
1746                                 damaged_area.y2 = new_plane_state->uapi.dst.y2;
1747                                 clip_area_update(&pipe_clip, &damaged_area);
1748                         }
1749                         continue;
1750                 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) {
1751                         /* If alpha changed mark the whole plane area as damaged */
1752                         damaged_area.y1 = new_plane_state->uapi.dst.y1;
1753                         damaged_area.y2 = new_plane_state->uapi.dst.y2;
1754                         clip_area_update(&pipe_clip, &damaged_area);
1755                         continue;
1756                 }
1757
1758                 drm_rect_fp_to_int(&src, &new_plane_state->uapi.src);
1759
1760                 drm_atomic_helper_damage_iter_init(&iter,
1761                                                    &old_plane_state->uapi,
1762                                                    &new_plane_state->uapi);
1763                 drm_atomic_for_each_plane_damage(&iter, &clip) {
1764                         if (drm_rect_intersect(&clip, &src))
1765                                 clip_area_update(&damaged_area, &clip);
1766                 }
1767
1768                 if (damaged_area.y1 == -1)
1769                         continue;
1770
1771                 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1;
1772                 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1;
1773                 clip_area_update(&pipe_clip, &damaged_area);
1774         }
1775
1776         if (full_update)
1777                 goto skip_sel_fetch_set_loop;
1778
1779         ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
1780         if (ret)
1781                 return ret;
1782
1783         intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip);
1784
1785         /*
1786          * Now that we have the pipe damaged area check if it intersect with
1787          * every plane, if it does set the plane selective fetch area.
1788          */
1789         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
1790                                              new_plane_state, i) {
1791                 struct drm_rect *sel_fetch_area, inter;
1792                 struct intel_plane *linked = new_plane_state->planar_linked_plane;
1793
1794                 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc ||
1795                     !new_plane_state->uapi.visible)
1796                         continue;
1797
1798                 inter = pipe_clip;
1799                 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst))
1800                         continue;
1801
1802                 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
1803                         full_update = true;
1804                         break;
1805                 }
1806
1807                 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
1808                 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1;
1809                 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1;
1810                 crtc_state->update_planes |= BIT(plane->id);
1811
1812                 /*
1813                  * Sel_fetch_area is calculated for UV plane. Use
1814                  * same area for Y plane as well.
1815                  */
1816                 if (linked) {
1817                         struct intel_plane_state *linked_new_plane_state;
1818                         struct drm_rect *linked_sel_fetch_area;
1819
1820                         linked_new_plane_state = intel_atomic_get_plane_state(state, linked);
1821                         if (IS_ERR(linked_new_plane_state))
1822                                 return PTR_ERR(linked_new_plane_state);
1823
1824                         linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area;
1825                         linked_sel_fetch_area->y1 = sel_fetch_area->y1;
1826                         linked_sel_fetch_area->y2 = sel_fetch_area->y2;
1827                         crtc_state->update_planes |= BIT(linked->id);
1828                 }
1829         }
1830
1831 skip_sel_fetch_set_loop:
1832         psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update);
1833         return 0;
1834 }
1835
1836 void intel_psr_pre_plane_update(struct intel_atomic_state *state,
1837                                 struct intel_crtc *crtc)
1838 {
1839         struct drm_i915_private *i915 = to_i915(state->base.dev);
1840         const struct intel_crtc_state *crtc_state =
1841                 intel_atomic_get_new_crtc_state(state, crtc);
1842         struct intel_encoder *encoder;
1843
1844         if (!HAS_PSR(i915))
1845                 return;
1846
1847         for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
1848                                              crtc_state->uapi.encoder_mask) {
1849                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1850                 struct intel_psr *psr = &intel_dp->psr;
1851                 bool needs_to_disable = false;
1852
1853                 mutex_lock(&psr->lock);
1854
1855                 /*
1856                  * Reasons to disable:
1857                  * - PSR disabled in new state
1858                  * - All planes will go inactive
1859                  * - Changing between PSR versions
1860                  */
1861                 needs_to_disable |= intel_crtc_needs_modeset(crtc_state);
1862                 needs_to_disable |= !crtc_state->has_psr;
1863                 needs_to_disable |= !crtc_state->active_planes;
1864                 needs_to_disable |= crtc_state->has_psr2 != psr->psr2_enabled;
1865
1866                 if (psr->enabled && needs_to_disable)
1867                         intel_psr_disable_locked(intel_dp);
1868
1869                 mutex_unlock(&psr->lock);
1870         }
1871 }
1872
1873 static void _intel_psr_post_plane_update(const struct intel_atomic_state *state,
1874                                          const struct intel_crtc_state *crtc_state)
1875 {
1876         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1877         struct intel_encoder *encoder;
1878
1879         if (!crtc_state->has_psr)
1880                 return;
1881
1882         for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
1883                                              crtc_state->uapi.encoder_mask) {
1884                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1885                 struct intel_psr *psr = &intel_dp->psr;
1886
1887                 mutex_lock(&psr->lock);
1888
1889                 if (psr->sink_not_reliable)
1890                         goto exit;
1891
1892                 drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes);
1893
1894                 /* Only enable if there is active planes */
1895                 if (!psr->enabled && crtc_state->active_planes)
1896                         intel_psr_enable_locked(intel_dp, crtc_state);
1897
1898                 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */
1899                 if (crtc_state->crc_enabled && psr->enabled)
1900                         psr_force_hw_tracking_exit(intel_dp);
1901
1902 exit:
1903                 mutex_unlock(&psr->lock);
1904         }
1905 }
1906
1907 void intel_psr_post_plane_update(const struct intel_atomic_state *state)
1908 {
1909         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1910         struct intel_crtc_state *crtc_state;
1911         struct intel_crtc *crtc;
1912         int i;
1913
1914         if (!HAS_PSR(dev_priv))
1915                 return;
1916
1917         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)
1918                 _intel_psr_post_plane_update(state, crtc_state);
1919 }
1920
1921 static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
1922 {
1923         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1924
1925         /*
1926          * Any state lower than EDP_PSR2_STATUS_STATE_DEEP_SLEEP is enough.
1927          * As all higher states has bit 4 of PSR2 state set we can just wait for
1928          * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared.
1929          */
1930         return intel_de_wait_for_clear(dev_priv,
1931                                        EDP_PSR2_STATUS(intel_dp->psr.transcoder),
1932                                        EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 50);
1933 }
1934
1935 static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
1936 {
1937         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1938
1939         /*
1940          * From bspec: Panel Self Refresh (BDW+)
1941          * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of
1942          * exit training time + 1.5 ms of aux channel handshake. 50 ms is
1943          * defensive enough to cover everything.
1944          */
1945         return intel_de_wait_for_clear(dev_priv,
1946                                        EDP_PSR_STATUS(intel_dp->psr.transcoder),
1947                                        EDP_PSR_STATUS_STATE_MASK, 50);
1948 }
1949
1950 /**
1951  * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update
1952  * @new_crtc_state: new CRTC state
1953  *
1954  * This function is expected to be called from pipe_update_start() where it is
1955  * not expected to race with PSR enable or disable.
1956  */
1957 void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state)
1958 {
1959         struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev);
1960         struct intel_encoder *encoder;
1961
1962         if (!new_crtc_state->has_psr)
1963                 return;
1964
1965         for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
1966                                              new_crtc_state->uapi.encoder_mask) {
1967                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1968                 int ret;
1969
1970                 lockdep_assert_held(&intel_dp->psr.lock);
1971
1972                 if (!intel_dp->psr.enabled)
1973                         continue;
1974
1975                 if (intel_dp->psr.psr2_enabled)
1976                         ret = _psr2_ready_for_pipe_update_locked(intel_dp);
1977                 else
1978                         ret = _psr1_ready_for_pipe_update_locked(intel_dp);
1979
1980                 if (ret)
1981                         drm_err(&dev_priv->drm, "PSR wait timed out, atomic update may fail\n");
1982         }
1983 }
1984
1985 static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
1986 {
1987         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1988         i915_reg_t reg;
1989         u32 mask;
1990         int err;
1991
1992         if (!intel_dp->psr.enabled)
1993                 return false;
1994
1995         if (intel_dp->psr.psr2_enabled) {
1996                 reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
1997                 mask = EDP_PSR2_STATUS_STATE_MASK;
1998         } else {
1999                 reg = EDP_PSR_STATUS(intel_dp->psr.transcoder);
2000                 mask = EDP_PSR_STATUS_STATE_MASK;
2001         }
2002
2003         mutex_unlock(&intel_dp->psr.lock);
2004
2005         err = intel_de_wait_for_clear(dev_priv, reg, mask, 50);
2006         if (err)
2007                 drm_err(&dev_priv->drm,
2008                         "Timed out waiting for PSR Idle for re-enable\n");
2009
2010         /* After the unlocked wait, verify that PSR is still wanted! */
2011         mutex_lock(&intel_dp->psr.lock);
2012         return err == 0 && intel_dp->psr.enabled;
2013 }
2014
2015 static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
2016 {
2017         struct drm_connector_list_iter conn_iter;
2018         struct drm_device *dev = &dev_priv->drm;
2019         struct drm_modeset_acquire_ctx ctx;
2020         struct drm_atomic_state *state;
2021         struct drm_connector *conn;
2022         int err = 0;
2023
2024         state = drm_atomic_state_alloc(dev);
2025         if (!state)
2026                 return -ENOMEM;
2027
2028         drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
2029         state->acquire_ctx = &ctx;
2030
2031 retry:
2032
2033         drm_connector_list_iter_begin(dev, &conn_iter);
2034         drm_for_each_connector_iter(conn, &conn_iter) {
2035                 struct drm_connector_state *conn_state;
2036                 struct drm_crtc_state *crtc_state;
2037
2038                 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP)
2039                         continue;
2040
2041                 conn_state = drm_atomic_get_connector_state(state, conn);
2042                 if (IS_ERR(conn_state)) {
2043                         err = PTR_ERR(conn_state);
2044                         break;
2045                 }
2046
2047                 if (!conn_state->crtc)
2048                         continue;
2049
2050                 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc);
2051                 if (IS_ERR(crtc_state)) {
2052                         err = PTR_ERR(crtc_state);
2053                         break;
2054                 }
2055
2056                 /* Mark mode as changed to trigger a pipe->update() */
2057                 crtc_state->mode_changed = true;
2058         }
2059         drm_connector_list_iter_end(&conn_iter);
2060
2061         if (err == 0)
2062                 err = drm_atomic_commit(state);
2063
2064         if (err == -EDEADLK) {
2065                 drm_atomic_state_clear(state);
2066                 err = drm_modeset_backoff(&ctx);
2067                 if (!err)
2068                         goto retry;
2069         }
2070
2071         drm_modeset_drop_locks(&ctx);
2072         drm_modeset_acquire_fini(&ctx);
2073         drm_atomic_state_put(state);
2074
2075         return err;
2076 }
2077
2078 int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val)
2079 {
2080         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2081         const u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
2082         u32 old_mode;
2083         int ret;
2084
2085         if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) ||
2086             mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
2087                 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val);
2088                 return -EINVAL;
2089         }
2090
2091         ret = mutex_lock_interruptible(&intel_dp->psr.lock);
2092         if (ret)
2093                 return ret;
2094
2095         old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK;
2096         intel_dp->psr.debug = val;
2097
2098         /*
2099          * Do it right away if it's already enabled, otherwise it will be done
2100          * when enabling the source.
2101          */
2102         if (intel_dp->psr.enabled)
2103                 psr_irq_control(intel_dp);
2104
2105         mutex_unlock(&intel_dp->psr.lock);
2106
2107         if (old_mode != mode)
2108                 ret = intel_psr_fastset_force(dev_priv);
2109
2110         return ret;
2111 }
2112
2113 static void intel_psr_handle_irq(struct intel_dp *intel_dp)
2114 {
2115         struct intel_psr *psr = &intel_dp->psr;
2116
2117         intel_psr_disable_locked(intel_dp);
2118         psr->sink_not_reliable = true;
2119         /* let's make sure that sink is awaken */
2120         drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
2121 }
2122
2123 static void intel_psr_work(struct work_struct *work)
2124 {
2125         struct intel_dp *intel_dp =
2126                 container_of(work, typeof(*intel_dp), psr.work);
2127
2128         mutex_lock(&intel_dp->psr.lock);
2129
2130         if (!intel_dp->psr.enabled)
2131                 goto unlock;
2132
2133         if (READ_ONCE(intel_dp->psr.irq_aux_error))
2134                 intel_psr_handle_irq(intel_dp);
2135
2136         /*
2137          * We have to make sure PSR is ready for re-enable
2138          * otherwise it keeps disabled until next full enable/disable cycle.
2139          * PSR might take some time to get fully disabled
2140          * and be ready for re-enable.
2141          */
2142         if (!__psr_wait_for_idle_locked(intel_dp))
2143                 goto unlock;
2144
2145         /*
2146          * The delayed work can race with an invalidate hence we need to
2147          * recheck. Since psr_flush first clears this and then reschedules we
2148          * won't ever miss a flush when bailing out here.
2149          */
2150         if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active)
2151                 goto unlock;
2152
2153         intel_psr_activate(intel_dp);
2154 unlock:
2155         mutex_unlock(&intel_dp->psr.lock);
2156 }
2157
2158 static void _psr_invalidate_handle(struct intel_dp *intel_dp)
2159 {
2160         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2161
2162         if (intel_dp->psr.psr2_sel_fetch_enabled) {
2163                 u32 val;
2164
2165                 if (intel_dp->psr.psr2_sel_fetch_cff_enabled)
2166                         return;
2167
2168                 val = man_trk_ctl_enable_bit_get(dev_priv) |
2169                       man_trk_ctl_partial_frame_bit_get(dev_priv) |
2170                       man_trk_ctl_continuos_full_frame(dev_priv);
2171                 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), val);
2172                 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
2173                 intel_dp->psr.psr2_sel_fetch_cff_enabled = true;
2174         } else {
2175                 intel_psr_exit(intel_dp);
2176         }
2177 }
2178
2179 /**
2180  * intel_psr_invalidate - Invalidade PSR
2181  * @dev_priv: i915 device
2182  * @frontbuffer_bits: frontbuffer plane tracking bits
2183  * @origin: which operation caused the invalidate
2184  *
2185  * Since the hardware frontbuffer tracking has gaps we need to integrate
2186  * with the software frontbuffer tracking. This function gets called every
2187  * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
2188  * disabled if the frontbuffer mask contains a buffer relevant to PSR.
2189  *
2190  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
2191  */
2192 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
2193                           unsigned frontbuffer_bits, enum fb_op_origin origin)
2194 {
2195         struct intel_encoder *encoder;
2196
2197         if (origin == ORIGIN_FLIP)
2198                 return;
2199
2200         for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2201                 unsigned int pipe_frontbuffer_bits = frontbuffer_bits;
2202                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2203
2204                 mutex_lock(&intel_dp->psr.lock);
2205                 if (!intel_dp->psr.enabled) {
2206                         mutex_unlock(&intel_dp->psr.lock);
2207                         continue;
2208                 }
2209
2210                 pipe_frontbuffer_bits &=
2211                         INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
2212                 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits;
2213
2214                 if (pipe_frontbuffer_bits)
2215                         _psr_invalidate_handle(intel_dp);
2216
2217                 mutex_unlock(&intel_dp->psr.lock);
2218         }
2219 }
2220 /*
2221  * When we will be completely rely on PSR2 S/W tracking in future,
2222  * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP
2223  * event also therefore tgl_dc3co_flush_locked() require to be changed
2224  * accordingly in future.
2225  */
2226 static void
2227 tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
2228                        enum fb_op_origin origin)
2229 {
2230         if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.psr2_enabled ||
2231             !intel_dp->psr.active)
2232                 return;
2233
2234         /*
2235          * At every frontbuffer flush flip event modified delay of delayed work,
2236          * when delayed work schedules that means display has been idle.
2237          */
2238         if (!(frontbuffer_bits &
2239             INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
2240                 return;
2241
2242         tgl_psr2_enable_dc3co(intel_dp);
2243         mod_delayed_work(system_wq, &intel_dp->psr.dc3co_work,
2244                          intel_dp->psr.dc3co_exit_delay);
2245 }
2246
2247 static void _psr_flush_handle(struct intel_dp *intel_dp)
2248 {
2249         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2250
2251         if (intel_dp->psr.psr2_sel_fetch_enabled) {
2252                 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
2253                         /* can we turn CFF off? */
2254                         if (intel_dp->psr.busy_frontbuffer_bits == 0) {
2255                                 u32 val = man_trk_ctl_enable_bit_get(dev_priv) |
2256                                           man_trk_ctl_partial_frame_bit_get(dev_priv) |
2257                                           man_trk_ctl_single_full_frame_bit_get(dev_priv);
2258
2259                                 /*
2260                                  * turn continuous full frame off and do a single
2261                                  * full frame
2262                                  */
2263                                 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
2264                                                val);
2265                                 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
2266                                 intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
2267                         }
2268                 } else {
2269                         /*
2270                          * continuous full frame is disabled, only a single full
2271                          * frame is required
2272                          */
2273                         psr_force_hw_tracking_exit(intel_dp);
2274                 }
2275         } else {
2276                 psr_force_hw_tracking_exit(intel_dp);
2277
2278                 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)
2279                         schedule_work(&intel_dp->psr.work);
2280         }
2281 }
2282
2283 /**
2284  * intel_psr_flush - Flush PSR
2285  * @dev_priv: i915 device
2286  * @frontbuffer_bits: frontbuffer plane tracking bits
2287  * @origin: which operation caused the flush
2288  *
2289  * Since the hardware frontbuffer tracking has gaps we need to integrate
2290  * with the software frontbuffer tracking. This function gets called every
2291  * time frontbuffer rendering has completed and flushed out to memory. PSR
2292  * can be enabled again if no other frontbuffer relevant to PSR is dirty.
2293  *
2294  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
2295  */
2296 void intel_psr_flush(struct drm_i915_private *dev_priv,
2297                      unsigned frontbuffer_bits, enum fb_op_origin origin)
2298 {
2299         struct intel_encoder *encoder;
2300
2301         for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2302                 unsigned int pipe_frontbuffer_bits = frontbuffer_bits;
2303                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2304
2305                 mutex_lock(&intel_dp->psr.lock);
2306                 if (!intel_dp->psr.enabled) {
2307                         mutex_unlock(&intel_dp->psr.lock);
2308                         continue;
2309                 }
2310
2311                 pipe_frontbuffer_bits &=
2312                         INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
2313                 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits;
2314
2315                 /*
2316                  * If the PSR is paused by an explicit intel_psr_paused() call,
2317                  * we have to ensure that the PSR is not activated until
2318                  * intel_psr_resume() is called.
2319                  */
2320                 if (intel_dp->psr.paused)
2321                         goto unlock;
2322
2323                 if (origin == ORIGIN_FLIP ||
2324                     (origin == ORIGIN_CURSOR_UPDATE &&
2325                      !intel_dp->psr.psr2_sel_fetch_enabled)) {
2326                         tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin);
2327                         goto unlock;
2328                 }
2329
2330                 if (pipe_frontbuffer_bits == 0)
2331                         goto unlock;
2332
2333                 /* By definition flush = invalidate + flush */
2334                 _psr_flush_handle(intel_dp);
2335 unlock:
2336                 mutex_unlock(&intel_dp->psr.lock);
2337         }
2338 }
2339
2340 /**
2341  * intel_psr_init - Init basic PSR work and mutex.
2342  * @intel_dp: Intel DP
2343  *
2344  * This function is called after the initializing connector.
2345  * (the initializing of connector treats the handling of connector capabilities)
2346  * And it initializes basic PSR stuff for each DP Encoder.
2347  */
2348 void intel_psr_init(struct intel_dp *intel_dp)
2349 {
2350         struct intel_connector *connector = intel_dp->attached_connector;
2351         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2352         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2353
2354         if (!HAS_PSR(dev_priv))
2355                 return;
2356
2357         /*
2358          * HSW spec explicitly says PSR is tied to port A.
2359          * BDW+ platforms have a instance of PSR registers per transcoder but
2360          * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder
2361          * than eDP one.
2362          * For now it only supports one instance of PSR for BDW, GEN9 and GEN11.
2363          * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11.
2364          * But GEN12 supports a instance of PSR registers per transcoder.
2365          */
2366         if (DISPLAY_VER(dev_priv) < 12 && dig_port->base.port != PORT_A) {
2367                 drm_dbg_kms(&dev_priv->drm,
2368                             "PSR condition failed: Port not supported\n");
2369                 return;
2370         }
2371
2372         intel_dp->psr.source_support = true;
2373
2374         if (dev_priv->params.enable_psr == -1)
2375                 if (!connector->panel.vbt.psr.enable)
2376                         dev_priv->params.enable_psr = 0;
2377
2378         /* Set link_standby x link_off defaults */
2379         if (DISPLAY_VER(dev_priv) < 12)
2380                 /* For new platforms up to TGL let's respect VBT back again */
2381                 intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link;
2382
2383         INIT_WORK(&intel_dp->psr.work, intel_psr_work);
2384         INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);
2385         mutex_init(&intel_dp->psr.lock);
2386 }
2387
2388 static int psr_get_status_and_error_status(struct intel_dp *intel_dp,
2389                                            u8 *status, u8 *error_status)
2390 {
2391         struct drm_dp_aux *aux = &intel_dp->aux;
2392         int ret;
2393
2394         ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status);
2395         if (ret != 1)
2396                 return ret;
2397
2398         ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status);
2399         if (ret != 1)
2400                 return ret;
2401
2402         *status = *status & DP_PSR_SINK_STATE_MASK;
2403
2404         return 0;
2405 }
2406
2407 static void psr_alpm_check(struct intel_dp *intel_dp)
2408 {
2409         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2410         struct drm_dp_aux *aux = &intel_dp->aux;
2411         struct intel_psr *psr = &intel_dp->psr;
2412         u8 val;
2413         int r;
2414
2415         if (!psr->psr2_enabled)
2416                 return;
2417
2418         r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val);
2419         if (r != 1) {
2420                 drm_err(&dev_priv->drm, "Error reading ALPM status\n");
2421                 return;
2422         }
2423
2424         if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) {
2425                 intel_psr_disable_locked(intel_dp);
2426                 psr->sink_not_reliable = true;
2427                 drm_dbg_kms(&dev_priv->drm,
2428                             "ALPM lock timeout error, disabling PSR\n");
2429
2430                 /* Clearing error */
2431                 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val);
2432         }
2433 }
2434
2435 static void psr_capability_changed_check(struct intel_dp *intel_dp)
2436 {
2437         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2438         struct intel_psr *psr = &intel_dp->psr;
2439         u8 val;
2440         int r;
2441
2442         r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val);
2443         if (r != 1) {
2444                 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n");
2445                 return;
2446         }
2447
2448         if (val & DP_PSR_CAPS_CHANGE) {
2449                 intel_psr_disable_locked(intel_dp);
2450                 psr->sink_not_reliable = true;
2451                 drm_dbg_kms(&dev_priv->drm,
2452                             "Sink PSR capability changed, disabling PSR\n");
2453
2454                 /* Clearing it */
2455                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val);
2456         }
2457 }
2458
2459 void intel_psr_short_pulse(struct intel_dp *intel_dp)
2460 {
2461         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2462         struct intel_psr *psr = &intel_dp->psr;
2463         u8 status, error_status;
2464         const u8 errors = DP_PSR_RFB_STORAGE_ERROR |
2465                           DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
2466                           DP_PSR_LINK_CRC_ERROR;
2467
2468         if (!CAN_PSR(intel_dp))
2469                 return;
2470
2471         mutex_lock(&psr->lock);
2472
2473         if (!psr->enabled)
2474                 goto exit;
2475
2476         if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) {
2477                 drm_err(&dev_priv->drm,
2478                         "Error reading PSR status or error status\n");
2479                 goto exit;
2480         }
2481
2482         if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) {
2483                 intel_psr_disable_locked(intel_dp);
2484                 psr->sink_not_reliable = true;
2485         }
2486
2487         if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status)
2488                 drm_dbg_kms(&dev_priv->drm,
2489                             "PSR sink internal error, disabling PSR\n");
2490         if (error_status & DP_PSR_RFB_STORAGE_ERROR)
2491                 drm_dbg_kms(&dev_priv->drm,
2492                             "PSR RFB storage error, disabling PSR\n");
2493         if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
2494                 drm_dbg_kms(&dev_priv->drm,
2495                             "PSR VSC SDP uncorrectable error, disabling PSR\n");
2496         if (error_status & DP_PSR_LINK_CRC_ERROR)
2497                 drm_dbg_kms(&dev_priv->drm,
2498                             "PSR Link CRC error, disabling PSR\n");
2499
2500         if (error_status & ~errors)
2501                 drm_err(&dev_priv->drm,
2502                         "PSR_ERROR_STATUS unhandled errors %x\n",
2503                         error_status & ~errors);
2504         /* clear status register */
2505         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);
2506
2507         psr_alpm_check(intel_dp);
2508         psr_capability_changed_check(intel_dp);
2509
2510 exit:
2511         mutex_unlock(&psr->lock);
2512 }
2513
2514 bool intel_psr_enabled(struct intel_dp *intel_dp)
2515 {
2516         bool ret;
2517
2518         if (!CAN_PSR(intel_dp))
2519                 return false;
2520
2521         mutex_lock(&intel_dp->psr.lock);
2522         ret = intel_dp->psr.enabled;
2523         mutex_unlock(&intel_dp->psr.lock);
2524
2525         return ret;
2526 }
2527
2528 /**
2529  * intel_psr_lock - grab PSR lock
2530  * @crtc_state: the crtc state
2531  *
2532  * This is initially meant to be used by around CRTC update, when
2533  * vblank sensitive registers are updated and we need grab the lock
2534  * before it to avoid vblank evasion.
2535  */
2536 void intel_psr_lock(const struct intel_crtc_state *crtc_state)
2537 {
2538         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2539         struct intel_encoder *encoder;
2540
2541         if (!crtc_state->has_psr)
2542                 return;
2543
2544         for_each_intel_encoder_mask_with_psr(&i915->drm, encoder,
2545                                              crtc_state->uapi.encoder_mask) {
2546                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2547
2548                 mutex_lock(&intel_dp->psr.lock);
2549                 break;
2550         }
2551 }
2552
2553 /**
2554  * intel_psr_unlock - release PSR lock
2555  * @crtc_state: the crtc state
2556  *
2557  * Release the PSR lock that was held during pipe update.
2558  */
2559 void intel_psr_unlock(const struct intel_crtc_state *crtc_state)
2560 {
2561         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2562         struct intel_encoder *encoder;
2563
2564         if (!crtc_state->has_psr)
2565                 return;
2566
2567         for_each_intel_encoder_mask_with_psr(&i915->drm, encoder,
2568                                              crtc_state->uapi.encoder_mask) {
2569                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2570
2571                 mutex_unlock(&intel_dp->psr.lock);
2572                 break;
2573         }
2574 }