git.itanic.dy.fi Git - linux-stable/blob - drivers/gpu/drm/i915/display/intel_psr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <drm/drm_atomic_helper.h>
  25 #include <drm/drm_damage_helper.h>
  26
  27 #include "display/intel_dp.h"
  28
  29 #include "i915_drv.h"
  30 #include "intel_atomic.h"
  31 #include "intel_crtc.h"
  32 #include "intel_de.h"
  33 #include "intel_display_types.h"
  34 #include "intel_dp_aux.h"
  35 #include "intel_hdmi.h"
  36 #include "intel_psr.h"
  37 #include "intel_snps_phy.h"
  38 #include "skl_universal_plane.h"
  39
  40 /**
  41  * DOC: Panel Self Refresh (PSR/SRD)
  42  *
  43  * Since Haswell Display controller supports Panel Self-Refresh on display
  44  * panels witch have a remote frame buffer (RFB) implemented according to PSR
  45  * spec in eDP1.3. PSR feature allows the display to go to lower standby states
  46  * when system is idle but display is on as it eliminates display refresh
  47  * request to DDR memory completely as long as the frame buffer for that
  48  * display is unchanged.
  49  *
  50  * Panel Self Refresh must be supported by both Hardware (source) and
  51  * Panel (sink).
  52  *
  53  * PSR saves power by caching the framebuffer in the panel RFB, which allows us
  54  * to power down the link and memory controller. For DSI panels the same idea
  55  * is called "manual mode".
  56  *
  57  * The implementation uses the hardware-based PSR support which automatically
  58  * enters/exits self-refresh mode. The hardware takes care of sending the
  59  * required DP aux message and could even retrain the link (that part isn't
  60  * enabled yet though). The hardware also keeps track of any frontbuffer
  61  * changes to know when to exit self-refresh mode again. Unfortunately that
  62  * part doesn't work too well, hence why the i915 PSR support uses the
  63  * software frontbuffer tracking to make sure it doesn't miss a screen
  64  * update. For this integration intel_psr_invalidate() and intel_psr_flush()
  65  * get called by the frontbuffer tracking code. Note that because of locking
  66  * issues the self-refresh re-enable code is done from a work queue, which
  67  * must be correctly synchronized/cancelled when shutting down the pipe."
  68  *
  69  * DC3CO (DC3 clock off)
  70  *
  71  * On top of PSR2, GEN12 adds a intermediate power savings state that turns
  72  * clock off automatically during PSR2 idle state.
  73  * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep
  74  * entry/exit allows the HW to enter a low-power state even when page flipping
  75  * periodically (for instance a 30fps video playback scenario).
  76  *
  77  * Every time a flips occurs PSR2 will get out of deep sleep state(if it was),
  78  * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6
  79  * frames, if no other flip occurs and the function above is executed, DC3CO is
  80  * disabled and PSR2 is configured to enter deep sleep, resetting again in case
  81  * of another flip.
  82  * Front buffer modifications do not trigger DC3CO activation on purpose as it
  83  * would bring a lot of complexity and most of the moderns systems will only
  84  * use page flips.
  85  */
  86
  87 static bool psr_global_enabled(struct intel_dp *intel_dp)
  88 {
  89         struct intel_connector *connector = intel_dp->attached_connector;
  90         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
  91
  92         switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
  93         case I915_PSR_DEBUG_DEFAULT:
  94                 if (i915->params.enable_psr == -1)
  95                         return connector->panel.vbt.psr.enable;
  96                 return i915->params.enable_psr;
  97         case I915_PSR_DEBUG_DISABLE:
  98                 return false;
  99         default:
 100                 return true;
 101         }
 102 }
 103
 104 static bool psr2_global_enabled(struct intel_dp *intel_dp)
 105 {
 106         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 107
 108         switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
 109         case I915_PSR_DEBUG_DISABLE:
 110         case I915_PSR_DEBUG_FORCE_PSR1:
 111                 return false;
 112         default:
 113                 if (i915->params.enable_psr == 1)
 114                         return false;
 115                 return true;
 116         }
 117 }
 118
 119 static void psr_irq_control(struct intel_dp *intel_dp)
 120 {
 121         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 122         enum transcoder trans_shift;
 123         i915_reg_t imr_reg;
 124         u32 mask, val;
 125
 126         /*
 127          * gen12+ has registers relative to transcoder and one per transcoder
 128          * using the same bit definition: handle it as TRANSCODER_EDP to force
 129          * 0 shift in bit definition
 130          */
 131         if (DISPLAY_VER(dev_priv) >= 12) {
 132                 trans_shift = 0;
 133                 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
 134         } else {
 135                 trans_shift = intel_dp->psr.transcoder;
 136                 imr_reg = EDP_PSR_IMR;
 137         }
 138
 139         mask = EDP_PSR_ERROR(trans_shift);
 140         if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
 141                 mask |= EDP_PSR_POST_EXIT(trans_shift) |
 142                         EDP_PSR_PRE_ENTRY(trans_shift);
 143
 144         /* Warning: it is masking/setting reserved bits too */
 145         val = intel_de_read(dev_priv, imr_reg);
 146         val &= ~EDP_PSR_TRANS_MASK(trans_shift);
 147         val |= ~mask;
 148         intel_de_write(dev_priv, imr_reg, val);
 149 }
 150
 151 static void psr_event_print(struct drm_i915_private *i915,
 152                             u32 val, bool psr2_enabled)
 153 {
 154         drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val);
 155         if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE)
 156                 drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n");
 157         if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled)
 158                 drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n");
 159         if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN)
 160                 drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n");
 161         if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN)
 162                 drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n");
 163         if (val & PSR_EVENT_GRAPHICS_RESET)
 164                 drm_dbg_kms(&i915->drm, "\tGraphics reset\n");
 165         if (val & PSR_EVENT_PCH_INTERRUPT)
 166                 drm_dbg_kms(&i915->drm, "\tPCH interrupt\n");
 167         if (val & PSR_EVENT_MEMORY_UP)
 168                 drm_dbg_kms(&i915->drm, "\tMemory up\n");
 169         if (val & PSR_EVENT_FRONT_BUFFER_MODIFY)
 170                 drm_dbg_kms(&i915->drm, "\tFront buffer modification\n");
 171         if (val & PSR_EVENT_WD_TIMER_EXPIRE)
 172                 drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n");
 173         if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE)
 174                 drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n");
 175         if (val & PSR_EVENT_REGISTER_UPDATE)
 176                 drm_dbg_kms(&i915->drm, "\tRegister updated\n");
 177         if (val & PSR_EVENT_HDCP_ENABLE)
 178                 drm_dbg_kms(&i915->drm, "\tHDCP enabled\n");
 179         if (val & PSR_EVENT_KVMR_SESSION_ENABLE)
 180                 drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n");
 181         if (val & PSR_EVENT_VBI_ENABLE)
 182                 drm_dbg_kms(&i915->drm, "\tVBI enabled\n");
 183         if (val & PSR_EVENT_LPSP_MODE_EXIT)
 184                 drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n");
 185         if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled)
 186                 drm_dbg_kms(&i915->drm, "\tPSR disabled\n");
 187 }
 188
 189 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
 190 {
 191         enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
 192         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 193         ktime_t time_ns =  ktime_get();
 194         enum transcoder trans_shift;
 195         i915_reg_t imr_reg;
 196
 197         if (DISPLAY_VER(dev_priv) >= 12) {
 198                 trans_shift = 0;
 199                 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
 200         } else {
 201                 trans_shift = intel_dp->psr.transcoder;
 202                 imr_reg = EDP_PSR_IMR;
 203         }
 204
 205         if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) {
 206                 intel_dp->psr.last_entry_attempt = time_ns;
 207                 drm_dbg_kms(&dev_priv->drm,
 208                             "[transcoder %s] PSR entry attempt in 2 vblanks\n",
 209                             transcoder_name(cpu_transcoder));
 210         }
 211
 212         if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) {
 213                 intel_dp->psr.last_exit = time_ns;
 214                 drm_dbg_kms(&dev_priv->drm,
 215                             "[transcoder %s] PSR exit completed\n",
 216                             transcoder_name(cpu_transcoder));
 217
 218                 if (DISPLAY_VER(dev_priv) >= 9) {
 219                         u32 val = intel_de_read(dev_priv,
 220                                                 PSR_EVENT(cpu_transcoder));
 221                         bool psr2_enabled = intel_dp->psr.psr2_enabled;
 222
 223                         intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder),
 224                                        val);
 225                         psr_event_print(dev_priv, val, psr2_enabled);
 226                 }
 227         }
 228
 229         if (psr_iir & EDP_PSR_ERROR(trans_shift)) {
 230                 u32 val;
 231
 232                 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n",
 233                          transcoder_name(cpu_transcoder));
 234
 235                 intel_dp->psr.irq_aux_error = true;
 236
 237                 /*
 238                  * If this interruption is not masked it will keep
 239                  * interrupting so fast that it prevents the scheduled
 240                  * work to run.
 241                  * Also after a PSR error, we don't want to arm PSR
 242                  * again so we don't care about unmask the interruption
 243                  * or unset irq_aux_error.
 244                  */
 245                 val = intel_de_read(dev_priv, imr_reg);
 246                 val |= EDP_PSR_ERROR(trans_shift);
 247                 intel_de_write(dev_priv, imr_reg, val);
 248
 249                 schedule_work(&intel_dp->psr.work);
 250         }
 251 }
 252
 253 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
 254 {
 255         u8 alpm_caps = 0;
 256
 257         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
 258                               &alpm_caps) != 1)
 259                 return false;
 260         return alpm_caps & DP_ALPM_CAP;
 261 }
 262
 263 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
 264 {
 265         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 266         u8 val = 8; /* assume the worst if we can't read the value */
 267
 268         if (drm_dp_dpcd_readb(&intel_dp->aux,
 269                               DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1)
 270                 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
 271         else
 272                 drm_dbg_kms(&i915->drm,
 273                             "Unable to get sink synchronization latency, assuming 8 frames\n");
 274         return val;
 275 }
 276
 277 static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
 278 {
 279         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 280         ssize_t r;
 281         u16 w;
 282         u8 y;
 283
 284         /* If sink don't have specific granularity requirements set legacy ones */
 285         if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
 286                 /* As PSR2 HW sends full lines, we do not care about x granularity */
 287                 w = 4;
 288                 y = 4;
 289                 goto exit;
 290         }
 291
 292         r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2);
 293         if (r != 2)
 294                 drm_dbg_kms(&i915->drm,
 295                             "Unable to read DP_PSR2_SU_X_GRANULARITY\n");
 296         /*
 297          * Spec says that if the value read is 0 the default granularity should
 298          * be used instead.
 299          */
 300         if (r != 2 || w == 0)
 301                 w = 4;
 302
 303         r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1);
 304         if (r != 1) {
 305                 drm_dbg_kms(&i915->drm,
 306                             "Unable to read DP_PSR2_SU_Y_GRANULARITY\n");
 307                 y = 4;
 308         }
 309         if (y == 0)
 310                 y = 1;
 311
 312 exit:
 313         intel_dp->psr.su_w_granularity = w;
 314         intel_dp->psr.su_y_granularity = y;
 315 }
 316
 317 void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 318 {
 319         struct drm_i915_private *dev_priv =
 320                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
 321
 322         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
 323                          sizeof(intel_dp->psr_dpcd));
 324
 325         if (!intel_dp->psr_dpcd[0])
 326                 return;
 327         drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n",
 328                     intel_dp->psr_dpcd[0]);
 329
 330         if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
 331                 drm_dbg_kms(&dev_priv->drm,
 332                             "PSR support not currently available for this panel\n");
 333                 return;
 334         }
 335
 336         if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
 337                 drm_dbg_kms(&dev_priv->drm,
 338                             "Panel lacks power state control, PSR cannot be enabled\n");
 339                 return;
 340         }
 341
 342         intel_dp->psr.sink_support = true;
 343         intel_dp->psr.sink_sync_latency =
 344                 intel_dp_get_sink_sync_latency(intel_dp);
 345
 346         if (DISPLAY_VER(dev_priv) >= 9 &&
 347             (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
 348                 bool y_req = intel_dp->psr_dpcd[1] &
 349                              DP_PSR2_SU_Y_COORDINATE_REQUIRED;
 350                 bool alpm = intel_dp_get_alpm_status(intel_dp);
 351
 352                 /*
 353                  * All panels that supports PSR version 03h (PSR2 +
 354                  * Y-coordinate) can handle Y-coordinates in VSC but we are
 355                  * only sure that it is going to be used when required by the
 356                  * panel. This way panel is capable to do selective update
 357                  * without a aux frame sync.
 358                  *
 359                  * To support PSR version 02h and PSR version 03h without
 360                  * Y-coordinate requirement panels we would need to enable
 361                  * GTC first.
 362                  */
 363                 intel_dp->psr.sink_psr2_support = y_req && alpm;
 364                 drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n",
 365                             intel_dp->psr.sink_psr2_support ? "" : "not ");
 366
 367                 if (intel_dp->psr.sink_psr2_support) {
 368                         intel_dp->psr.colorimetry_support =
 369                                 intel_dp_get_colorimetry_status(intel_dp);
 370                         intel_dp_get_su_granularity(intel_dp);
 371                 }
 372         }
 373 }
 374
 375 static void intel_psr_enable_sink(struct intel_dp *intel_dp)
 376 {
 377         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 378         u8 dpcd_val = DP_PSR_ENABLE;
 379
 380         /* Enable ALPM at sink for psr2 */
 381         if (intel_dp->psr.psr2_enabled) {
 382                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
 383                                    DP_ALPM_ENABLE |
 384                                    DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
 385
 386                 dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
 387         } else {
 388                 if (intel_dp->psr.link_standby)
 389                         dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
 390
 391                 if (DISPLAY_VER(dev_priv) >= 8)
 392                         dpcd_val |= DP_PSR_CRC_VERIFICATION;
 393         }
 394
 395         if (intel_dp->psr.req_psr2_sdp_prior_scanline)
 396                 dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE;
 397
 398         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
 399
 400         drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
 401 }
 402
 403 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
 404 {
 405         struct intel_connector *connector = intel_dp->attached_connector;
 406         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 407         u32 val = 0;
 408
 409         if (DISPLAY_VER(dev_priv) >= 11)
 410                 val |= EDP_PSR_TP4_TIME_0US;
 411
 412         if (dev_priv->params.psr_safest_params) {
 413                 val |= EDP_PSR_TP1_TIME_2500us;
 414                 val |= EDP_PSR_TP2_TP3_TIME_2500us;
 415                 goto check_tp3_sel;
 416         }
 417
 418         if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0)
 419                 val |= EDP_PSR_TP1_TIME_0us;
 420         else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100)
 421                 val |= EDP_PSR_TP1_TIME_100us;
 422         else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500)
 423                 val |= EDP_PSR_TP1_TIME_500us;
 424         else
 425                 val |= EDP_PSR_TP1_TIME_2500us;
 426
 427         if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0)
 428                 val |= EDP_PSR_TP2_TP3_TIME_0us;
 429         else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100)
 430                 val |= EDP_PSR_TP2_TP3_TIME_100us;
 431         else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500)
 432                 val |= EDP_PSR_TP2_TP3_TIME_500us;
 433         else
 434                 val |= EDP_PSR_TP2_TP3_TIME_2500us;
 435
 436 check_tp3_sel:
 437         if (intel_dp_source_supports_tps3(dev_priv) &&
 438             drm_dp_tps3_supported(intel_dp->dpcd))
 439                 val |= EDP_PSR_TP1_TP3_SEL;
 440         else
 441                 val |= EDP_PSR_TP1_TP2_SEL;
 442
 443         return val;
 444 }
 445
 446 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
 447 {
 448         struct intel_connector *connector = intel_dp->attached_connector;
 449         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 450         int idle_frames;
 451
 452         /* Let's use 6 as the minimum to cover all known cases including the
 453          * off-by-one issue that HW has in some cases.
 454          */
 455         idle_frames = max(6, connector->panel.vbt.psr.idle_frames);
 456         idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1);
 457
 458         if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf))
 459                 idle_frames = 0xf;
 460
 461         return idle_frames;
 462 }
 463
 464 static void hsw_activate_psr1(struct intel_dp *intel_dp)
 465 {
 466         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 467         u32 max_sleep_time = 0x1f;
 468         u32 val = EDP_PSR_ENABLE;
 469
 470         val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT;
 471
 472         val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
 473         if (IS_HASWELL(dev_priv))
 474                 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 475
 476         if (intel_dp->psr.link_standby)
 477                 val |= EDP_PSR_LINK_STANDBY;
 478
 479         val |= intel_psr1_get_tp_time(intel_dp);
 480
 481         if (DISPLAY_VER(dev_priv) >= 8)
 482                 val |= EDP_PSR_CRC_ENABLE;
 483
 484         val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) &
 485                 EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK);
 486         intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val);
 487 }
 488
 489 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
 490 {
 491         struct intel_connector *connector = intel_dp->attached_connector;
 492         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 493         u32 val = 0;
 494
 495         if (dev_priv->params.psr_safest_params)
 496                 return EDP_PSR2_TP2_TIME_2500us;
 497
 498         if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
 499             connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
 500                 val |= EDP_PSR2_TP2_TIME_50us;
 501         else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
 502                 val |= EDP_PSR2_TP2_TIME_100us;
 503         else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
 504                 val |= EDP_PSR2_TP2_TIME_500us;
 505         else
 506                 val |= EDP_PSR2_TP2_TIME_2500us;
 507
 508         return val;
 509 }
 510
 511 static void hsw_activate_psr2(struct intel_dp *intel_dp)
 512 {
 513         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 514         u32 val = EDP_PSR2_ENABLE;
 515
 516         val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
 517
 518         if (!IS_ALDERLAKE_P(dev_priv))
 519                 val |= EDP_SU_TRACK_ENABLE;
 520
 521         if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
 522                 val |= EDP_Y_COORDINATE_ENABLE;
 523
 524         val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp->psr.sink_sync_latency + 1, 2));
 525         val |= intel_psr2_get_tp_time(intel_dp);
 526
 527         /* Wa_22012278275:adl-p */
 528         if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
 529                 static const u8 map[] = {
 530                         2, /* 5 lines */
 531                         1, /* 6 lines */
 532                         0, /* 7 lines */
 533                         3, /* 8 lines */
 534                         6, /* 9 lines */
 535                         5, /* 10 lines */
 536                         4, /* 11 lines */
 537                         7, /* 12 lines */
 538                 };
 539                 /*
 540                  * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see
 541                  * comments bellow for more information
 542                  */
 543                 u32 tmp, lines = 7;
 544
 545                 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
 546
 547                 tmp = map[lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES];
 548                 tmp = tmp << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT;
 549                 val |= tmp;
 550
 551                 tmp = map[lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
 552                 tmp = tmp << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT;
 553                 val |= tmp;
 554         } else if (DISPLAY_VER(dev_priv) >= 12) {
 555                 /*
 556                  * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default
 557                  * values from BSpec. In order to setting an optimal power
 558                  * consumption, lower than 4k resoluition mode needs to decrese
 559                  * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution
 560                  * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE.
 561                  */
 562                 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
 563                 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7);
 564                 val |= TGL_EDP_PSR2_FAST_WAKE(7);
 565         } else if (DISPLAY_VER(dev_priv) >= 9) {
 566                 val |= EDP_PSR2_IO_BUFFER_WAKE(7);
 567                 val |= EDP_PSR2_FAST_WAKE(7);
 568         }
 569
 570         if (intel_dp->psr.req_psr2_sdp_prior_scanline)
 571                 val |= EDP_PSR2_SU_SDP_SCANLINE;
 572
 573         if (intel_dp->psr.psr2_sel_fetch_enabled) {
 574                 u32 tmp;
 575
 576                 /* Wa_1408330847 */
 577                 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 578                         intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
 579                                      DIS_RAM_BYPASS_PSR2_MAN_TRACK,
 580                                      DIS_RAM_BYPASS_PSR2_MAN_TRACK);
 581
 582                 tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
 583                 drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));
 584         } else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
 585                 intel_de_write(dev_priv,
 586                                PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0);
 587         }
 588
 589         /*
 590          * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is
 591          * recommending keep this bit unset while PSR2 is enabled.
 592          */
 593         intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0);
 594
 595         intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
 596 }
 597
 598 static bool
 599 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans)
 600 {
 601         if (IS_ALDERLAKE_P(dev_priv))
 602                 return trans == TRANSCODER_A || trans == TRANSCODER_B;
 603         else if (DISPLAY_VER(dev_priv) >= 12)
 604                 return trans == TRANSCODER_A;
 605         else
 606                 return trans == TRANSCODER_EDP;
 607 }
 608
 609 static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)
 610 {
 611         if (!cstate || !cstate->hw.active)
 612                 return 0;
 613
 614         return DIV_ROUND_UP(1000 * 1000,
 615                             drm_mode_vrefresh(&cstate->hw.adjusted_mode));
 616 }
 617
 618 static void psr2_program_idle_frames(struct intel_dp *intel_dp,
 619                                      u32 idle_frames)
 620 {
 621         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 622         u32 val;
 623
 624         idle_frames <<=  EDP_PSR2_IDLE_FRAME_SHIFT;
 625         val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder));
 626         val &= ~EDP_PSR2_IDLE_FRAME_MASK;
 627         val |= idle_frames;
 628         intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
 629 }
 630
 631 static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp)
 632 {
 633         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 634
 635         psr2_program_idle_frames(intel_dp, 0);
 636         intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO);
 637 }
 638
 639 static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp)
 640 {
 641         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 642
 643         intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 644         psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp));
 645 }
 646
 647 static void tgl_dc3co_disable_work(struct work_struct *work)
 648 {
 649         struct intel_dp *intel_dp =
 650                 container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
 651
 652         mutex_lock(&intel_dp->psr.lock);
 653         /* If delayed work is pending, it is not idle */
 654         if (delayed_work_pending(&intel_dp->psr.dc3co_work))
 655                 goto unlock;
 656
 657         tgl_psr2_disable_dc3co(intel_dp);
 658 unlock:
 659         mutex_unlock(&intel_dp->psr.lock);
 660 }
 661
 662 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp)
 663 {
 664         if (!intel_dp->psr.dc3co_exitline)
 665                 return;
 666
 667         cancel_delayed_work(&intel_dp->psr.dc3co_work);
 668         /* Before PSR2 exit disallow dc3co*/
 669         tgl_psr2_disable_dc3co(intel_dp);
 670 }
 671
 672 static bool
 673 dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp,
 674                               struct intel_crtc_state *crtc_state)
 675 {
 676         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 677         enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
 678         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 679         enum port port = dig_port->base.port;
 680
 681         if (IS_ALDERLAKE_P(dev_priv))
 682                 return pipe <= PIPE_B && port <= PORT_B;
 683         else
 684                 return pipe == PIPE_A && port == PORT_A;
 685 }
 686
 687 static void
 688 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
 689                                   struct intel_crtc_state *crtc_state)
 690 {
 691         const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay;
 692         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 693         u32 exit_scanlines;
 694
 695         /*
 696          * FIXME: Due to the changed sequence of activating/deactivating DC3CO,
 697          * disable DC3CO until the changed dc3co activating/deactivating sequence
 698          * is applied. B.Specs:49196
 699          */
 700         return;
 701
 702         /*
 703          * DMC's DC3CO exit mechanism has an issue with Selective Fecth
 704          * TODO: when the issue is addressed, this restriction should be removed.
 705          */
 706         if (crtc_state->enable_psr2_sel_fetch)
 707                 return;
 708
 709         if (!(dev_priv->dmc.allowed_dc_mask & DC_STATE_EN_DC3CO))
 710                 return;
 711
 712         if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
 713                 return;
 714
 715         /* Wa_16011303918:adl-p */
 716         if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 717                 return;
 718
 719         /*
 720          * DC3CO Exit time 200us B.Spec 49196
 721          * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
 722          */
 723         exit_scanlines =
 724                 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1;
 725
 726         if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay))
 727                 return;
 728
 729         crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;
 730 }
 731
 732 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
 733                                               struct intel_crtc_state *crtc_state)
 734 {
 735         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 736
 737         if (!dev_priv->params.enable_psr2_sel_fetch &&
 738             intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
 739                 drm_dbg_kms(&dev_priv->drm,
 740                             "PSR2 sel fetch not enabled, disabled by parameter\n");
 741                 return false;
 742         }
 743
 744         if (crtc_state->uapi.async_flip) {
 745                 drm_dbg_kms(&dev_priv->drm,
 746                             "PSR2 sel fetch not enabled, async flip enabled\n");
 747                 return false;
 748         }
 749
 750         /* Wa_14010254185 Wa_14010103792 */
 751         if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
 752                 drm_dbg_kms(&dev_priv->drm,
 753                             "PSR2 sel fetch not enabled, missing the implementation of WAs\n");
 754                 return false;
 755         }
 756
 757         return crtc_state->enable_psr2_sel_fetch = true;
 758 }
 759
 760 static bool psr2_granularity_check(struct intel_dp *intel_dp,
 761                                    struct intel_crtc_state *crtc_state)
 762 {
 763         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 764         const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 765         const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
 766         u16 y_granularity = 0;
 767
 768         /* PSR2 HW only send full lines so we only need to validate the width */
 769         if (crtc_hdisplay % intel_dp->psr.su_w_granularity)
 770                 return false;
 771
 772         if (crtc_vdisplay % intel_dp->psr.su_y_granularity)
 773                 return false;
 774
 775         /* HW tracking is only aligned to 4 lines */
 776         if (!crtc_state->enable_psr2_sel_fetch)
 777                 return intel_dp->psr.su_y_granularity == 4;
 778
 779         /*
 780          * adl_p has 1 line granularity. For other platforms with SW tracking we
 781          * can adjust the y coordinates to match sink requirement if multiple of
 782          * 4.
 783          */
 784         if (IS_ALDERLAKE_P(dev_priv))
 785                 y_granularity = intel_dp->psr.su_y_granularity;
 786         else if (intel_dp->psr.su_y_granularity <= 2)
 787                 y_granularity = 4;
 788         else if ((intel_dp->psr.su_y_granularity % 4) == 0)
 789                 y_granularity = intel_dp->psr.su_y_granularity;
 790
 791         if (y_granularity == 0 || crtc_vdisplay % y_granularity)
 792                 return false;
 793
 794         crtc_state->su_y_granularity = y_granularity;
 795         return true;
 796 }
 797
 798 static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp,
 799                                                         struct intel_crtc_state *crtc_state)
 800 {
 801         const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode;
 802         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 803         u32 hblank_total, hblank_ns, req_ns;
 804
 805         hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start;
 806         hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock);
 807
 808         /* From spec: (72 / number of lanes) * 1000 / symbol clock frequency MHz */
 809         req_ns = (72 / crtc_state->lane_count) * 1000 / (crtc_state->port_clock / 1000);
 810
 811         if ((hblank_ns - req_ns) > 100)
 812                 return true;
 813
 814         if (DISPLAY_VER(dev_priv) < 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b)
 815                 return false;
 816
 817         crtc_state->req_psr2_sdp_prior_scanline = true;
 818         return true;
 819 }
 820
 821 static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 822                                     struct intel_crtc_state *crtc_state)
 823 {
 824         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 825         int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 826         int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
 827         int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
 828
 829         if (!intel_dp->psr.sink_psr2_support)
 830                 return false;
 831
 832         /* JSL and EHL only supports eDP 1.3 */
 833         if (IS_JSL_EHL(dev_priv)) {
 834                 drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n");
 835                 return false;
 836         }
 837
 838         /* Wa_16011181250 */
 839         if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 840             IS_DG2(dev_priv)) {
 841                 drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this platform\n");
 842                 return false;
 843         }
 844
 845         if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
 846                 drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n");
 847                 return false;
 848         }
 849
 850         if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) {
 851                 drm_dbg_kms(&dev_priv->drm,
 852                             "PSR2 not supported in transcoder %s\n",
 853                             transcoder_name(crtc_state->cpu_transcoder));
 854                 return false;
 855         }
 856
 857         if (!psr2_global_enabled(intel_dp)) {
 858                 drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n");
 859                 return false;
 860         }
 861
 862         /*
 863          * DSC and PSR2 cannot be enabled simultaneously. If a requested
 864          * resolution requires DSC to be enabled, priority is given to DSC
 865          * over PSR2.
 866          */
 867         if (crtc_state->dsc.compression_enable) {
 868                 drm_dbg_kms(&dev_priv->drm,
 869                             "PSR2 cannot be enabled since DSC is enabled\n");
 870                 return false;
 871         }
 872
 873         if (crtc_state->crc_enabled) {
 874                 drm_dbg_kms(&dev_priv->drm,
 875                             "PSR2 not enabled because it would inhibit pipe CRC calculation\n");
 876                 return false;
 877         }
 878
 879         if (DISPLAY_VER(dev_priv) >= 12) {
 880                 psr_max_h = 5120;
 881                 psr_max_v = 3200;
 882                 max_bpp = 30;
 883         } else if (DISPLAY_VER(dev_priv) >= 10) {
 884                 psr_max_h = 4096;
 885                 psr_max_v = 2304;
 886                 max_bpp = 24;
 887         } else if (DISPLAY_VER(dev_priv) == 9) {
 888                 psr_max_h = 3640;
 889                 psr_max_v = 2304;
 890                 max_bpp = 24;
 891         }
 892
 893         if (crtc_state->pipe_bpp > max_bpp) {
 894                 drm_dbg_kms(&dev_priv->drm,
 895                             "PSR2 not enabled, pipe bpp %d > max supported %d\n",
 896                             crtc_state->pipe_bpp, max_bpp);
 897                 return false;
 898         }
 899
 900         /* Wa_16011303918:adl-p */
 901         if (crtc_state->vrr.enable &&
 902             IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
 903                 drm_dbg_kms(&dev_priv->drm,
 904                             "PSR2 not enabled, not compatible with HW stepping + VRR\n");
 905                 return false;
 906         }
 907
 908         if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) {
 909                 drm_dbg_kms(&dev_priv->drm,
 910                             "PSR2 not enabled, PSR2 SDP indication do not fit in hblank\n");
 911                 return false;
 912         }
 913
 914         if (HAS_PSR2_SEL_FETCH(dev_priv)) {
 915                 if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
 916                     !HAS_PSR_HW_TRACKING(dev_priv)) {
 917                         drm_dbg_kms(&dev_priv->drm,
 918                                     "PSR2 not enabled, selective fetch not valid and no HW tracking available\n");
 919                         return false;
 920                 }
 921         }
 922
 923         /* Wa_2209313811 */
 924         if (!crtc_state->enable_psr2_sel_fetch &&
 925             IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
 926                 drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n");
 927                 goto unsupported;
 928         }
 929
 930         if (!psr2_granularity_check(intel_dp, crtc_state)) {
 931                 drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n");
 932                 goto unsupported;
 933         }
 934
 935         if (!crtc_state->enable_psr2_sel_fetch &&
 936             (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) {
 937                 drm_dbg_kms(&dev_priv->drm,
 938                             "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n",
 939                             crtc_hdisplay, crtc_vdisplay,
 940                             psr_max_h, psr_max_v);
 941                 goto unsupported;
 942         }
 943
 944         tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
 945         return true;
 946
 947 unsupported:
 948         crtc_state->enable_psr2_sel_fetch = false;
 949         return false;
 950 }
 951
 952 void intel_psr_compute_config(struct intel_dp *intel_dp,
 953                               struct intel_crtc_state *crtc_state,
 954                               struct drm_connector_state *conn_state)
 955 {
 956         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 957         const struct drm_display_mode *adjusted_mode =
 958                 &crtc_state->hw.adjusted_mode;
 959         int psr_setup_time;
 960
 961         /*
 962          * Current PSR panels dont work reliably with VRR enabled
 963          * So if VRR is enabled, do not enable PSR.
 964          */
 965         if (crtc_state->vrr.enable)
 966                 return;
 967
 968         if (!CAN_PSR(intel_dp))
 969                 return;
 970
 971         if (!psr_global_enabled(intel_dp)) {
 972                 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
 973                 return;
 974         }
 975
 976         if (intel_dp->psr.sink_not_reliable) {
 977                 drm_dbg_kms(&dev_priv->drm,
 978                             "PSR sink implementation is not reliable\n");
 979                 return;
 980         }
 981
 982         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
 983                 drm_dbg_kms(&dev_priv->drm,
 984                             "PSR condition failed: Interlaced mode enabled\n");
 985                 return;
 986         }
 987
 988         psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
 989         if (psr_setup_time < 0) {
 990                 drm_dbg_kms(&dev_priv->drm,
 991                             "PSR condition failed: Invalid PSR setup time (0x%02x)\n",
 992                             intel_dp->psr_dpcd[1]);
 993                 return;
 994         }
 995
 996         if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
 997             adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
 998                 drm_dbg_kms(&dev_priv->drm,
 999                             "PSR condition failed: PSR setup time (%d us) too long\n",
1000                             psr_setup_time);
1001                 return;
1002         }
1003
1004         crtc_state->has_psr = true;
1005         crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
1006
1007         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1008         intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
1009                                      &crtc_state->psr_vsc);
1010 }
1011
1012 void intel_psr_get_config(struct intel_encoder *encoder,
1013                           struct intel_crtc_state *pipe_config)
1014 {
1015         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1016         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1017         struct intel_dp *intel_dp;
1018         u32 val;
1019
1020         if (!dig_port)
1021                 return;
1022
1023         intel_dp = &dig_port->dp;
1024         if (!CAN_PSR(intel_dp))
1025                 return;
1026
1027         mutex_lock(&intel_dp->psr.lock);
1028         if (!intel_dp->psr.enabled)
1029                 goto unlock;
1030
1031         /*
1032          * Not possible to read EDP_PSR/PSR2_CTL registers as it is
1033          * enabled/disabled because of frontbuffer tracking and others.
1034          */
1035         pipe_config->has_psr = true;
1036         pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
1037         pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1038
1039         if (!intel_dp->psr.psr2_enabled)
1040                 goto unlock;
1041
1042         if (HAS_PSR2_SEL_FETCH(dev_priv)) {
1043                 val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
1044                 if (val & PSR2_MAN_TRK_CTL_ENABLE)
1045                         pipe_config->enable_psr2_sel_fetch = true;
1046         }
1047
1048         if (DISPLAY_VER(dev_priv) >= 12) {
1049                 val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder));
1050                 val &= EXITLINE_MASK;
1051                 pipe_config->dc3co_exitline = val;
1052         }
1053 unlock:
1054         mutex_unlock(&intel_dp->psr.lock);
1055 }
1056
1057 static void intel_psr_activate(struct intel_dp *intel_dp)
1058 {
1059         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1060         enum transcoder transcoder = intel_dp->psr.transcoder;
1061
1062         if (transcoder_has_psr2(dev_priv, transcoder))
1063                 drm_WARN_ON(&dev_priv->drm,
1064                             intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE);
1065
1066         drm_WARN_ON(&dev_priv->drm,
1067                     intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE);
1068         drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active);
1069         lockdep_assert_held(&intel_dp->psr.lock);
1070
1071         /* psr1 and psr2 are mutually exclusive.*/
1072         if (intel_dp->psr.psr2_enabled)
1073                 hsw_activate_psr2(intel_dp);
1074         else
1075                 hsw_activate_psr1(intel_dp);
1076
1077         intel_dp->psr.active = true;
1078 }
1079
1080 static u32 wa_16013835468_bit_get(struct intel_dp *intel_dp)
1081 {
1082         switch (intel_dp->psr.pipe) {
1083         case PIPE_A:
1084                 return LATENCY_REPORTING_REMOVED_PIPE_A;
1085         case PIPE_B:
1086                 return LATENCY_REPORTING_REMOVED_PIPE_B;
1087         case PIPE_C:
1088                 return LATENCY_REPORTING_REMOVED_PIPE_C;
1089         default:
1090                 MISSING_CASE(intel_dp->psr.pipe);
1091                 return 0;
1092         }
1093 }
1094
1095 static void intel_psr_enable_source(struct intel_dp *intel_dp,
1096                                     const struct intel_crtc_state *crtc_state)
1097 {
1098         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1099         enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1100         u32 mask;
1101
1102         /*
1103          * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
1104          * mask LPSP to avoid dependency on other drivers that might block
1105          * runtime_pm besides preventing  other hw tracking issues now we
1106          * can rely on frontbuffer tracking.
1107          */
1108         mask = EDP_PSR_DEBUG_MASK_MEMUP |
1109                EDP_PSR_DEBUG_MASK_HPD |
1110                EDP_PSR_DEBUG_MASK_LPSP |
1111                EDP_PSR_DEBUG_MASK_MAX_SLEEP;
1112
1113         if (DISPLAY_VER(dev_priv) < 11)
1114                 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
1115
1116         intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder),
1117                        mask);
1118
1119         psr_irq_control(intel_dp);
1120
1121         if (intel_dp->psr.dc3co_exitline) {
1122                 u32 val;
1123
1124                 /*
1125                  * TODO: if future platforms supports DC3CO in more than one
1126                  * transcoder, EXITLINE will need to be unset when disabling PSR
1127                  */
1128                 val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder));
1129                 val &= ~EXITLINE_MASK;
1130                 val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT;
1131                 val |= EXITLINE_ENABLE;
1132                 intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val);
1133         }
1134
1135         if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv))
1136                 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,
1137                              intel_dp->psr.psr2_sel_fetch_enabled ?
1138                              IGNORE_PSR2_HW_TRACKING : 0);
1139
1140         if (intel_dp->psr.psr2_enabled) {
1141                 if (DISPLAY_VER(dev_priv) == 9)
1142                         intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
1143                                      PSR2_VSC_ENABLE_PROG_HEADER |
1144                                      PSR2_ADD_VERTICAL_LINE_COUNT);
1145
1146                 /*
1147                  * Wa_16014451276:adlp
1148                  * All supported adlp panels have 1-based X granularity, this may
1149                  * cause issues if non-supported panels are used.
1150                  */
1151                 if (IS_ALDERLAKE_P(dev_priv))
1152                         intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
1153                                      ADLP_1_BASED_X_GRANULARITY);
1154
1155                 /* Wa_16011168373:adl-p */
1156                 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
1157                         intel_de_rmw(dev_priv,
1158                                      TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
1159                                      TRANS_SET_CONTEXT_LATENCY_MASK,
1160                                      TRANS_SET_CONTEXT_LATENCY_VALUE(1));
1161
1162                 /* Wa_16012604467:adlp */
1163                 if (IS_ALDERLAKE_P(dev_priv))
1164                         intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0,
1165                                      CLKGATE_DIS_MISC_DMASC_GATING_DIS);
1166
1167                 /* Wa_16013835468:tgl[b0+], dg1 */
1168                 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) ||
1169                     IS_DG1(dev_priv)) {
1170                         u16 vtotal, vblank;
1171
1172                         vtotal = crtc_state->uapi.adjusted_mode.crtc_vtotal -
1173                                  crtc_state->uapi.adjusted_mode.crtc_vdisplay;
1174                         vblank = crtc_state->uapi.adjusted_mode.crtc_vblank_end -
1175                                  crtc_state->uapi.adjusted_mode.crtc_vblank_start;
1176                         if (vblank > vtotal)
1177                                 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0,
1178                                              wa_16013835468_bit_get(intel_dp));
1179                 }
1180         }
1181 }
1182
1183 static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
1184 {
1185         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1186         u32 val;
1187
1188         /*
1189          * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
1190          * will still keep the error set even after the reset done in the
1191          * irq_preinstall and irq_uninstall hooks.
1192          * And enabling in this situation cause the screen to freeze in the
1193          * first time that PSR HW tries to activate so lets keep PSR disabled
1194          * to avoid any rendering problems.
1195          */
1196         if (DISPLAY_VER(dev_priv) >= 12) {
1197                 val = intel_de_read(dev_priv,
1198                                     TRANS_PSR_IIR(intel_dp->psr.transcoder));
1199                 val &= EDP_PSR_ERROR(0);
1200         } else {
1201                 val = intel_de_read(dev_priv, EDP_PSR_IIR);
1202                 val &= EDP_PSR_ERROR(intel_dp->psr.transcoder);
1203         }
1204         if (val) {
1205                 intel_dp->psr.sink_not_reliable = true;
1206                 drm_dbg_kms(&dev_priv->drm,
1207                             "PSR interruption error set, not enabling PSR\n");
1208                 return false;
1209         }
1210
1211         return true;
1212 }
1213
1214 static void intel_psr_enable_locked(struct intel_dp *intel_dp,
1215                                     const struct intel_crtc_state *crtc_state)
1216 {
1217         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1218         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1219         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
1220         struct intel_encoder *encoder = &dig_port->base;
1221         u32 val;
1222
1223         drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
1224
1225         intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
1226         intel_dp->psr.busy_frontbuffer_bits = 0;
1227         intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
1228         intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
1229         /* DC5/DC6 requires at least 6 idle frames */
1230         val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
1231         intel_dp->psr.dc3co_exit_delay = val;
1232         intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
1233         intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
1234         intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
1235         intel_dp->psr.req_psr2_sdp_prior_scanline =
1236                 crtc_state->req_psr2_sdp_prior_scanline;
1237
1238         if (!psr_interrupt_error_check(intel_dp))
1239                 return;
1240
1241         drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
1242                     intel_dp->psr.psr2_enabled ? "2" : "1");
1243         intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc);
1244         intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
1245         intel_psr_enable_sink(intel_dp);
1246         intel_psr_enable_source(intel_dp, crtc_state);
1247         intel_dp->psr.enabled = true;
1248         intel_dp->psr.paused = false;
1249
1250         intel_psr_activate(intel_dp);
1251 }
1252
1253 static void intel_psr_exit(struct intel_dp *intel_dp)
1254 {
1255         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1256         u32 val;
1257
1258         if (!intel_dp->psr.active) {
1259                 if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) {
1260                         val = intel_de_read(dev_priv,
1261                                             EDP_PSR2_CTL(intel_dp->psr.transcoder));
1262                         drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE);
1263                 }
1264
1265                 val = intel_de_read(dev_priv,
1266                                     EDP_PSR_CTL(intel_dp->psr.transcoder));
1267                 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE);
1268
1269                 return;
1270         }
1271
1272         if (intel_dp->psr.psr2_enabled) {
1273                 tgl_disallow_dc3co_on_psr2_exit(intel_dp);
1274                 val = intel_de_read(dev_priv,
1275                                     EDP_PSR2_CTL(intel_dp->psr.transcoder));
1276                 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE));
1277                 val &= ~EDP_PSR2_ENABLE;
1278                 intel_de_write(dev_priv,
1279                                EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
1280         } else {
1281                 val = intel_de_read(dev_priv,
1282                                     EDP_PSR_CTL(intel_dp->psr.transcoder));
1283                 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE));
1284                 val &= ~EDP_PSR_ENABLE;
1285                 intel_de_write(dev_priv,
1286                                EDP_PSR_CTL(intel_dp->psr.transcoder), val);
1287         }
1288         intel_dp->psr.active = false;
1289 }
1290
1291 static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)
1292 {
1293         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1294         i915_reg_t psr_status;
1295         u32 psr_status_mask;
1296
1297         if (intel_dp->psr.psr2_enabled) {
1298                 psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
1299                 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
1300         } else {
1301                 psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder);
1302                 psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
1303         }
1304
1305         /* Wait till PSR is idle */
1306         if (intel_de_wait_for_clear(dev_priv, psr_status,
1307                                     psr_status_mask, 2000))
1308                 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n");
1309 }
1310
1311 static void intel_psr_disable_locked(struct intel_dp *intel_dp)
1312 {
1313         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1314         enum phy phy = intel_port_to_phy(dev_priv,
1315                                          dp_to_dig_port(intel_dp)->base.port);
1316
1317         lockdep_assert_held(&intel_dp->psr.lock);
1318
1319         if (!intel_dp->psr.enabled)
1320                 return;
1321
1322         drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
1323                     intel_dp->psr.psr2_enabled ? "2" : "1");
1324
1325         intel_psr_exit(intel_dp);
1326         intel_psr_wait_exit_locked(intel_dp);
1327
1328         /* Wa_1408330847 */
1329         if (intel_dp->psr.psr2_sel_fetch_enabled &&
1330             IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
1331                 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
1332                              DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
1333
1334         if (intel_dp->psr.psr2_enabled) {
1335                 /* Wa_16011168373:adl-p */
1336                 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
1337                         intel_de_rmw(dev_priv,
1338                                      TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
1339                                      TRANS_SET_CONTEXT_LATENCY_MASK, 0);
1340
1341                 /* Wa_16012604467:adlp */
1342                 if (IS_ALDERLAKE_P(dev_priv))
1343                         intel_de_rmw(dev_priv, CLKGATE_DIS_MISC,
1344                                      CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0);
1345
1346                 /* Wa_16013835468:tgl[b0+], dg1 */
1347                 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) ||
1348                     IS_DG1(dev_priv))
1349                         intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
1350                                      wa_16013835468_bit_get(intel_dp), 0);
1351         }
1352
1353         intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
1354
1355         /* Disable PSR on Sink */
1356         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
1357
1358         if (intel_dp->psr.psr2_enabled)
1359                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0);
1360
1361         intel_dp->psr.enabled = false;
1362         intel_dp->psr.psr2_enabled = false;
1363         intel_dp->psr.psr2_sel_fetch_enabled = false;
1364         intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
1365 }
1366
1367 /**
1368  * intel_psr_disable - Disable PSR
1369  * @intel_dp: Intel DP
1370  * @old_crtc_state: old CRTC state
1371  *
1372  * This function needs to be called before disabling pipe.
1373  */
1374 void intel_psr_disable(struct intel_dp *intel_dp,
1375                        const struct intel_crtc_state *old_crtc_state)
1376 {
1377         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1378
1379         if (!old_crtc_state->has_psr)
1380                 return;
1381
1382         if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp)))
1383                 return;
1384
1385         mutex_lock(&intel_dp->psr.lock);
1386
1387         intel_psr_disable_locked(intel_dp);
1388
1389         mutex_unlock(&intel_dp->psr.lock);
1390         cancel_work_sync(&intel_dp->psr.work);
1391         cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
1392 }
1393
1394 /**
1395  * intel_psr_pause - Pause PSR
1396  * @intel_dp: Intel DP
1397  *
1398  * This function need to be called after enabling psr.
1399  */
1400 void intel_psr_pause(struct intel_dp *intel_dp)
1401 {
1402         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1403         struct intel_psr *psr = &intel_dp->psr;
1404
1405         if (!CAN_PSR(intel_dp))
1406                 return;
1407
1408         mutex_lock(&psr->lock);
1409
1410         if (!psr->enabled) {
1411                 mutex_unlock(&psr->lock);
1412                 return;
1413         }
1414
1415         /* If we ever hit this, we will need to add refcount to pause/resume */
1416         drm_WARN_ON(&dev_priv->drm, psr->paused);
1417
1418         intel_psr_exit(intel_dp);
1419         intel_psr_wait_exit_locked(intel_dp);
1420         psr->paused = true;
1421
1422         mutex_unlock(&psr->lock);
1423
1424         cancel_work_sync(&psr->work);
1425         cancel_delayed_work_sync(&psr->dc3co_work);
1426 }
1427
1428 /**
1429  * intel_psr_resume - Resume PSR
1430  * @intel_dp: Intel DP
1431  *
1432  * This function need to be called after pausing psr.
1433  */
1434 void intel_psr_resume(struct intel_dp *intel_dp)
1435 {
1436         struct intel_psr *psr = &intel_dp->psr;
1437
1438         if (!CAN_PSR(intel_dp))
1439                 return;
1440
1441         mutex_lock(&psr->lock);
1442
1443         if (!psr->paused)
1444                 goto unlock;
1445
1446         psr->paused = false;
1447         intel_psr_activate(intel_dp);
1448
1449 unlock:
1450         mutex_unlock(&psr->lock);
1451 }
1452
1453 static u32 man_trk_ctl_enable_bit_get(struct drm_i915_private *dev_priv)
1454 {
1455         return IS_ALDERLAKE_P(dev_priv) ? 0 : PSR2_MAN_TRK_CTL_ENABLE;
1456 }
1457
1458 static u32 man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private *dev_priv)
1459 {
1460         return IS_ALDERLAKE_P(dev_priv) ?
1461                ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME :
1462                PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
1463 }
1464
1465 static u32 man_trk_ctl_partial_frame_bit_get(struct drm_i915_private *dev_priv)
1466 {
1467         return IS_ALDERLAKE_P(dev_priv) ?
1468                ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE :
1469                PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
1470 }
1471
1472 static u32 man_trk_ctl_continuos_full_frame(struct drm_i915_private *dev_priv)
1473 {
1474         return IS_ALDERLAKE_P(dev_priv) ?
1475                ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME :
1476                PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME;
1477 }
1478
1479 static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
1480 {
1481         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1482
1483         if (intel_dp->psr.psr2_sel_fetch_enabled)
1484                 intel_de_write(dev_priv,
1485                                PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
1486                                man_trk_ctl_enable_bit_get(dev_priv) |
1487                                man_trk_ctl_partial_frame_bit_get(dev_priv) |
1488                                man_trk_ctl_single_full_frame_bit_get(dev_priv));
1489
1490         /*
1491          * Display WA #0884: skl+
1492          * This documented WA for bxt can be safely applied
1493          * broadly so we can force HW tracking to exit PSR
1494          * instead of disabling and re-enabling.
1495          * Workaround tells us to write 0 to CUR_SURFLIVE_A,
1496          * but it makes more sense write to the current active
1497          * pipe.
1498          *
1499          * This workaround do not exist for platforms with display 10 or newer
1500          * but testing proved that it works for up display 13, for newer
1501          * than that testing will be needed.
1502          */
1503         intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
1504 }
1505
1506 void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
1507                                         const struct intel_crtc_state *crtc_state)
1508 {
1509         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1510         enum pipe pipe = plane->pipe;
1511
1512         if (!crtc_state->enable_psr2_sel_fetch)
1513                 return;
1514
1515         intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
1516 }
1517
1518 void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
1519                                         const struct intel_crtc_state *crtc_state,
1520                                         const struct intel_plane_state *plane_state,
1521                                         int color_plane)
1522 {
1523         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1524         enum pipe pipe = plane->pipe;
1525         const struct drm_rect *clip;
1526         u32 val;
1527         int x, y;
1528
1529         if (!crtc_state->enable_psr2_sel_fetch)
1530                 return;
1531
1532         if (plane->id == PLANE_CURSOR) {
1533                 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
1534                                   plane_state->ctl);
1535                 return;
1536         }
1537
1538         clip = &plane_state->psr2_sel_fetch_area;
1539
1540         val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
1541         val |= plane_state->uapi.dst.x1;
1542         intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
1543
1544         x = plane_state->view.color_plane[color_plane].x;
1545
1546         /*
1547          * From Bspec: UV surface Start Y Position = half of Y plane Y
1548          * start position.
1549          */
1550         if (!color_plane)
1551                 y = plane_state->view.color_plane[color_plane].y + clip->y1;
1552         else
1553                 y = plane_state->view.color_plane[color_plane].y + clip->y1 / 2;
1554
1555         val = y << 16 | x;
1556
1557         intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
1558                           val);
1559
1560         /* Sizes are 0 based */
1561         val = (drm_rect_height(clip) - 1) << 16;
1562         val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
1563         intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
1564
1565         intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
1566                           PLANE_SEL_FETCH_CTL_ENABLE);
1567 }
1568
1569 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
1570 {
1571         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1572         struct intel_encoder *encoder;
1573
1574         if (!crtc_state->enable_psr2_sel_fetch)
1575                 return;
1576
1577         for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
1578                                              crtc_state->uapi.encoder_mask) {
1579                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1580
1581                 lockdep_assert_held(&intel_dp->psr.lock);
1582                 if (intel_dp->psr.psr2_sel_fetch_cff_enabled)
1583                         return;
1584                 break;
1585         }
1586
1587         intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder),
1588                        crtc_state->psr2_man_track_ctl);
1589 }
1590
1591 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
1592                                   struct drm_rect *clip, bool full_update)
1593 {
1594         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1595         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1596         u32 val = man_trk_ctl_enable_bit_get(dev_priv);
1597
1598         /* SF partial frame enable has to be set even on full update */
1599         val |= man_trk_ctl_partial_frame_bit_get(dev_priv);
1600
1601         if (full_update) {
1602                 /*
1603                  * Not applying Wa_14014971508:adlp as we do not support the
1604                  * feature that requires this workaround.
1605                  */
1606                 val |= man_trk_ctl_single_full_frame_bit_get(dev_priv);
1607                 goto exit;
1608         }
1609
1610         if (clip->y1 == -1)
1611                 goto exit;
1612
1613         if (IS_ALDERLAKE_P(dev_priv)) {
1614                 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1);
1615                 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 - 1);
1616         } else {
1617                 drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
1618
1619                 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
1620                 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
1621         }
1622 exit:
1623         crtc_state->psr2_man_track_ctl = val;
1624 }
1625
1626 static void clip_area_update(struct drm_rect *overlap_damage_area,
1627                              struct drm_rect *damage_area)
1628 {
1629         if (overlap_damage_area->y1 == -1) {
1630                 overlap_damage_area->y1 = damage_area->y1;
1631                 overlap_damage_area->y2 = damage_area->y2;
1632                 return;
1633         }
1634
1635         if (damage_area->y1 < overlap_damage_area->y1)
1636                 overlap_damage_area->y1 = damage_area->y1;
1637
1638         if (damage_area->y2 > overlap_damage_area->y2)
1639                 overlap_damage_area->y2 = damage_area->y2;
1640 }
1641
1642 static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state,
1643                                                 struct drm_rect *pipe_clip)
1644 {
1645         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1646         const u16 y_alignment = crtc_state->su_y_granularity;
1647
1648         pipe_clip->y1 -= pipe_clip->y1 % y_alignment;
1649         if (pipe_clip->y2 % y_alignment)
1650                 pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment;
1651
1652         if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable)
1653                 drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n");
1654 }
1655
1656 /*
1657  * TODO: Not clear how to handle planes with negative position,
1658  * also planes are not updated if they have a negative X
1659  * position so for now doing a full update in this cases
1660  *
1661  * Plane scaling and rotation is not supported by selective fetch and both
1662  * properties can change without a modeset, so need to be check at every
1663  * atomic commmit.
1664  */
1665 static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state)
1666 {
1667         if (plane_state->uapi.dst.y1 < 0 ||
1668             plane_state->uapi.dst.x1 < 0 ||
1669             plane_state->scaler_id >= 0 ||
1670             plane_state->uapi.rotation != DRM_MODE_ROTATE_0)
1671                 return false;
1672
1673         return true;
1674 }
1675
1676 /*
1677  * Check for pipe properties that is not supported by selective fetch.
1678  *
1679  * TODO: pipe scaling causes a modeset but skl_update_scaler_crtc() is executed
1680  * after intel_psr_compute_config(), so for now keeping PSR2 selective fetch
1681  * enabled and going to the full update path.
1682  */
1683 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state)
1684 {
1685         if (crtc_state->scaler_state.scaler_id >= 0)
1686                 return false;
1687
1688         return true;
1689 }
1690
1691 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
1692                                 struct intel_crtc *crtc)
1693 {
1694         struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1695         struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 };
1696         struct intel_plane_state *new_plane_state, *old_plane_state;
1697         struct intel_plane *plane;
1698         bool full_update = false;
1699         int i, ret;
1700
1701         if (!crtc_state->enable_psr2_sel_fetch)
1702                 return 0;
1703
1704         if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) {
1705                 full_update = true;
1706                 goto skip_sel_fetch_set_loop;
1707         }
1708
1709         /*
1710          * Calculate minimal selective fetch area of each plane and calculate
1711          * the pipe damaged area.
1712          * In the next loop the plane selective fetch area will actually be set
1713          * using whole pipe damaged area.
1714          */
1715         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
1716                                              new_plane_state, i) {
1717                 struct drm_rect src, damaged_area = { .y1 = -1 };
1718                 struct drm_atomic_helper_damage_iter iter;
1719                 struct drm_rect clip;
1720
1721                 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
1722                         continue;
1723
1724                 if (!new_plane_state->uapi.visible &&
1725                     !old_plane_state->uapi.visible)
1726                         continue;
1727
1728                 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
1729                         full_update = true;
1730                         break;
1731                 }
1732
1733                 /*
1734                  * If visibility or plane moved, mark the whole plane area as
1735                  * damaged as it needs to be complete redraw in the new and old
1736                  * position.
1737                  */
1738                 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible ||
1739                     !drm_rect_equals(&new_plane_state->uapi.dst,
1740                                      &old_plane_state->uapi.dst)) {
1741                         if (old_plane_state->uapi.visible) {
1742                                 damaged_area.y1 = old_plane_state->uapi.dst.y1;
1743                                 damaged_area.y2 = old_plane_state->uapi.dst.y2;
1744                                 clip_area_update(&pipe_clip, &damaged_area);
1745                         }
1746
1747                         if (new_plane_state->uapi.visible) {
1748                                 damaged_area.y1 = new_plane_state->uapi.dst.y1;
1749                                 damaged_area.y2 = new_plane_state->uapi.dst.y2;
1750                                 clip_area_update(&pipe_clip, &damaged_area);
1751                         }
1752                         continue;
1753                 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) {
1754                         /* If alpha changed mark the whole plane area as damaged */
1755                         damaged_area.y1 = new_plane_state->uapi.dst.y1;
1756                         damaged_area.y2 = new_plane_state->uapi.dst.y2;
1757                         clip_area_update(&pipe_clip, &damaged_area);
1758                         continue;
1759                 }
1760
1761                 drm_rect_fp_to_int(&src, &new_plane_state->uapi.src);
1762
1763                 drm_atomic_helper_damage_iter_init(&iter,
1764                                                    &old_plane_state->uapi,
1765                                                    &new_plane_state->uapi);
1766                 drm_atomic_for_each_plane_damage(&iter, &clip) {
1767                         if (drm_rect_intersect(&clip, &src))
1768                                 clip_area_update(&damaged_area, &clip);
1769                 }
1770
1771                 if (damaged_area.y1 == -1)
1772                         continue;
1773
1774                 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1;
1775                 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1;
1776                 clip_area_update(&pipe_clip, &damaged_area);
1777         }
1778
1779         if (full_update)
1780                 goto skip_sel_fetch_set_loop;
1781
1782         ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
1783         if (ret)
1784                 return ret;
1785
1786         intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip);
1787
1788         /*
1789          * Now that we have the pipe damaged area check if it intersect with
1790          * every plane, if it does set the plane selective fetch area.
1791          */
1792         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
1793                                              new_plane_state, i) {
1794                 struct drm_rect *sel_fetch_area, inter;
1795                 struct intel_plane *linked = new_plane_state->planar_linked_plane;
1796
1797                 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc ||
1798                     !new_plane_state->uapi.visible)
1799                         continue;
1800
1801                 inter = pipe_clip;
1802                 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst))
1803                         continue;
1804
1805                 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
1806                         full_update = true;
1807                         break;
1808                 }
1809
1810                 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
1811                 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1;
1812                 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1;
1813                 crtc_state->update_planes |= BIT(plane->id);
1814
1815                 /*
1816                  * Sel_fetch_area is calculated for UV plane. Use
1817                  * same area for Y plane as well.
1818                  */
1819                 if (linked) {
1820                         struct intel_plane_state *linked_new_plane_state;
1821                         struct drm_rect *linked_sel_fetch_area;
1822
1823                         linked_new_plane_state = intel_atomic_get_plane_state(state, linked);
1824                         if (IS_ERR(linked_new_plane_state))
1825                                 return PTR_ERR(linked_new_plane_state);
1826
1827                         linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area;
1828                         linked_sel_fetch_area->y1 = sel_fetch_area->y1;
1829                         linked_sel_fetch_area->y2 = sel_fetch_area->y2;
1830                         crtc_state->update_planes |= BIT(linked->id);
1831                 }
1832         }
1833
1834 skip_sel_fetch_set_loop:
1835         psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update);
1836         return 0;
1837 }
1838
1839 void intel_psr_pre_plane_update(struct intel_atomic_state *state,
1840                                 struct intel_crtc *crtc)
1841 {
1842         struct drm_i915_private *i915 = to_i915(state->base.dev);
1843         const struct intel_crtc_state *crtc_state =
1844                 intel_atomic_get_new_crtc_state(state, crtc);
1845         struct intel_encoder *encoder;
1846
1847         if (!HAS_PSR(i915))
1848                 return;
1849
1850         for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
1851                                              crtc_state->uapi.encoder_mask) {
1852                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1853                 struct intel_psr *psr = &intel_dp->psr;
1854                 bool needs_to_disable = false;
1855
1856                 mutex_lock(&psr->lock);
1857
1858                 /*
1859                  * Reasons to disable:
1860                  * - PSR disabled in new state
1861                  * - All planes will go inactive
1862                  * - Changing between PSR versions
1863                  */
1864                 needs_to_disable |= intel_crtc_needs_modeset(crtc_state);
1865                 needs_to_disable |= !crtc_state->has_psr;
1866                 needs_to_disable |= !crtc_state->active_planes;
1867                 needs_to_disable |= crtc_state->has_psr2 != psr->psr2_enabled;
1868
1869                 if (psr->enabled && needs_to_disable)
1870                         intel_psr_disable_locked(intel_dp);
1871
1872                 mutex_unlock(&psr->lock);
1873         }
1874 }
1875
1876 static void _intel_psr_post_plane_update(const struct intel_atomic_state *state,
1877                                          const struct intel_crtc_state *crtc_state)
1878 {
1879         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1880         struct intel_encoder *encoder;
1881
1882         if (!crtc_state->has_psr)
1883                 return;
1884
1885         for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
1886                                              crtc_state->uapi.encoder_mask) {
1887                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1888                 struct intel_psr *psr = &intel_dp->psr;
1889
1890                 mutex_lock(&psr->lock);
1891
1892                 if (psr->sink_not_reliable)
1893                         goto exit;
1894
1895                 drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes);
1896
1897                 /* Only enable if there is active planes */
1898                 if (!psr->enabled && crtc_state->active_planes)
1899                         intel_psr_enable_locked(intel_dp, crtc_state);
1900
1901                 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */
1902                 if (crtc_state->crc_enabled && psr->enabled)
1903                         psr_force_hw_tracking_exit(intel_dp);
1904
1905 exit:
1906                 mutex_unlock(&psr->lock);
1907         }
1908 }
1909
1910 void intel_psr_post_plane_update(const struct intel_atomic_state *state)
1911 {
1912         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1913         struct intel_crtc_state *crtc_state;
1914         struct intel_crtc *crtc;
1915         int i;
1916
1917         if (!HAS_PSR(dev_priv))
1918                 return;
1919
1920         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)
1921                 _intel_psr_post_plane_update(state, crtc_state);
1922 }
1923
1924 static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
1925 {
1926         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1927
1928         /*
1929          * Any state lower than EDP_PSR2_STATUS_STATE_DEEP_SLEEP is enough.
1930          * As all higher states has bit 4 of PSR2 state set we can just wait for
1931          * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared.
1932          */
1933         return intel_de_wait_for_clear(dev_priv,
1934                                        EDP_PSR2_STATUS(intel_dp->psr.transcoder),
1935                                        EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 50);
1936 }
1937
1938 static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
1939 {
1940         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1941
1942         /*
1943          * From bspec: Panel Self Refresh (BDW+)
1944          * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of
1945          * exit training time + 1.5 ms of aux channel handshake. 50 ms is
1946          * defensive enough to cover everything.
1947          */
1948         return intel_de_wait_for_clear(dev_priv,
1949                                        EDP_PSR_STATUS(intel_dp->psr.transcoder),
1950                                        EDP_PSR_STATUS_STATE_MASK, 50);
1951 }
1952
1953 /**
1954  * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update
1955  * @new_crtc_state: new CRTC state
1956  *
1957  * This function is expected to be called from pipe_update_start() where it is
1958  * not expected to race with PSR enable or disable.
1959  */
1960 void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state)
1961 {
1962         struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev);
1963         struct intel_encoder *encoder;
1964
1965         if (!new_crtc_state->has_psr)
1966                 return;
1967
1968         for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
1969                                              new_crtc_state->uapi.encoder_mask) {
1970                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1971                 int ret;
1972
1973                 lockdep_assert_held(&intel_dp->psr.lock);
1974
1975                 if (!intel_dp->psr.enabled)
1976                         continue;
1977
1978                 if (intel_dp->psr.psr2_enabled)
1979                         ret = _psr2_ready_for_pipe_update_locked(intel_dp);
1980                 else
1981                         ret = _psr1_ready_for_pipe_update_locked(intel_dp);
1982
1983                 if (ret)
1984                         drm_err(&dev_priv->drm, "PSR wait timed out, atomic update may fail\n");
1985         }
1986 }
1987
1988 static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
1989 {
1990         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1991         i915_reg_t reg;
1992         u32 mask;
1993         int err;
1994
1995         if (!intel_dp->psr.enabled)
1996                 return false;
1997
1998         if (intel_dp->psr.psr2_enabled) {
1999                 reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
2000                 mask = EDP_PSR2_STATUS_STATE_MASK;
2001         } else {
2002                 reg = EDP_PSR_STATUS(intel_dp->psr.transcoder);
2003                 mask = EDP_PSR_STATUS_STATE_MASK;
2004         }
2005
2006         mutex_unlock(&intel_dp->psr.lock);
2007
2008         err = intel_de_wait_for_clear(dev_priv, reg, mask, 50);
2009         if (err)
2010                 drm_err(&dev_priv->drm,
2011                         "Timed out waiting for PSR Idle for re-enable\n");
2012
2013         /* After the unlocked wait, verify that PSR is still wanted! */
2014         mutex_lock(&intel_dp->psr.lock);
2015         return err == 0 && intel_dp->psr.enabled;
2016 }
2017
2018 static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
2019 {
2020         struct drm_connector_list_iter conn_iter;
2021         struct drm_device *dev = &dev_priv->drm;
2022         struct drm_modeset_acquire_ctx ctx;
2023         struct drm_atomic_state *state;
2024         struct drm_connector *conn;
2025         int err = 0;
2026
2027         state = drm_atomic_state_alloc(dev);
2028         if (!state)
2029                 return -ENOMEM;
2030
2031         drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
2032         state->acquire_ctx = &ctx;
2033
2034 retry:
2035
2036         drm_connector_list_iter_begin(dev, &conn_iter);
2037         drm_for_each_connector_iter(conn, &conn_iter) {
2038                 struct drm_connector_state *conn_state;
2039                 struct drm_crtc_state *crtc_state;
2040
2041                 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP)
2042                         continue;
2043
2044                 conn_state = drm_atomic_get_connector_state(state, conn);
2045                 if (IS_ERR(conn_state)) {
2046                         err = PTR_ERR(conn_state);
2047                         break;
2048                 }
2049
2050                 if (!conn_state->crtc)
2051                         continue;
2052
2053                 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc);
2054                 if (IS_ERR(crtc_state)) {
2055                         err = PTR_ERR(crtc_state);
2056                         break;
2057                 }
2058
2059                 /* Mark mode as changed to trigger a pipe->update() */
2060                 crtc_state->mode_changed = true;
2061         }
2062         drm_connector_list_iter_end(&conn_iter);
2063
2064         if (err == 0)
2065                 err = drm_atomic_commit(state);
2066
2067         if (err == -EDEADLK) {
2068                 drm_atomic_state_clear(state);
2069                 err = drm_modeset_backoff(&ctx);
2070                 if (!err)
2071                         goto retry;
2072         }
2073
2074         drm_modeset_drop_locks(&ctx);
2075         drm_modeset_acquire_fini(&ctx);
2076         drm_atomic_state_put(state);
2077
2078         return err;
2079 }
2080
2081 int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val)
2082 {
2083         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2084         const u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
2085         u32 old_mode;
2086         int ret;
2087
2088         if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) ||
2089             mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
2090                 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val);
2091                 return -EINVAL;
2092         }
2093
2094         ret = mutex_lock_interruptible(&intel_dp->psr.lock);
2095         if (ret)
2096                 return ret;
2097
2098         old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK;
2099         intel_dp->psr.debug = val;
2100
2101         /*
2102          * Do it right away if it's already enabled, otherwise it will be done
2103          * when enabling the source.
2104          */
2105         if (intel_dp->psr.enabled)
2106                 psr_irq_control(intel_dp);
2107
2108         mutex_unlock(&intel_dp->psr.lock);
2109
2110         if (old_mode != mode)
2111                 ret = intel_psr_fastset_force(dev_priv);
2112
2113         return ret;
2114 }
2115
2116 static void intel_psr_handle_irq(struct intel_dp *intel_dp)
2117 {
2118         struct intel_psr *psr = &intel_dp->psr;
2119
2120         intel_psr_disable_locked(intel_dp);
2121         psr->sink_not_reliable = true;
2122         /* let's make sure that sink is awaken */
2123         drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
2124 }
2125
2126 static void intel_psr_work(struct work_struct *work)
2127 {
2128         struct intel_dp *intel_dp =
2129                 container_of(work, typeof(*intel_dp), psr.work);
2130
2131         mutex_lock(&intel_dp->psr.lock);
2132
2133         if (!intel_dp->psr.enabled)
2134                 goto unlock;
2135
2136         if (READ_ONCE(intel_dp->psr.irq_aux_error))
2137                 intel_psr_handle_irq(intel_dp);
2138
2139         /*
2140          * We have to make sure PSR is ready for re-enable
2141          * otherwise it keeps disabled until next full enable/disable cycle.
2142          * PSR might take some time to get fully disabled
2143          * and be ready for re-enable.
2144          */
2145         if (!__psr_wait_for_idle_locked(intel_dp))
2146                 goto unlock;
2147
2148         /*
2149          * The delayed work can race with an invalidate hence we need to
2150          * recheck. Since psr_flush first clears this and then reschedules we
2151          * won't ever miss a flush when bailing out here.
2152          */
2153         if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active)
2154                 goto unlock;
2155
2156         intel_psr_activate(intel_dp);
2157 unlock:
2158         mutex_unlock(&intel_dp->psr.lock);
2159 }
2160
2161 static void _psr_invalidate_handle(struct intel_dp *intel_dp)
2162 {
2163         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2164
2165         if (intel_dp->psr.psr2_sel_fetch_enabled) {
2166                 u32 val;
2167
2168                 if (intel_dp->psr.psr2_sel_fetch_cff_enabled)
2169                         return;
2170
2171                 val = man_trk_ctl_enable_bit_get(dev_priv) |
2172                       man_trk_ctl_partial_frame_bit_get(dev_priv) |
2173                       man_trk_ctl_continuos_full_frame(dev_priv);
2174                 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), val);
2175                 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
2176                 intel_dp->psr.psr2_sel_fetch_cff_enabled = true;
2177         } else {
2178                 intel_psr_exit(intel_dp);
2179         }
2180 }
2181
2182 /**
2183  * intel_psr_invalidate - Invalidade PSR
2184  * @dev_priv: i915 device
2185  * @frontbuffer_bits: frontbuffer plane tracking bits
2186  * @origin: which operation caused the invalidate
2187  *
2188  * Since the hardware frontbuffer tracking has gaps we need to integrate
2189  * with the software frontbuffer tracking. This function gets called every
2190  * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
2191  * disabled if the frontbuffer mask contains a buffer relevant to PSR.
2192  *
2193  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
2194  */
2195 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
2196                           unsigned frontbuffer_bits, enum fb_op_origin origin)
2197 {
2198         struct intel_encoder *encoder;
2199
2200         if (origin == ORIGIN_FLIP)
2201                 return;
2202
2203         for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2204                 unsigned int pipe_frontbuffer_bits = frontbuffer_bits;
2205                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2206
2207                 mutex_lock(&intel_dp->psr.lock);
2208                 if (!intel_dp->psr.enabled) {
2209                         mutex_unlock(&intel_dp->psr.lock);
2210                         continue;
2211                 }
2212
2213                 pipe_frontbuffer_bits &=
2214                         INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
2215                 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits;
2216
2217                 if (pipe_frontbuffer_bits)
2218                         _psr_invalidate_handle(intel_dp);
2219
2220                 mutex_unlock(&intel_dp->psr.lock);
2221         }
2222 }
2223 /*
2224  * When we will be completely rely on PSR2 S/W tracking in future,
2225  * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP
2226  * event also therefore tgl_dc3co_flush_locked() require to be changed
2227  * accordingly in future.
2228  */
2229 static void
2230 tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
2231                        enum fb_op_origin origin)
2232 {
2233         if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.psr2_enabled ||
2234             !intel_dp->psr.active)
2235                 return;
2236
2237         /*
2238          * At every frontbuffer flush flip event modified delay of delayed work,
2239          * when delayed work schedules that means display has been idle.
2240          */
2241         if (!(frontbuffer_bits &
2242             INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
2243                 return;
2244
2245         tgl_psr2_enable_dc3co(intel_dp);
2246         mod_delayed_work(system_wq, &intel_dp->psr.dc3co_work,
2247                          intel_dp->psr.dc3co_exit_delay);
2248 }
2249
2250 static void _psr_flush_handle(struct intel_dp *intel_dp)
2251 {
2252         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2253
2254         if (intel_dp->psr.psr2_sel_fetch_enabled) {
2255                 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
2256                         /* can we turn CFF off? */
2257                         if (intel_dp->psr.busy_frontbuffer_bits == 0) {
2258                                 u32 val = man_trk_ctl_enable_bit_get(dev_priv) |
2259                                           man_trk_ctl_partial_frame_bit_get(dev_priv) |
2260                                           man_trk_ctl_single_full_frame_bit_get(dev_priv);
2261
2262                                 /*
2263                                  * turn continuous full frame off and do a single
2264                                  * full frame
2265                                  */
2266                                 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
2267                                                val);
2268                                 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
2269                                 intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
2270                         }
2271                 } else {
2272                         /*
2273                          * continuous full frame is disabled, only a single full
2274                          * frame is required
2275                          */
2276                         psr_force_hw_tracking_exit(intel_dp);
2277                 }
2278         } else {
2279                 psr_force_hw_tracking_exit(intel_dp);
2280
2281                 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)
2282                         schedule_work(&intel_dp->psr.work);
2283         }
2284 }
2285
2286 /**
2287  * intel_psr_flush - Flush PSR
2288  * @dev_priv: i915 device
2289  * @frontbuffer_bits: frontbuffer plane tracking bits
2290  * @origin: which operation caused the flush
2291  *
2292  * Since the hardware frontbuffer tracking has gaps we need to integrate
2293  * with the software frontbuffer tracking. This function gets called every
2294  * time frontbuffer rendering has completed and flushed out to memory. PSR
2295  * can be enabled again if no other frontbuffer relevant to PSR is dirty.
2296  *
2297  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
2298  */
2299 void intel_psr_flush(struct drm_i915_private *dev_priv,
2300                      unsigned frontbuffer_bits, enum fb_op_origin origin)
2301 {
2302         struct intel_encoder *encoder;
2303
2304         for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2305                 unsigned int pipe_frontbuffer_bits = frontbuffer_bits;
2306                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2307
2308                 mutex_lock(&intel_dp->psr.lock);
2309                 if (!intel_dp->psr.enabled) {
2310                         mutex_unlock(&intel_dp->psr.lock);
2311                         continue;
2312                 }
2313
2314                 pipe_frontbuffer_bits &=
2315                         INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
2316                 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits;
2317
2318                 /*
2319                  * If the PSR is paused by an explicit intel_psr_paused() call,
2320                  * we have to ensure that the PSR is not activated until
2321                  * intel_psr_resume() is called.
2322                  */
2323                 if (intel_dp->psr.paused)
2324                         goto unlock;
2325
2326                 if (origin == ORIGIN_FLIP ||
2327                     (origin == ORIGIN_CURSOR_UPDATE &&
2328                      !intel_dp->psr.psr2_sel_fetch_enabled)) {
2329                         tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin);
2330                         goto unlock;
2331                 }
2332
2333                 if (pipe_frontbuffer_bits == 0)
2334                         goto unlock;
2335
2336                 /* By definition flush = invalidate + flush */
2337                 _psr_flush_handle(intel_dp);
2338 unlock:
2339                 mutex_unlock(&intel_dp->psr.lock);
2340         }
2341 }
2342
2343 /**
2344  * intel_psr_init - Init basic PSR work and mutex.
2345  * @intel_dp: Intel DP
2346  *
2347  * This function is called after the initializing connector.
2348  * (the initializing of connector treats the handling of connector capabilities)
2349  * And it initializes basic PSR stuff for each DP Encoder.
2350  */
2351 void intel_psr_init(struct intel_dp *intel_dp)
2352 {
2353         struct intel_connector *connector = intel_dp->attached_connector;
2354         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2355         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2356
2357         if (!HAS_PSR(dev_priv))
2358                 return;
2359
2360         /*
2361          * HSW spec explicitly says PSR is tied to port A.
2362          * BDW+ platforms have a instance of PSR registers per transcoder but
2363          * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder
2364          * than eDP one.
2365          * For now it only supports one instance of PSR for BDW, GEN9 and GEN11.
2366          * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11.
2367          * But GEN12 supports a instance of PSR registers per transcoder.
2368          */
2369         if (DISPLAY_VER(dev_priv) < 12 && dig_port->base.port != PORT_A) {
2370                 drm_dbg_kms(&dev_priv->drm,
2371                             "PSR condition failed: Port not supported\n");
2372                 return;
2373         }
2374
2375         intel_dp->psr.source_support = true;
2376
2377         /* Set link_standby x link_off defaults */
2378         if (DISPLAY_VER(dev_priv) < 12)
2379                 /* For new platforms up to TGL let's respect VBT back again */
2380                 intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link;
2381
2382         INIT_WORK(&intel_dp->psr.work, intel_psr_work);
2383         INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);
2384         mutex_init(&intel_dp->psr.lock);
2385 }
2386
2387 static int psr_get_status_and_error_status(struct intel_dp *intel_dp,
2388                                            u8 *status, u8 *error_status)
2389 {
2390         struct drm_dp_aux *aux = &intel_dp->aux;
2391         int ret;
2392
2393         ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status);
2394         if (ret != 1)
2395                 return ret;
2396
2397         ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status);
2398         if (ret != 1)
2399                 return ret;
2400
2401         *status = *status & DP_PSR_SINK_STATE_MASK;
2402
2403         return 0;
2404 }
2405
2406 static void psr_alpm_check(struct intel_dp *intel_dp)
2407 {
2408         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2409         struct drm_dp_aux *aux = &intel_dp->aux;
2410         struct intel_psr *psr = &intel_dp->psr;
2411         u8 val;
2412         int r;
2413
2414         if (!psr->psr2_enabled)
2415                 return;
2416
2417         r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val);
2418         if (r != 1) {
2419                 drm_err(&dev_priv->drm, "Error reading ALPM status\n");
2420                 return;
2421         }
2422
2423         if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) {
2424                 intel_psr_disable_locked(intel_dp);
2425                 psr->sink_not_reliable = true;
2426                 drm_dbg_kms(&dev_priv->drm,
2427                             "ALPM lock timeout error, disabling PSR\n");
2428
2429                 /* Clearing error */
2430                 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val);
2431         }
2432 }
2433
2434 static void psr_capability_changed_check(struct intel_dp *intel_dp)
2435 {
2436         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2437         struct intel_psr *psr = &intel_dp->psr;
2438         u8 val;
2439         int r;
2440
2441         r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val);
2442         if (r != 1) {
2443                 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n");
2444                 return;
2445         }
2446
2447         if (val & DP_PSR_CAPS_CHANGE) {
2448                 intel_psr_disable_locked(intel_dp);
2449                 psr->sink_not_reliable = true;
2450                 drm_dbg_kms(&dev_priv->drm,
2451                             "Sink PSR capability changed, disabling PSR\n");
2452
2453                 /* Clearing it */
2454                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val);
2455         }
2456 }
2457
2458 void intel_psr_short_pulse(struct intel_dp *intel_dp)
2459 {
2460         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2461         struct intel_psr *psr = &intel_dp->psr;
2462         u8 status, error_status;
2463         const u8 errors = DP_PSR_RFB_STORAGE_ERROR |
2464                           DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
2465                           DP_PSR_LINK_CRC_ERROR;
2466
2467         if (!CAN_PSR(intel_dp))
2468                 return;
2469
2470         mutex_lock(&psr->lock);
2471
2472         if (!psr->enabled)
2473                 goto exit;
2474
2475         if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) {
2476                 drm_err(&dev_priv->drm,
2477                         "Error reading PSR status or error status\n");
2478                 goto exit;
2479         }
2480
2481         if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) {
2482                 intel_psr_disable_locked(intel_dp);
2483                 psr->sink_not_reliable = true;
2484         }
2485
2486         if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status)
2487                 drm_dbg_kms(&dev_priv->drm,
2488                             "PSR sink internal error, disabling PSR\n");
2489         if (error_status & DP_PSR_RFB_STORAGE_ERROR)
2490                 drm_dbg_kms(&dev_priv->drm,
2491                             "PSR RFB storage error, disabling PSR\n");
2492         if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
2493                 drm_dbg_kms(&dev_priv->drm,
2494                             "PSR VSC SDP uncorrectable error, disabling PSR\n");
2495         if (error_status & DP_PSR_LINK_CRC_ERROR)
2496                 drm_dbg_kms(&dev_priv->drm,
2497                             "PSR Link CRC error, disabling PSR\n");
2498
2499         if (error_status & ~errors)
2500                 drm_err(&dev_priv->drm,
2501                         "PSR_ERROR_STATUS unhandled errors %x\n",
2502                         error_status & ~errors);
2503         /* clear status register */
2504         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);
2505
2506         psr_alpm_check(intel_dp);
2507         psr_capability_changed_check(intel_dp);
2508
2509 exit:
2510         mutex_unlock(&psr->lock);
2511 }
2512
2513 bool intel_psr_enabled(struct intel_dp *intel_dp)
2514 {
2515         bool ret;
2516
2517         if (!CAN_PSR(intel_dp))
2518                 return false;
2519
2520         mutex_lock(&intel_dp->psr.lock);
2521         ret = intel_dp->psr.enabled;
2522         mutex_unlock(&intel_dp->psr.lock);
2523
2524         return ret;
2525 }
2526
2527 /**
2528  * intel_psr_lock - grab PSR lock
2529  * @crtc_state: the crtc state
2530  *
2531  * This is initially meant to be used by around CRTC update, when
2532  * vblank sensitive registers are updated and we need grab the lock
2533  * before it to avoid vblank evasion.
2534  */
2535 void intel_psr_lock(const struct intel_crtc_state *crtc_state)
2536 {
2537         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2538         struct intel_encoder *encoder;
2539
2540         if (!crtc_state->has_psr)
2541                 return;
2542
2543         for_each_intel_encoder_mask_with_psr(&i915->drm, encoder,
2544                                              crtc_state->uapi.encoder_mask) {
2545                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2546
2547                 mutex_lock(&intel_dp->psr.lock);
2548                 break;
2549         }
2550 }
2551
2552 /**
2553  * intel_psr_unlock - release PSR lock
2554  * @crtc_state: the crtc state
2555  *
2556  * Release the PSR lock that was held during pipe update.
2557  */
2558 void intel_psr_unlock(const struct intel_crtc_state *crtc_state)
2559 {
2560         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2561         struct intel_encoder *encoder;
2562
2563         if (!crtc_state->has_psr)
2564                 return;
2565
2566         for_each_intel_encoder_mask_with_psr(&i915->drm, encoder,
2567                                              crtc_state->uapi.encoder_mask) {
2568                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2569
2570                 mutex_unlock(&intel_dp->psr.lock);
2571                 break;
2572         }
2573 }