1 // SPDX-License-Identifier: GPL-2.0
3 * Mellanox BlueField I2C bus driver
5 * Copyright (C) 2020 Mellanox Technologies, Ltd.
8 #include <linux/acpi.h>
9 #include <linux/delay.h>
10 #include <linux/err.h>
11 #include <linux/interrupt.h>
12 #include <linux/i2c.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/mutex.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/string.h>
21 /* Defines what functionality is present. */
22 #define MLXBF_I2C_FUNC_SMBUS_BLOCK \
23 (I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL)
25 #define MLXBF_I2C_FUNC_SMBUS_DEFAULT \
26 (I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA | \
27 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_I2C_BLOCK | \
28 I2C_FUNC_SMBUS_PROC_CALL)
30 #define MLXBF_I2C_FUNC_ALL \
31 (MLXBF_I2C_FUNC_SMBUS_DEFAULT | MLXBF_I2C_FUNC_SMBUS_BLOCK | \
32 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SLAVE)
34 #define MLXBF_I2C_SMBUS_MAX 3
36 /* Shared resources info in BlueField platforms. */
38 #define MLXBF_I2C_COALESCE_TYU_ADDR 0x02801300
39 #define MLXBF_I2C_COALESCE_TYU_SIZE 0x010
41 #define MLXBF_I2C_GPIO_TYU_ADDR 0x02802000
42 #define MLXBF_I2C_GPIO_TYU_SIZE 0x100
44 #define MLXBF_I2C_COREPLL_TYU_ADDR 0x02800358
45 #define MLXBF_I2C_COREPLL_TYU_SIZE 0x008
47 #define MLXBF_I2C_COREPLL_YU_ADDR 0x02800c30
48 #define MLXBF_I2C_COREPLL_YU_SIZE 0x00c
50 #define MLXBF_I2C_SHARED_RES_MAX 3
53 * Note that the following SMBus, CAUSE, GPIO and PLL register addresses
54 * refer to their respective offsets relative to the corresponding
55 * memory-mapped region whose addresses are specified in either the DT or
56 * the ACPI tables or above.
60 * SMBus Master core clock frequency. Timing configurations are
61 * strongly dependent on the core clock frequency of the SMBus
62 * Master. Default value is set to 400MHz.
64 #define MLXBF_I2C_TYU_PLL_OUT_FREQ (400 * 1000 * 1000)
65 /* Reference clock for Bluefield - 156 MHz. */
66 #define MLXBF_I2C_PLL_IN_FREQ (156 * 1000 * 1000)
68 /* Constant used to determine the PLL frequency. */
69 #define MLNXBF_I2C_COREPLL_CONST 16384
72 #define MLXBF_I2C_CORE_PLL_REG0 0x0
73 #define MLXBF_I2C_CORE_PLL_REG1 0x4
74 #define MLXBF_I2C_CORE_PLL_REG2 0x8
76 /* OR cause register. */
77 #define MLXBF_I2C_CAUSE_OR_EVTEN0 0x14
78 #define MLXBF_I2C_CAUSE_OR_CLEAR 0x18
80 /* Arbiter Cause Register. */
81 #define MLXBF_I2C_CAUSE_ARBITER 0x1c
84 * Cause Status flags. Note that those bits might be considered
85 * as interrupt enabled bits.
88 /* Transaction ended with STOP. */
89 #define MLXBF_I2C_CAUSE_TRANSACTION_ENDED BIT(0)
90 /* Master arbitration lost. */
91 #define MLXBF_I2C_CAUSE_M_ARBITRATION_LOST BIT(1)
92 /* Unexpected start detected. */
93 #define MLXBF_I2C_CAUSE_UNEXPECTED_START BIT(2)
94 /* Unexpected stop detected. */
95 #define MLXBF_I2C_CAUSE_UNEXPECTED_STOP BIT(3)
96 /* Wait for transfer continuation. */
97 #define MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA BIT(4)
98 /* Failed to generate STOP. */
99 #define MLXBF_I2C_CAUSE_PUT_STOP_FAILED BIT(5)
100 /* Failed to generate START. */
101 #define MLXBF_I2C_CAUSE_PUT_START_FAILED BIT(6)
102 /* Clock toggle completed. */
103 #define MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE BIT(7)
104 /* Transfer timeout occurred. */
105 #define MLXBF_I2C_CAUSE_M_FW_TIMEOUT BIT(8)
106 /* Master busy bit reset. */
107 #define MLXBF_I2C_CAUSE_M_GW_BUSY_FALL BIT(9)
109 #define MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK GENMASK(9, 0)
111 #define MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR \
112 (MLXBF_I2C_CAUSE_M_ARBITRATION_LOST | \
113 MLXBF_I2C_CAUSE_UNEXPECTED_START | \
114 MLXBF_I2C_CAUSE_UNEXPECTED_STOP | \
115 MLXBF_I2C_CAUSE_PUT_STOP_FAILED | \
116 MLXBF_I2C_CAUSE_PUT_START_FAILED | \
117 MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE | \
118 MLXBF_I2C_CAUSE_M_FW_TIMEOUT)
121 * Slave cause status flags. Note that those bits might be considered
122 * as interrupt enabled bits.
125 /* Write transaction received successfully. */
126 #define MLXBF_I2C_CAUSE_WRITE_SUCCESS BIT(0)
127 /* Read transaction received, waiting for response. */
128 #define MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE BIT(13)
129 /* Slave busy bit reset. */
130 #define MLXBF_I2C_CAUSE_S_GW_BUSY_FALL BIT(18)
132 #define MLXBF_I2C_CAUSE_SLAVE_ARBITER_BITS_MASK GENMASK(20, 0)
134 /* Cause coalesce registers. */
135 #define MLXBF_I2C_CAUSE_COALESCE_0 0x00
136 #define MLXBF_I2C_CAUSE_COALESCE_1 0x04
137 #define MLXBF_I2C_CAUSE_COALESCE_2 0x08
139 #define MLXBF_I2C_CAUSE_TYU_SLAVE_BIT MLXBF_I2C_SMBUS_MAX
140 #define MLXBF_I2C_CAUSE_YU_SLAVE_BIT 1
142 /* Functional enable register. */
143 #define MLXBF_I2C_GPIO_0_FUNC_EN_0 0x28
144 /* Force OE enable register. */
145 #define MLXBF_I2C_GPIO_0_FORCE_OE_EN 0x30
147 * Note that Smbus GWs are on GPIOs 30:25. Two pins are used to control
150 * SMBUS GW0 -> bits[26:25]
151 * SMBUS GW1 -> bits[28:27]
152 * SMBUS GW2 -> bits[30:29]
154 #define MLXBF_I2C_GPIO_SMBUS_GW_PINS(num) (25 + ((num) << 1))
156 /* Note that gw_id can be 0,1 or 2. */
157 #define MLXBF_I2C_GPIO_SMBUS_GW_MASK(num) \
158 (0xffffffff & (~(0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num))))
160 #define MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(num, val) \
161 ((val) & MLXBF_I2C_GPIO_SMBUS_GW_MASK(num))
163 #define MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(num, val) \
164 ((val) | (0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num)))
166 /* SMBus timing parameters. */
167 #define MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH 0x00
168 #define MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE 0x04
169 #define MLXBF_I2C_SMBUS_TIMER_THOLD 0x08
170 #define MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP 0x0c
171 #define MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA 0x10
172 #define MLXBF_I2C_SMBUS_THIGH_MAX_TBUF 0x14
173 #define MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT 0x18
176 * Defines SMBus operating frequency and core clock frequency.
177 * According to ADB files, default values are compliant to 100KHz SMBus
178 * @ 400MHz core clock. The driver should be able to calculate core
179 * frequency based on PLL parameters.
181 #define MLXBF_I2C_COREPLL_FREQ MLXBF_I2C_TYU_PLL_OUT_FREQ
183 /* Core PLL TYU configuration. */
184 #define MLXBF_I2C_COREPLL_CORE_F_TYU_MASK GENMASK(12, 0)
185 #define MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK GENMASK(3, 0)
186 #define MLXBF_I2C_COREPLL_CORE_R_TYU_MASK GENMASK(5, 0)
188 #define MLXBF_I2C_COREPLL_CORE_F_TYU_SHIFT 3
189 #define MLXBF_I2C_COREPLL_CORE_OD_TYU_SHIFT 16
190 #define MLXBF_I2C_COREPLL_CORE_R_TYU_SHIFT 20
192 /* Core PLL YU configuration. */
193 #define MLXBF_I2C_COREPLL_CORE_F_YU_MASK GENMASK(25, 0)
194 #define MLXBF_I2C_COREPLL_CORE_OD_YU_MASK GENMASK(3, 0)
195 #define MLXBF_I2C_COREPLL_CORE_R_YU_MASK GENMASK(5, 0)
197 #define MLXBF_I2C_COREPLL_CORE_F_YU_SHIFT 0
198 #define MLXBF_I2C_COREPLL_CORE_OD_YU_SHIFT 1
199 #define MLXBF_I2C_COREPLL_CORE_R_YU_SHIFT 26
201 /* Core PLL frequency. */
202 static u64 mlxbf_i2c_corepll_frequency;
204 /* SMBus Master GW. */
205 #define MLXBF_I2C_SMBUS_MASTER_GW 0x200
206 /* Number of bytes received and sent. */
207 #define MLXBF_I2C_SMBUS_RS_BYTES 0x300
208 /* Packet error check (PEC) value. */
209 #define MLXBF_I2C_SMBUS_MASTER_PEC 0x304
210 /* Status bits (ACK/NACK/FW Timeout). */
211 #define MLXBF_I2C_SMBUS_MASTER_STATUS 0x308
212 /* SMbus Master Finite State Machine. */
213 #define MLXBF_I2C_SMBUS_MASTER_FSM 0x310
216 * When enabled, the master will issue a stop condition in case of
217 * timeout while waiting for FW response.
219 #define MLXBF_I2C_SMBUS_EN_FW_TIMEOUT 0x31c
221 /* SMBus master GW control bits offset in MLXBF_I2C_SMBUS_MASTER_GW[31:3]. */
222 #define MLXBF_I2C_MASTER_LOCK_BIT BIT(31) /* Lock bit. */
223 #define MLXBF_I2C_MASTER_BUSY_BIT BIT(30) /* Busy bit. */
224 #define MLXBF_I2C_MASTER_START_BIT BIT(29) /* Control start. */
225 #define MLXBF_I2C_MASTER_CTL_WRITE_BIT BIT(28) /* Control write phase. */
226 #define MLXBF_I2C_MASTER_CTL_READ_BIT BIT(19) /* Control read phase. */
227 #define MLXBF_I2C_MASTER_STOP_BIT BIT(3) /* Control stop. */
229 #define MLXBF_I2C_MASTER_ENABLE \
230 (MLXBF_I2C_MASTER_LOCK_BIT | MLXBF_I2C_MASTER_BUSY_BIT | \
231 MLXBF_I2C_MASTER_START_BIT | MLXBF_I2C_MASTER_STOP_BIT)
233 #define MLXBF_I2C_MASTER_ENABLE_WRITE \
234 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_WRITE_BIT)
236 #define MLXBF_I2C_MASTER_ENABLE_READ \
237 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_READ_BIT)
239 #define MLXBF_I2C_MASTER_SLV_ADDR_SHIFT 12 /* Slave address shift. */
240 #define MLXBF_I2C_MASTER_WRITE_SHIFT 21 /* Control write bytes shift. */
241 #define MLXBF_I2C_MASTER_SEND_PEC_SHIFT 20 /* Send PEC byte shift. */
242 #define MLXBF_I2C_MASTER_PARSE_EXP_SHIFT 11 /* Parse expected bytes shift. */
243 #define MLXBF_I2C_MASTER_READ_SHIFT 4 /* Control read bytes shift. */
245 /* SMBus master GW Data descriptor. */
246 #define MLXBF_I2C_MASTER_DATA_DESC_ADDR 0x280
247 #define MLXBF_I2C_MASTER_DATA_DESC_SIZE 0x80 /* Size in bytes. */
249 /* Maximum bytes to read/write per SMBus transaction. */
250 #define MLXBF_I2C_MASTER_DATA_R_LENGTH MLXBF_I2C_MASTER_DATA_DESC_SIZE
251 #define MLXBF_I2C_MASTER_DATA_W_LENGTH (MLXBF_I2C_MASTER_DATA_DESC_SIZE - 1)
253 /* All bytes were transmitted. */
254 #define MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE BIT(0)
256 #define MLXBF_I2C_SMBUS_STATUS_NACK_RCV BIT(1)
257 /* Slave's byte count >128 bytes. */
258 #define MLXBF_I2C_SMBUS_STATUS_READ_ERR BIT(2)
259 /* Timeout occurred. */
260 #define MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT BIT(3)
262 #define MLXBF_I2C_SMBUS_MASTER_STATUS_MASK GENMASK(3, 0)
264 #define MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR \
265 (MLXBF_I2C_SMBUS_STATUS_NACK_RCV | \
266 MLXBF_I2C_SMBUS_STATUS_READ_ERR | \
267 MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT)
269 #define MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK BIT(31)
270 #define MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK BIT(15)
272 /* SMBus slave GW. */
273 #define MLXBF_I2C_SMBUS_SLAVE_GW 0x400
274 /* Number of bytes received and sent from/to master. */
275 #define MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES 0x500
276 /* Packet error check (PEC) value. */
277 #define MLXBF_I2C_SMBUS_SLAVE_PEC 0x504
278 /* SMBus slave Finite State Machine (FSM). */
279 #define MLXBF_I2C_SMBUS_SLAVE_FSM 0x510
281 * Should be set when all raised causes handled, and cleared by HW on
284 #define MLXBF_I2C_SMBUS_SLAVE_READY 0x52c
286 /* SMBus slave GW control bits offset in MLXBF_I2C_SMBUS_SLAVE_GW[31:19]. */
287 #define MLXBF_I2C_SLAVE_BUSY_BIT BIT(30) /* Busy bit. */
288 #define MLXBF_I2C_SLAVE_WRITE_BIT BIT(29) /* Control write enable. */
290 #define MLXBF_I2C_SLAVE_ENABLE \
291 (MLXBF_I2C_SLAVE_BUSY_BIT | MLXBF_I2C_SLAVE_WRITE_BIT)
293 #define MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT 22 /* Number of bytes to write. */
294 #define MLXBF_I2C_SLAVE_SEND_PEC_SHIFT 21 /* Send PEC byte shift. */
296 /* SMBus slave GW Data descriptor. */
297 #define MLXBF_I2C_SLAVE_DATA_DESC_ADDR 0x480
298 #define MLXBF_I2C_SLAVE_DATA_DESC_SIZE 0x80 /* Size in bytes. */
300 /* SMbus slave configuration registers. */
301 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG 0x514
302 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT 16
303 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT 7
304 #define MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK GENMASK(6, 0)
306 #define MLXBF_I2C_SLAVE_ADDR_ENABLED(addr) \
307 ((addr) & (1 << MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT))
310 * Timeout is given in microsends. Note also that timeout handling is not
313 #define MLXBF_I2C_SMBUS_TIMEOUT (300 * 1000) /* 300ms */
315 /* Encapsulates timing parameters. */
316 struct mlxbf_i2c_timings {
317 u16 scl_high; /* Clock high period. */
318 u16 scl_low; /* Clock low period. */
319 u8 sda_rise; /* Data rise time. */
320 u8 sda_fall; /* Data fall time. */
321 u8 scl_rise; /* Clock rise time. */
322 u8 scl_fall; /* Clock fall time. */
323 u16 hold_start; /* Hold time after (REPEATED) START. */
324 u16 hold_data; /* Data hold time. */
325 u16 setup_start; /* REPEATED START condition setup time. */
326 u16 setup_stop; /* STOP condition setup time. */
327 u16 setup_data; /* Data setup time. */
328 u16 pad; /* Padding. */
329 u16 buf; /* Bus free time between STOP and START. */
330 u16 thigh_max; /* Thigh max. */
331 u32 timeout; /* Detect clock low timeout. */
335 MLXBF_I2C_F_READ = BIT(0),
336 MLXBF_I2C_F_WRITE = BIT(1),
337 MLXBF_I2C_F_NORESTART = BIT(3),
338 MLXBF_I2C_F_SMBUS_OPERATION = BIT(4),
339 MLXBF_I2C_F_SMBUS_BLOCK = BIT(5),
340 MLXBF_I2C_F_SMBUS_PEC = BIT(6),
341 MLXBF_I2C_F_SMBUS_PROCESS_CALL = BIT(7),
344 struct mlxbf_i2c_smbus_operation {
346 u32 length; /* Buffer length in bytes. */
350 #define MLXBF_I2C_SMBUS_OP_CNT_1 1
351 #define MLXBF_I2C_SMBUS_OP_CNT_2 2
352 #define MLXBF_I2C_SMBUS_OP_CNT_3 3
353 #define MLXBF_I2C_SMBUS_MAX_OP_CNT MLXBF_I2C_SMBUS_OP_CNT_3
355 struct mlxbf_i2c_smbus_request {
358 struct mlxbf_i2c_smbus_operation operation[MLXBF_I2C_SMBUS_MAX_OP_CNT];
361 struct mlxbf_i2c_resource {
363 struct resource *params;
364 struct mutex *lock; /* Mutex to protect mlxbf_i2c_resource. */
368 /* List of chip resources that are being accessed by the driver. */
371 MLXBF_I2C_MST_CAUSE_RES,
372 MLXBF_I2C_SLV_CAUSE_RES,
373 MLXBF_I2C_COALESCE_RES,
374 MLXBF_I2C_COREPLL_RES,
379 /* Helper macro to define an I2C resource parameters. */
380 #define MLXBF_I2C_RES_PARAMS(addr, size, str) \
383 .end = (addr) + (size) - 1, \
387 static struct resource mlxbf_i2c_coalesce_tyu_params =
388 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COALESCE_TYU_ADDR,
389 MLXBF_I2C_COALESCE_TYU_SIZE,
391 static struct resource mlxbf_i2c_corepll_tyu_params =
392 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_TYU_ADDR,
393 MLXBF_I2C_COREPLL_TYU_SIZE,
395 static struct resource mlxbf_i2c_corepll_yu_params =
396 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_YU_ADDR,
397 MLXBF_I2C_COREPLL_YU_SIZE,
399 static struct resource mlxbf_i2c_gpio_tyu_params =
400 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_GPIO_TYU_ADDR,
401 MLXBF_I2C_GPIO_TYU_SIZE,
404 static struct mutex mlxbf_i2c_coalesce_lock;
405 static struct mutex mlxbf_i2c_corepll_lock;
406 static struct mutex mlxbf_i2c_gpio_lock;
408 /* Mellanox BlueField chip type. */
409 enum mlxbf_i2c_chip_type {
410 MLXBF_I2C_CHIP_TYPE_1, /* Mellanox BlueField-1 chip. */
411 MLXBF_I2C_CHIP_TYPE_2, /* Mallanox BlueField-2 chip. */
414 struct mlxbf_i2c_chip_info {
415 enum mlxbf_i2c_chip_type type;
416 /* Chip shared resources that are being used by the I2C controller. */
417 struct mlxbf_i2c_resource *shared_res[MLXBF_I2C_SHARED_RES_MAX];
419 /* Callback to calculate the core PLL frequency. */
420 u64 (*calculate_freq)(struct mlxbf_i2c_resource *corepll_res);
423 struct mlxbf_i2c_priv {
424 const struct mlxbf_i2c_chip_info *chip;
425 struct i2c_adapter adap;
426 struct mlxbf_i2c_resource *smbus;
427 struct mlxbf_i2c_resource *mst_cause;
428 struct mlxbf_i2c_resource *slv_cause;
429 struct mlxbf_i2c_resource *coalesce;
430 u64 frequency; /* Core frequency in Hz. */
431 int bus; /* Physical bus identifier. */
433 struct i2c_client *slave;
436 static struct mlxbf_i2c_resource mlxbf_i2c_coalesce_res[] = {
437 [MLXBF_I2C_CHIP_TYPE_1] = {
438 .params = &mlxbf_i2c_coalesce_tyu_params,
439 .lock = &mlxbf_i2c_coalesce_lock,
440 .type = MLXBF_I2C_COALESCE_RES
445 static struct mlxbf_i2c_resource mlxbf_i2c_corepll_res[] = {
446 [MLXBF_I2C_CHIP_TYPE_1] = {
447 .params = &mlxbf_i2c_corepll_tyu_params,
448 .lock = &mlxbf_i2c_corepll_lock,
449 .type = MLXBF_I2C_COREPLL_RES
451 [MLXBF_I2C_CHIP_TYPE_2] = {
452 .params = &mlxbf_i2c_corepll_yu_params,
453 .lock = &mlxbf_i2c_corepll_lock,
454 .type = MLXBF_I2C_COREPLL_RES,
458 static struct mlxbf_i2c_resource mlxbf_i2c_gpio_res[] = {
459 [MLXBF_I2C_CHIP_TYPE_1] = {
460 .params = &mlxbf_i2c_gpio_tyu_params,
461 .lock = &mlxbf_i2c_gpio_lock,
462 .type = MLXBF_I2C_GPIO_RES
467 static u8 mlxbf_i2c_bus_count;
469 static struct mutex mlxbf_i2c_bus_lock;
471 /* Polling frequency in microseconds. */
472 #define MLXBF_I2C_POLL_FREQ_IN_USEC 200
474 #define MLXBF_I2C_SHIFT_0 0
475 #define MLXBF_I2C_SHIFT_8 8
476 #define MLXBF_I2C_SHIFT_16 16
477 #define MLXBF_I2C_SHIFT_24 24
479 #define MLXBF_I2C_MASK_8 GENMASK(7, 0)
480 #define MLXBF_I2C_MASK_16 GENMASK(15, 0)
482 #define MLXBF_I2C_FREQUENCY_1GHZ 1000000000
485 * Function to poll a set of bits at a specific address; it checks whether
486 * the bits are equal to zero when eq_zero is set to 'true', and not equal
487 * to zero when eq_zero is set to 'false'.
488 * Note that the timeout is given in microseconds.
490 static u32 mlxbf_smbus_poll(void __iomem *io, u32 addr, u32 mask,
491 bool eq_zero, u32 timeout)
495 timeout = (timeout / MLXBF_I2C_POLL_FREQ_IN_USEC) + 1;
498 bits = readl(io + addr) & mask;
499 if (eq_zero ? bits == 0 : bits != 0)
500 return eq_zero ? 1 : bits;
501 udelay(MLXBF_I2C_POLL_FREQ_IN_USEC);
502 } while (timeout-- != 0);
508 * SW must make sure that the SMBus Master GW is idle before starting
509 * a transaction. Accordingly, this function polls the Master FSM stop
510 * bit; it returns false when the bit is asserted, true if not.
512 static bool mlxbf_smbus_master_wait_for_idle(struct mlxbf_i2c_priv *priv)
514 u32 mask = MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK;
515 u32 addr = MLXBF_I2C_SMBUS_MASTER_FSM;
516 u32 timeout = MLXBF_I2C_SMBUS_TIMEOUT;
518 if (mlxbf_smbus_poll(priv->smbus->io, addr, mask, true, timeout))
524 static bool mlxbf_i2c_smbus_transaction_success(u32 master_status,
528 * When transaction ended with STOP, all bytes were transmitted,
529 * and no NACK received, then the transaction ended successfully.
530 * On the other hand, when the GW is configured with the stop bit
531 * de-asserted then the SMBus expects the following GW configuration
532 * for transfer continuation.
534 if ((cause_status & MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA) ||
535 ((cause_status & MLXBF_I2C_CAUSE_TRANSACTION_ENDED) &&
536 (master_status & MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE) &&
537 !(master_status & MLXBF_I2C_SMBUS_STATUS_NACK_RCV)))
544 * Poll SMBus master status and return transaction status,
545 * i.e. whether succeeded or failed. I2C and SMBus fault codes
546 * are returned as negative numbers from most calls, with zero
547 * or some positive number indicating a non-fault return.
549 static int mlxbf_i2c_smbus_check_status(struct mlxbf_i2c_priv *priv)
551 u32 master_status_bits;
552 u32 cause_status_bits;
555 * GW busy bit is raised by the driver and cleared by the HW
556 * when the transaction is completed. The busy bit is a good
557 * indicator of transaction status. So poll the busy bit, and
558 * then read the cause and master status bits to determine if
559 * errors occurred during the transaction.
561 mlxbf_smbus_poll(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_GW,
562 MLXBF_I2C_MASTER_BUSY_BIT, true,
563 MLXBF_I2C_SMBUS_TIMEOUT);
565 /* Read cause status bits. */
566 cause_status_bits = readl(priv->mst_cause->io +
567 MLXBF_I2C_CAUSE_ARBITER);
568 cause_status_bits &= MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK;
571 * Parse both Cause and Master GW bits, then return transaction status.
574 master_status_bits = readl(priv->smbus->io +
575 MLXBF_I2C_SMBUS_MASTER_STATUS);
576 master_status_bits &= MLXBF_I2C_SMBUS_MASTER_STATUS_MASK;
578 if (mlxbf_i2c_smbus_transaction_success(master_status_bits,
583 * In case of timeout on GW busy, the ISR will clear busy bit but
584 * transaction ended bits cause will not be set so the transaction
585 * fails. Then, we must check Master GW status bits.
587 if ((master_status_bits & MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR) &&
588 (cause_status_bits & (MLXBF_I2C_CAUSE_TRANSACTION_ENDED |
589 MLXBF_I2C_CAUSE_M_GW_BUSY_FALL)))
592 if (cause_status_bits & MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR)
598 static void mlxbf_i2c_smbus_write_data(struct mlxbf_i2c_priv *priv,
599 const u8 *data, u8 length, u32 addr)
601 u8 offset, aligned_length;
604 aligned_length = round_up(length, 4);
607 * Copy data bytes from 4-byte aligned source buffer.
608 * Data copied to the Master GW Data Descriptor MUST be shifted
609 * left so the data starts at the MSB of the descriptor registers
610 * as required by the underlying hardware. Enable byte swapping
611 * when writing data bytes to the 32 * 32-bit HW Data registers
612 * a.k.a Master GW Data Descriptor.
614 for (offset = 0; offset < aligned_length; offset += sizeof(u32)) {
615 data32 = *((u32 *)(data + offset));
616 iowrite32be(data32, priv->smbus->io + addr + offset);
620 static void mlxbf_i2c_smbus_read_data(struct mlxbf_i2c_priv *priv,
621 u8 *data, u8 length, u32 addr)
626 mask = sizeof(u32) - 1;
629 * Data bytes in the Master GW Data Descriptor are shifted left
630 * so the data starts at the MSB of the descriptor registers as
631 * set by the underlying hardware. Enable byte swapping while
632 * reading data bytes from the 32 * 32-bit HW Data registers
633 * a.k.a Master GW Data Descriptor.
636 for (offset = 0; offset < (length & ~mask); offset += sizeof(u32)) {
637 data32 = ioread32be(priv->smbus->io + addr + offset);
638 *((u32 *)(data + offset)) = data32;
641 if (!(length & mask))
644 data32 = ioread32be(priv->smbus->io + addr + offset);
646 for (byte = 0; byte < (length & mask); byte++) {
647 data[offset + byte] = data32 & GENMASK(7, 0);
648 data32 = ror32(data32, MLXBF_I2C_SHIFT_8);
652 static int mlxbf_i2c_smbus_enable(struct mlxbf_i2c_priv *priv, u8 slave,
653 u8 len, u8 block_en, u8 pec_en, bool read)
657 /* Set Master GW control word. */
659 command = MLXBF_I2C_MASTER_ENABLE_READ;
660 command |= rol32(len, MLXBF_I2C_MASTER_READ_SHIFT);
662 command = MLXBF_I2C_MASTER_ENABLE_WRITE;
663 command |= rol32(len, MLXBF_I2C_MASTER_WRITE_SHIFT);
665 command |= rol32(slave, MLXBF_I2C_MASTER_SLV_ADDR_SHIFT);
666 command |= rol32(block_en, MLXBF_I2C_MASTER_PARSE_EXP_SHIFT);
667 command |= rol32(pec_en, MLXBF_I2C_MASTER_SEND_PEC_SHIFT);
669 /* Clear status bits. */
670 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_STATUS);
671 /* Set the cause data. */
672 writel(~0x0, priv->mst_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR);
674 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_PEC);
675 /* Zero byte count. */
676 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_RS_BYTES);
679 writel(command, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_GW);
682 * Poll master status and check status bits. An ACK is sent when
683 * completing writing data to the bus (Master 'byte_count_done' bit
686 return mlxbf_i2c_smbus_check_status(priv);
690 mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv,
691 struct mlxbf_i2c_smbus_request *request)
693 u8 data_desc[MLXBF_I2C_MASTER_DATA_DESC_SIZE] = { 0 };
694 u8 op_idx, data_idx, data_len, write_len, read_len;
695 struct mlxbf_i2c_smbus_operation *operation;
696 u8 read_en, write_en, block_en, pec_en;
697 u8 slave, flags, addr;
701 if (request->operation_cnt > MLXBF_I2C_SMBUS_MAX_OP_CNT)
712 slave = request->slave & GENMASK(6, 0);
715 /* First of all, check whether the HW is idle. */
716 if (WARN_ON(!mlxbf_smbus_master_wait_for_idle(priv)))
719 /* Set first byte. */
720 data_desc[data_idx++] = addr;
722 for (op_idx = 0; op_idx < request->operation_cnt; op_idx++) {
723 operation = &request->operation[op_idx];
724 flags = operation->flags;
727 * Note that read and write operations might be handled by a
728 * single command. If the MLXBF_I2C_F_SMBUS_OPERATION is set
729 * then write command byte and set the optional SMBus specific
730 * bits such as block_en and pec_en. These bits MUST be
731 * submitted by the first operation only.
733 if (op_idx == 0 && flags & MLXBF_I2C_F_SMBUS_OPERATION) {
734 block_en = flags & MLXBF_I2C_F_SMBUS_BLOCK;
735 pec_en = flags & MLXBF_I2C_F_SMBUS_PEC;
738 if (flags & MLXBF_I2C_F_WRITE) {
740 write_len += operation->length;
741 if (data_idx + operation->length >
742 MLXBF_I2C_MASTER_DATA_DESC_SIZE)
744 memcpy(data_desc + data_idx,
745 operation->buffer, operation->length);
746 data_idx += operation->length;
749 * We assume that read operations are performed only once per
750 * SMBus transaction. *TBD* protect this statement so it won't
751 * be executed twice? or return an error if we try to read more
754 if (flags & MLXBF_I2C_F_READ) {
756 /* Subtract 1 as required by HW. */
757 read_len = operation->length - 1;
758 read_buf = operation->buffer;
762 /* Set Master GW data descriptor. */
763 data_len = write_len + 1; /* Add one byte of the slave address. */
765 * Note that data_len cannot be 0. Indeed, the slave address byte
766 * must be written to the data registers.
768 mlxbf_i2c_smbus_write_data(priv, (const u8 *)data_desc, data_len,
769 MLXBF_I2C_MASTER_DATA_DESC_ADDR);
772 ret = mlxbf_i2c_smbus_enable(priv, slave, write_len, block_en,
779 /* Write slave address to Master GW data descriptor. */
780 mlxbf_i2c_smbus_write_data(priv, (const u8 *)&addr, 1,
781 MLXBF_I2C_MASTER_DATA_DESC_ADDR);
782 ret = mlxbf_i2c_smbus_enable(priv, slave, read_len, block_en,
785 /* Get Master GW data descriptor. */
786 mlxbf_i2c_smbus_read_data(priv, data_desc, read_len + 1,
787 MLXBF_I2C_MASTER_DATA_DESC_ADDR);
789 /* Get data from Master GW data descriptor. */
790 memcpy(read_buf, data_desc, read_len + 1);
794 * After a read operation the SMBus FSM ps (present state)
795 * needs to be 'manually' reset. This should be removed in
796 * next tag integration.
798 writel(MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK,
799 priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_FSM);
805 /* I2C SMBus protocols. */
808 mlxbf_i2c_smbus_quick_command(struct mlxbf_i2c_smbus_request *request,
811 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1;
813 request->operation[0].length = 0;
814 request->operation[0].flags = MLXBF_I2C_F_WRITE;
815 request->operation[0].flags |= read ? MLXBF_I2C_F_READ : 0;
818 static void mlxbf_i2c_smbus_byte_func(struct mlxbf_i2c_smbus_request *request,
819 u8 *data, bool read, bool pec_check)
821 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1;
823 request->operation[0].length = 1;
824 request->operation[0].length += pec_check;
826 request->operation[0].flags = MLXBF_I2C_F_SMBUS_OPERATION;
827 request->operation[0].flags |= read ?
828 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;
829 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
831 request->operation[0].buffer = data;
835 mlxbf_i2c_smbus_data_byte_func(struct mlxbf_i2c_smbus_request *request,
836 u8 *command, u8 *data, bool read, bool pec_check)
838 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2;
840 request->operation[0].length = 1;
841 request->operation[0].flags =
842 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
843 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
844 request->operation[0].buffer = command;
846 request->operation[1].length = 1;
847 request->operation[1].length += pec_check;
848 request->operation[1].flags = read ?
849 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;
850 request->operation[1].buffer = data;
854 mlxbf_i2c_smbus_data_word_func(struct mlxbf_i2c_smbus_request *request,
855 u8 *command, u8 *data, bool read, bool pec_check)
857 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2;
859 request->operation[0].length = 1;
860 request->operation[0].flags =
861 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
862 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
863 request->operation[0].buffer = command;
865 request->operation[1].length = 2;
866 request->operation[1].length += pec_check;
867 request->operation[1].flags = read ?
868 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;
869 request->operation[1].buffer = data;
873 mlxbf_i2c_smbus_i2c_block_func(struct mlxbf_i2c_smbus_request *request,
874 u8 *command, u8 *data, u8 *data_len, bool read,
877 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2;
879 request->operation[0].length = 1;
880 request->operation[0].flags =
881 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
882 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
883 request->operation[0].buffer = command;
886 * As specified in the standard, the max number of bytes to read/write
887 * per block operation is 32 bytes. In Golan code, the controller can
888 * read up to 128 bytes and write up to 127 bytes.
890 request->operation[1].length =
891 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ?
892 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check;
893 request->operation[1].flags = read ?
894 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;
896 * Skip the first data byte, which corresponds to the number of bytes
899 request->operation[1].buffer = data + 1;
901 *data_len = request->operation[1].length;
903 /* Set the number of byte to read. This will be used by userspace. */
908 static void mlxbf_i2c_smbus_block_func(struct mlxbf_i2c_smbus_request *request,
909 u8 *command, u8 *data, u8 *data_len,
910 bool read, bool pec_check)
912 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2;
914 request->operation[0].length = 1;
915 request->operation[0].flags =
916 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
917 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK;
918 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
919 request->operation[0].buffer = command;
921 request->operation[1].length =
922 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ?
923 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check;
924 request->operation[1].flags = read ?
925 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;
926 request->operation[1].buffer = data + 1;
928 *data_len = request->operation[1].length;
930 /* Set the number of bytes to read. This will be used by userspace. */
936 mlxbf_i2c_smbus_process_call_func(struct mlxbf_i2c_smbus_request *request,
937 u8 *command, u8 *data, bool pec_check)
939 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3;
941 request->operation[0].length = 1;
942 request->operation[0].flags =
943 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
944 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK;
945 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
946 request->operation[0].buffer = command;
948 request->operation[1].length = 2;
949 request->operation[1].flags = MLXBF_I2C_F_WRITE;
950 request->operation[1].buffer = data;
952 request->operation[2].length = 3;
953 request->operation[2].flags = MLXBF_I2C_F_READ;
954 request->operation[2].buffer = data;
958 mlxbf_i2c_smbus_blk_process_call_func(struct mlxbf_i2c_smbus_request *request,
959 u8 *command, u8 *data, u8 *data_len,
964 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3;
966 request->operation[0].length = 1;
967 request->operation[0].flags =
968 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
969 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK;
970 request->operation[0].flags |= (pec_check) ? MLXBF_I2C_F_SMBUS_PEC : 0;
971 request->operation[0].buffer = command;
973 length = (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ?
974 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check;
976 request->operation[1].length = length - pec_check;
977 request->operation[1].flags = MLXBF_I2C_F_WRITE;
978 request->operation[1].buffer = data;
980 request->operation[2].length = length;
981 request->operation[2].flags = MLXBF_I2C_F_READ;
982 request->operation[2].buffer = data;
984 *data_len = length; /* including PEC byte. */
987 /* Initialization functions. */
989 static bool mlxbf_i2c_has_chip_type(struct mlxbf_i2c_priv *priv, u8 type)
991 return priv->chip->type == type;
994 static struct mlxbf_i2c_resource *
995 mlxbf_i2c_get_shared_resource(struct mlxbf_i2c_priv *priv, u8 type)
997 const struct mlxbf_i2c_chip_info *chip = priv->chip;
998 struct mlxbf_i2c_resource *res;
1001 for (res_idx = 0; res_idx < MLXBF_I2C_SHARED_RES_MAX; res_idx++) {
1002 res = chip->shared_res[res_idx];
1003 if (res && res->type == type)
1010 static int mlxbf_i2c_init_resource(struct platform_device *pdev,
1011 struct mlxbf_i2c_resource **res,
1014 struct mlxbf_i2c_resource *tmp_res;
1015 struct device *dev = &pdev->dev;
1017 if (!res || *res || type >= MLXBF_I2C_END_RES)
1020 tmp_res = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource),
1025 tmp_res->params = platform_get_resource(pdev, IORESOURCE_MEM, type);
1026 if (!tmp_res->params) {
1027 devm_kfree(dev, tmp_res);
1031 tmp_res->io = devm_ioremap_resource(dev, tmp_res->params);
1032 if (IS_ERR(tmp_res->io)) {
1033 devm_kfree(dev, tmp_res);
1034 return PTR_ERR(tmp_res->io);
1037 tmp_res->type = type;
1044 static u32 mlxbf_i2c_get_ticks(struct mlxbf_i2c_priv *priv, u64 nanoseconds,
1051 * Compute ticks as follow:
1054 * Time = --------- x 10^9 => Ticks = Time x Frequency x 10^-9
1057 frequency = priv->frequency;
1058 ticks = (nanoseconds * frequency) / MLXBF_I2C_FREQUENCY_1GHZ;
1060 * The number of ticks is rounded down and if minimum is equal to 1
1061 * then add one tick.
1069 static u32 mlxbf_i2c_set_timer(struct mlxbf_i2c_priv *priv, u64 nsec, bool opt,
1072 u32 val = (mlxbf_i2c_get_ticks(priv, nsec, opt) & mask) << shift;
1077 static void mlxbf_i2c_set_timings(struct mlxbf_i2c_priv *priv,
1078 const struct mlxbf_i2c_timings *timings)
1082 timer = mlxbf_i2c_set_timer(priv, timings->scl_high,
1083 false, MLXBF_I2C_MASK_16,
1085 timer |= mlxbf_i2c_set_timer(priv, timings->scl_low,
1086 false, MLXBF_I2C_MASK_16,
1087 MLXBF_I2C_SHIFT_16);
1088 writel(timer, priv->smbus->io +
1089 MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH);
1091 timer = mlxbf_i2c_set_timer(priv, timings->sda_rise, false,
1092 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_0);
1093 timer |= mlxbf_i2c_set_timer(priv, timings->sda_fall, false,
1094 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_8);
1095 timer |= mlxbf_i2c_set_timer(priv, timings->scl_rise, false,
1096 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_16);
1097 timer |= mlxbf_i2c_set_timer(priv, timings->scl_fall, false,
1098 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_24);
1099 writel(timer, priv->smbus->io +
1100 MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE);
1102 timer = mlxbf_i2c_set_timer(priv, timings->hold_start, true,
1103 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
1104 timer |= mlxbf_i2c_set_timer(priv, timings->hold_data, true,
1105 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);
1106 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_TIMER_THOLD);
1108 timer = mlxbf_i2c_set_timer(priv, timings->setup_start, true,
1109 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
1110 timer |= mlxbf_i2c_set_timer(priv, timings->setup_stop, true,
1111 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);
1112 writel(timer, priv->smbus->io +
1113 MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP);
1115 timer = mlxbf_i2c_set_timer(priv, timings->setup_data, true,
1116 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
1117 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA);
1119 timer = mlxbf_i2c_set_timer(priv, timings->buf, false,
1120 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
1121 timer |= mlxbf_i2c_set_timer(priv, timings->thigh_max, false,
1122 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);
1123 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_THIGH_MAX_TBUF);
1125 timer = timings->timeout;
1126 writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT);
1129 enum mlxbf_i2c_timings_config {
1130 MLXBF_I2C_TIMING_CONFIG_100KHZ,
1131 MLXBF_I2C_TIMING_CONFIG_400KHZ,
1132 MLXBF_I2C_TIMING_CONFIG_1000KHZ,
1136 * Note that the mlxbf_i2c_timings->timeout value is not related to the
1137 * bus frequency, it is impacted by the time it takes the driver to
1138 * complete data transmission before transaction abort.
1140 static const struct mlxbf_i2c_timings mlxbf_i2c_timings[] = {
1141 [MLXBF_I2C_TIMING_CONFIG_100KHZ] = {
1145 .setup_start = 4800,
1157 [MLXBF_I2C_TIMING_CONFIG_400KHZ] = {
1173 [MLXBF_I2C_TIMING_CONFIG_1000KHZ] = {
1191 static int mlxbf_i2c_init_timings(struct platform_device *pdev,
1192 struct mlxbf_i2c_priv *priv)
1194 enum mlxbf_i2c_timings_config config_idx;
1195 struct device *dev = &pdev->dev;
1200 ret = device_property_read_u32(dev, "clock-frequency", &config_khz);
1202 config_khz = I2C_MAX_STANDARD_MODE_FREQ;
1204 switch (config_khz) {
1206 /* Default settings is 100 KHz. */
1207 pr_warn("Illegal value %d: defaulting to 100 KHz\n",
1210 case I2C_MAX_STANDARD_MODE_FREQ:
1211 config_idx = MLXBF_I2C_TIMING_CONFIG_100KHZ;
1214 case I2C_MAX_FAST_MODE_FREQ:
1215 config_idx = MLXBF_I2C_TIMING_CONFIG_400KHZ;
1218 case I2C_MAX_FAST_MODE_PLUS_FREQ:
1219 config_idx = MLXBF_I2C_TIMING_CONFIG_1000KHZ;
1223 mlxbf_i2c_set_timings(priv, &mlxbf_i2c_timings[config_idx]);
1228 static int mlxbf_i2c_get_gpio(struct platform_device *pdev,
1229 struct mlxbf_i2c_priv *priv)
1231 struct mlxbf_i2c_resource *gpio_res;
1232 struct device *dev = &pdev->dev;
1233 struct resource *params;
1234 resource_size_t size;
1236 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES);
1241 * The GPIO region in TYU space is shared among I2C busses.
1242 * This function MUST be serialized to avoid racing when
1243 * claiming the memory region and/or setting up the GPIO.
1245 lockdep_assert_held(gpio_res->lock);
1247 /* Check whether the memory map exist. */
1251 params = gpio_res->params;
1252 size = resource_size(params);
1254 if (!devm_request_mem_region(dev, params->start, size, params->name))
1257 gpio_res->io = devm_ioremap(dev, params->start, size);
1258 if (!gpio_res->io) {
1259 devm_release_mem_region(dev, params->start, size);
1266 static int mlxbf_i2c_release_gpio(struct platform_device *pdev,
1267 struct mlxbf_i2c_priv *priv)
1269 struct mlxbf_i2c_resource *gpio_res;
1270 struct device *dev = &pdev->dev;
1271 struct resource *params;
1273 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES);
1277 mutex_lock(gpio_res->lock);
1280 /* Release the GPIO resource. */
1281 params = gpio_res->params;
1282 devm_iounmap(dev, gpio_res->io);
1283 devm_release_mem_region(dev, params->start,
1284 resource_size(params));
1287 mutex_unlock(gpio_res->lock);
1292 static int mlxbf_i2c_get_corepll(struct platform_device *pdev,
1293 struct mlxbf_i2c_priv *priv)
1295 struct mlxbf_i2c_resource *corepll_res;
1296 struct device *dev = &pdev->dev;
1297 struct resource *params;
1298 resource_size_t size;
1300 corepll_res = mlxbf_i2c_get_shared_resource(priv,
1301 MLXBF_I2C_COREPLL_RES);
1306 * The COREPLL region in TYU space is shared among I2C busses.
1307 * This function MUST be serialized to avoid racing when
1308 * claiming the memory region.
1310 lockdep_assert_held(corepll_res->lock);
1312 /* Check whether the memory map exist. */
1313 if (corepll_res->io)
1316 params = corepll_res->params;
1317 size = resource_size(params);
1319 if (!devm_request_mem_region(dev, params->start, size, params->name))
1322 corepll_res->io = devm_ioremap(dev, params->start, size);
1323 if (!corepll_res->io) {
1324 devm_release_mem_region(dev, params->start, size);
1331 static int mlxbf_i2c_release_corepll(struct platform_device *pdev,
1332 struct mlxbf_i2c_priv *priv)
1334 struct mlxbf_i2c_resource *corepll_res;
1335 struct device *dev = &pdev->dev;
1336 struct resource *params;
1338 corepll_res = mlxbf_i2c_get_shared_resource(priv,
1339 MLXBF_I2C_COREPLL_RES);
1341 mutex_lock(corepll_res->lock);
1343 if (corepll_res->io) {
1344 /* Release the CorePLL resource. */
1345 params = corepll_res->params;
1346 devm_iounmap(dev, corepll_res->io);
1347 devm_release_mem_region(dev, params->start,
1348 resource_size(params));
1351 mutex_unlock(corepll_res->lock);
1356 static int mlxbf_i2c_init_master(struct platform_device *pdev,
1357 struct mlxbf_i2c_priv *priv)
1359 struct mlxbf_i2c_resource *gpio_res;
1360 struct device *dev = &pdev->dev;
1364 /* This configuration is only needed for BlueField 1. */
1365 if (!mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1))
1368 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES);
1373 * The GPIO region in TYU space is shared among I2C busses.
1374 * This function MUST be serialized to avoid racing when
1375 * claiming the memory region and/or setting up the GPIO.
1378 mutex_lock(gpio_res->lock);
1380 ret = mlxbf_i2c_get_gpio(pdev, priv);
1382 dev_err(dev, "Failed to get gpio resource");
1383 mutex_unlock(gpio_res->lock);
1388 * TYU - Configuration for GPIO pins. Those pins must be asserted in
1389 * MLXBF_I2C_GPIO_0_FUNC_EN_0, i.e. GPIO 0 is controlled by HW, and must
1390 * be reset in MLXBF_I2C_GPIO_0_FORCE_OE_EN, i.e. GPIO_OE will be driven
1392 * For now, we do not reset the GPIO state when the driver is removed.
1393 * First, it is not necessary to disable the bus since we are using
1394 * the same busses. Then, some busses might be shared among Linux and
1395 * platform firmware; disabling the bus might compromise the system
1398 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0);
1399 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(priv->bus,
1401 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0);
1403 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN);
1404 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(priv->bus,
1406 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN);
1408 mutex_unlock(gpio_res->lock);
1413 static u64 mlxbf_calculate_freq_from_tyu(struct mlxbf_i2c_resource *corepll_res)
1415 u64 core_frequency, pad_frequency;
1420 pad_frequency = MLXBF_I2C_PLL_IN_FREQ;
1422 corepll_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1);
1424 /* Get Core PLL configuration bits. */
1425 core_f = rol32(corepll_val, MLXBF_I2C_COREPLL_CORE_F_TYU_SHIFT) &
1426 MLXBF_I2C_COREPLL_CORE_F_TYU_MASK;
1427 core_od = rol32(corepll_val, MLXBF_I2C_COREPLL_CORE_OD_TYU_SHIFT) &
1428 MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK;
1429 core_r = rol32(corepll_val, MLXBF_I2C_COREPLL_CORE_R_TYU_SHIFT) &
1430 MLXBF_I2C_COREPLL_CORE_R_TYU_MASK;
1433 * Compute PLL output frequency as follow:
1436 * PLL_OUT_FREQ = PLL_IN_FREQ * ----------------------------
1437 * (CORE_R + 1) * (CORE_OD + 1)
1439 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency
1440 * and PadFrequency, respectively.
1442 core_frequency = pad_frequency * (++core_f);
1443 core_frequency /= (++core_r) * (++core_od);
1445 return core_frequency;
1448 static u64 mlxbf_calculate_freq_from_yu(struct mlxbf_i2c_resource *corepll_res)
1450 u32 corepll_reg1_val, corepll_reg2_val;
1451 u64 corepll_frequency, pad_frequency;
1455 pad_frequency = MLXBF_I2C_PLL_IN_FREQ;
1457 corepll_reg1_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1);
1458 corepll_reg2_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG2);
1460 /* Get Core PLL configuration bits */
1461 core_f = rol32(corepll_reg1_val, MLXBF_I2C_COREPLL_CORE_F_YU_SHIFT) &
1462 MLXBF_I2C_COREPLL_CORE_F_YU_MASK;
1463 core_r = rol32(corepll_reg1_val, MLXBF_I2C_COREPLL_CORE_R_YU_SHIFT) &
1464 MLXBF_I2C_COREPLL_CORE_R_YU_MASK;
1465 core_od = rol32(corepll_reg2_val, MLXBF_I2C_COREPLL_CORE_OD_YU_SHIFT) &
1466 MLXBF_I2C_COREPLL_CORE_OD_YU_MASK;
1469 * Compute PLL output frequency as follow:
1472 * PLL_OUT_FREQ = PLL_IN_FREQ * ----------------------------
1473 * (CORE_R + 1) * (CORE_OD + 1)
1475 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency
1476 * and PadFrequency, respectively.
1478 corepll_frequency = (pad_frequency * core_f) / MLNXBF_I2C_COREPLL_CONST;
1479 corepll_frequency /= (++core_r) * (++core_od);
1481 return corepll_frequency;
1484 static int mlxbf_i2c_calculate_corepll_freq(struct platform_device *pdev,
1485 struct mlxbf_i2c_priv *priv)
1487 const struct mlxbf_i2c_chip_info *chip = priv->chip;
1488 struct mlxbf_i2c_resource *corepll_res;
1489 struct device *dev = &pdev->dev;
1490 u64 *freq = &priv->frequency;
1493 corepll_res = mlxbf_i2c_get_shared_resource(priv,
1494 MLXBF_I2C_COREPLL_RES);
1499 * First, check whether the TYU core Clock frequency is set.
1500 * The TYU core frequency is the same for all I2C busses; when
1501 * the first device gets probed the frequency is determined and
1502 * stored into a globally visible variable. So, first of all,
1503 * check whether the frequency is already set. Here, we assume
1504 * that the frequency is expected to be greater than 0.
1506 mutex_lock(corepll_res->lock);
1507 if (!mlxbf_i2c_corepll_frequency) {
1508 if (!chip->calculate_freq) {
1509 mutex_unlock(corepll_res->lock);
1513 ret = mlxbf_i2c_get_corepll(pdev, priv);
1515 dev_err(dev, "Failed to get corePLL resource");
1516 mutex_unlock(corepll_res->lock);
1520 mlxbf_i2c_corepll_frequency = chip->calculate_freq(corepll_res);
1522 mutex_unlock(corepll_res->lock);
1524 *freq = mlxbf_i2c_corepll_frequency;
1529 static int mlxbf_slave_enable(struct mlxbf_i2c_priv *priv, u8 addr)
1531 u32 slave_reg, slave_reg_tmp, slave_reg_avail, slave_addr_mask;
1532 u8 reg, reg_cnt, byte, addr_tmp, reg_avail, byte_avail;
1533 bool avail, disabled;
1541 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2;
1542 slave_addr_mask = MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK;
1545 * Read the slave registers. There are 4 * 32-bit slave registers.
1546 * Each slave register can hold up to 4 * 8-bit slave configuration
1547 * (7-bit address, 1 status bit (1 if enabled, 0 if not)).
1549 for (reg = 0; reg < reg_cnt; reg++) {
1550 slave_reg = readl(priv->smbus->io +
1551 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4);
1553 * Each register holds 4 slave addresses. So, we have to keep
1554 * the byte order consistent with the value read in order to
1555 * update the register correctly, if needed.
1557 slave_reg_tmp = slave_reg;
1558 for (byte = 0; byte < 4; byte++) {
1559 addr_tmp = slave_reg_tmp & GENMASK(7, 0);
1562 * Mark the first available slave address slot, i.e. its
1563 * enabled bit should be unset. This slot might be used
1564 * later on to register our slave.
1566 if (!avail && !MLXBF_I2C_SLAVE_ADDR_ENABLED(addr_tmp)) {
1570 slave_reg_avail = slave_reg;
1574 * Parse slave address bytes and check whether the
1575 * slave address already exists and it's enabled,
1576 * i.e. most significant bit is set.
1578 if ((addr_tmp & slave_addr_mask) == addr) {
1579 if (MLXBF_I2C_SLAVE_ADDR_ENABLED(addr_tmp))
1585 /* Parse next byte. */
1586 slave_reg_tmp >>= 8;
1589 /* Exit the loop if the slave address is found. */
1594 if (!avail && !disabled)
1595 return -EINVAL; /* No room for a new slave address. */
1597 if (avail && !disabled) {
1600 /* Set the slave address. */
1601 slave_reg_avail &= ~(slave_addr_mask << (byte * 8));
1602 slave_reg_avail |= addr << (byte * 8);
1603 slave_reg = slave_reg_avail;
1606 /* Enable the slave address and update the register. */
1607 slave_reg |= (1 << MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT) << (byte * 8);
1608 writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG +
1614 static int mlxbf_slave_disable(struct mlxbf_i2c_priv *priv)
1616 u32 slave_reg, slave_reg_tmp, slave_addr_mask;
1617 u8 addr, addr_tmp, reg, reg_cnt, slave_byte;
1618 struct i2c_client *client = priv->slave;
1623 addr = client->addr;
1624 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2;
1625 slave_addr_mask = MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK;
1628 * Read the slave registers. There are 4 * 32-bit slave registers.
1629 * Each slave register can hold up to 4 * 8-bit slave configuration
1630 * (7-bit address, 1 status bit (1 if enabled, 0 if not)).
1632 for (reg = 0; reg < reg_cnt; reg++) {
1633 slave_reg = readl(priv->smbus->io +
1634 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4);
1636 /* Check whether the address slots are empty. */
1641 * Each register holds 4 slave addresses. So, we have to keep
1642 * the byte order consistent with the value read in order to
1643 * update the register correctly, if needed.
1645 slave_reg_tmp = slave_reg;
1647 while (slave_reg_tmp != 0) {
1648 addr_tmp = slave_reg_tmp & slave_addr_mask;
1650 * Parse slave address bytes and check whether the
1651 * slave address already exists.
1653 if (addr_tmp == addr) {
1658 /* Parse next byte. */
1659 slave_reg_tmp >>= 8;
1663 /* Exit the loop if the slave address is found. */
1669 return 0; /* Slave is not registered, nothing to do. */
1671 /* Cleanup the slave address slot. */
1672 slave_reg &= ~(GENMASK(7, 0) << (slave_byte * 8));
1673 writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG +
1679 static int mlxbf_i2c_init_coalesce(struct platform_device *pdev,
1680 struct mlxbf_i2c_priv *priv)
1682 struct mlxbf_i2c_resource *coalesce_res;
1683 struct resource *params;
1684 resource_size_t size;
1688 * Unlike BlueField-1 platform, the coalesce registers is a dedicated
1689 * resource in the next generations of BlueField.
1691 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) {
1692 coalesce_res = mlxbf_i2c_get_shared_resource(priv,
1693 MLXBF_I2C_COALESCE_RES);
1698 * The Cause Coalesce group in TYU space is shared among
1699 * I2C busses. This function MUST be serialized to avoid
1700 * racing when claiming the memory region.
1702 lockdep_assert_held(mlxbf_i2c_gpio_res->lock);
1704 /* Check whether the memory map exist. */
1705 if (coalesce_res->io) {
1706 priv->coalesce = coalesce_res;
1710 params = coalesce_res->params;
1711 size = resource_size(params);
1713 if (!request_mem_region(params->start, size, params->name))
1716 coalesce_res->io = ioremap(params->start, size);
1717 if (!coalesce_res->io) {
1718 release_mem_region(params->start, size);
1722 priv->coalesce = coalesce_res;
1725 ret = mlxbf_i2c_init_resource(pdev, &priv->coalesce,
1726 MLXBF_I2C_COALESCE_RES);
1732 static int mlxbf_i2c_release_coalesce(struct platform_device *pdev,
1733 struct mlxbf_i2c_priv *priv)
1735 struct mlxbf_i2c_resource *coalesce_res;
1736 struct device *dev = &pdev->dev;
1737 struct resource *params;
1738 resource_size_t size;
1740 coalesce_res = priv->coalesce;
1742 if (coalesce_res->io) {
1743 params = coalesce_res->params;
1744 size = resource_size(params);
1745 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) {
1746 mutex_lock(coalesce_res->lock);
1747 iounmap(coalesce_res->io);
1748 release_mem_region(params->start, size);
1749 mutex_unlock(coalesce_res->lock);
1751 devm_release_mem_region(dev, params->start, size);
1758 static int mlxbf_i2c_init_slave(struct platform_device *pdev,
1759 struct mlxbf_i2c_priv *priv)
1761 struct device *dev = &pdev->dev;
1766 writel(0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_FSM);
1769 * Enable slave cause interrupt bits. Drive
1770 * MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE and
1771 * MLXBF_I2C_CAUSE_WRITE_SUCCESS, these are enabled when an external
1772 * masters issue a Read and Write, respectively. But, clear all
1775 writel(~0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR);
1776 int_reg = MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE;
1777 int_reg |= MLXBF_I2C_CAUSE_WRITE_SUCCESS;
1778 writel(int_reg, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_EVTEN0);
1780 /* Finally, set the 'ready' bit to start handling transactions. */
1781 writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY);
1783 /* Initialize the cause coalesce resource. */
1784 ret = mlxbf_i2c_init_coalesce(pdev, priv);
1786 dev_err(dev, "failed to initialize cause coalesce\n");
1793 static bool mlxbf_i2c_has_coalesce(struct mlxbf_i2c_priv *priv, bool *read,
1796 const struct mlxbf_i2c_chip_info *chip = priv->chip;
1797 u32 coalesce0_reg, cause_reg;
1798 u8 slave_shift, is_set;
1803 slave_shift = chip->type != MLXBF_I2C_CHIP_TYPE_1 ?
1804 MLXBF_I2C_CAUSE_YU_SLAVE_BIT :
1805 priv->bus + MLXBF_I2C_CAUSE_TYU_SLAVE_BIT;
1807 coalesce0_reg = readl(priv->coalesce->io + MLXBF_I2C_CAUSE_COALESCE_0);
1808 is_set = coalesce0_reg & (1 << slave_shift);
1813 /* Check the source of the interrupt, i.e. whether a Read or Write. */
1814 cause_reg = readl(priv->slv_cause->io + MLXBF_I2C_CAUSE_ARBITER);
1815 if (cause_reg & MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE)
1817 else if (cause_reg & MLXBF_I2C_CAUSE_WRITE_SUCCESS)
1820 /* Clear cause bits. */
1821 writel(~0x0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR);
1826 static bool mlxbf_smbus_slave_wait_for_idle(struct mlxbf_i2c_priv *priv,
1829 u32 mask = MLXBF_I2C_CAUSE_S_GW_BUSY_FALL;
1830 u32 addr = MLXBF_I2C_CAUSE_ARBITER;
1832 if (mlxbf_smbus_poll(priv->slv_cause->io, addr, mask, false, timeout))
1838 /* Send byte to 'external' smbus master. */
1839 static int mlxbf_smbus_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
1841 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 };
1842 u8 write_size, pec_en, addr, byte, value, byte_cnt, desc_size;
1843 struct i2c_client *slave = priv->slave;
1844 u32 control32, data32;
1852 desc_size = MLXBF_I2C_SLAVE_DATA_DESC_SIZE;
1855 * Read bytes received from the external master. These bytes should
1856 * be located in the first data descriptor register of the slave GW.
1857 * These bytes are the slave address byte and the internal register
1858 * address, if supplied.
1860 if (recv_bytes > 0) {
1861 data32 = ioread32be(priv->smbus->io +
1862 MLXBF_I2C_SLAVE_DATA_DESC_ADDR);
1864 /* Parse the received bytes. */
1865 switch (recv_bytes) {
1867 byte = (data32 >> 8) & GENMASK(7, 0);
1870 addr = (data32 & GENMASK(7, 0)) >> 1;
1873 /* Check whether it's our slave address. */
1874 if (slave->addr != addr)
1879 * I2C read transactions may start by a WRITE followed by a READ.
1880 * Indeed, most slave devices would expect the internal address
1881 * following the slave address byte. So, write that byte first,
1882 * and then, send the requested data bytes to the master.
1884 if (recv_bytes > 1) {
1885 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1887 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED,
1889 i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
1896 * Now, send data to the master; currently, the driver supports
1897 * READ_BYTE, READ_WORD and BLOCK READ protocols. Note that the
1898 * hardware can send up to 128 bytes per transfer. That is the
1899 * size of its data registers.
1901 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1903 for (byte_cnt = 0; byte_cnt < desc_size; byte_cnt++) {
1904 data_desc[byte_cnt] = value;
1905 i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value);
1908 /* Send a stop condition to the backend. */
1909 i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
1911 /* Handle the actual transfer. */
1913 /* Set the number of bytes to write to master. */
1914 write_size = (byte_cnt - 1) & 0x7f;
1916 /* Write data to Slave GW data descriptor. */
1917 mlxbf_i2c_smbus_write_data(priv, data_desc, byte_cnt,
1918 MLXBF_I2C_SLAVE_DATA_DESC_ADDR);
1920 pec_en = 0; /* Disable PEC since it is not supported. */
1922 /* Prepare control word. */
1923 control32 = MLXBF_I2C_SLAVE_ENABLE;
1924 control32 |= rol32(write_size, MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT);
1925 control32 |= rol32(pec_en, MLXBF_I2C_SLAVE_SEND_PEC_SHIFT);
1927 writel(control32, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_GW);
1930 * Wait until the transfer is completed; the driver will wait
1931 * until the GW is idle, a cause will rise on fall of GW busy.
1933 mlxbf_smbus_slave_wait_for_idle(priv, MLXBF_I2C_SMBUS_TIMEOUT);
1935 /* Release the Slave GW. */
1936 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
1937 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC);
1938 writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY);
1943 /* Receive bytes from 'external' smbus master. */
1944 static int mlxbf_smbus_irq_recv(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
1946 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 };
1947 struct i2c_client *slave = priv->slave;
1948 u8 value, byte, addr;
1954 /* Read data from Slave GW data descriptor. */
1955 mlxbf_i2c_smbus_read_data(priv, data_desc, recv_bytes,
1956 MLXBF_I2C_SLAVE_DATA_DESC_ADDR);
1958 /* Check whether its our slave address. */
1959 addr = data_desc[0] >> 1;
1960 if (slave->addr != addr)
1964 * Notify the slave backend; another I2C master wants to write data
1965 * to us. This event is sent once the slave address and the write bit
1968 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1970 /* Send the received data to the slave backend. */
1971 for (byte = 1; byte < recv_bytes; byte++) {
1972 value = data_desc[byte];
1973 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED,
1979 /* Send a stop condition to the backend. */
1980 i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
1982 /* Release the Slave GW. */
1983 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
1984 writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC);
1985 writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY);
1990 static irqreturn_t mlxbf_smbus_irq(int irq, void *ptr)
1992 struct mlxbf_i2c_priv *priv = ptr;
1993 bool read, write, irq_is_set;
1998 * Read TYU interrupt register and determine the source of the
1999 * interrupt. Based on the source of the interrupt one of the
2000 * following actions are performed:
2001 * - Receive data and send response to master.
2002 * - Send data and release slave GW.
2004 * Handle read/write transaction only. CRmaster and Iarp requests
2005 * are ignored for now.
2007 irq_is_set = mlxbf_i2c_has_coalesce(priv, &read, &write);
2008 if (!irq_is_set || (!read && !write)) {
2009 /* Nothing to do here, interrupt was not from this device. */
2014 * The MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES includes the number of
2015 * bytes from/to master. These are defined by 8-bits each. If the lower
2016 * 8 bits are set, then the master expect to read N bytes from the
2017 * slave, if the higher 8 bits are sent then the slave expect N bytes
2020 rw_bytes_reg = readl(priv->smbus->io +
2021 MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
2022 recv_bytes = (rw_bytes_reg >> 8) & GENMASK(7, 0);
2025 * For now, the slave supports 128 bytes transfer. Discard remaining
2026 * data bytes if the master wrote more than
2027 * MLXBF_I2C_SLAVE_DATA_DESC_SIZE, i.e, the actual size of the slave
2030 * Note that we will never expect to transfer more than 128 bytes; as
2031 * specified in the SMBus standard, block transactions cannot exceed
2034 recv_bytes = recv_bytes > MLXBF_I2C_SLAVE_DATA_DESC_SIZE ?
2035 MLXBF_I2C_SLAVE_DATA_DESC_SIZE : recv_bytes;
2038 mlxbf_smbus_irq_send(priv, recv_bytes);
2040 mlxbf_smbus_irq_recv(priv, recv_bytes);
2045 /* Return negative errno on error. */
2046 static s32 mlxbf_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr,
2047 unsigned short flags, char read_write,
2048 u8 command, int size,
2049 union i2c_smbus_data *data)
2051 struct mlxbf_i2c_smbus_request request = { 0 };
2052 struct mlxbf_i2c_priv *priv;
2056 request.slave = addr;
2058 read = (read_write == I2C_SMBUS_READ);
2059 pec = flags & I2C_FUNC_SMBUS_PEC;
2062 case I2C_SMBUS_QUICK:
2063 mlxbf_i2c_smbus_quick_command(&request, read);
2064 dev_dbg(&adap->dev, "smbus quick, slave 0x%02x\n", addr);
2067 case I2C_SMBUS_BYTE:
2068 mlxbf_i2c_smbus_byte_func(&request,
2069 read ? &data->byte : &command, read,
2071 dev_dbg(&adap->dev, "smbus %s byte, slave 0x%02x.\n",
2072 read ? "read" : "write", addr);
2075 case I2C_SMBUS_BYTE_DATA:
2076 mlxbf_i2c_smbus_data_byte_func(&request, &command, &data->byte,
2078 dev_dbg(&adap->dev, "smbus %s byte data at 0x%02x, slave 0x%02x.\n",
2079 read ? "read" : "write", command, addr);
2082 case I2C_SMBUS_WORD_DATA:
2083 mlxbf_i2c_smbus_data_word_func(&request, &command,
2084 (u8 *)&data->word, read, pec);
2085 dev_dbg(&adap->dev, "smbus %s word data at 0x%02x, slave 0x%02x.\n",
2086 read ? "read" : "write", command, addr);
2089 case I2C_SMBUS_I2C_BLOCK_DATA:
2090 byte_cnt = data->block[0];
2091 mlxbf_i2c_smbus_i2c_block_func(&request, &command, data->block,
2092 &byte_cnt, read, pec);
2093 dev_dbg(&adap->dev, "i2c %s block data, %d bytes at 0x%02x, slave 0x%02x.\n",
2094 read ? "read" : "write", byte_cnt, command, addr);
2097 case I2C_SMBUS_BLOCK_DATA:
2098 byte_cnt = read ? I2C_SMBUS_BLOCK_MAX : data->block[0];
2099 mlxbf_i2c_smbus_block_func(&request, &command, data->block,
2100 &byte_cnt, read, pec);
2101 dev_dbg(&adap->dev, "smbus %s block data, %d bytes at 0x%02x, slave 0x%02x.\n",
2102 read ? "read" : "write", byte_cnt, command, addr);
2105 case I2C_FUNC_SMBUS_PROC_CALL:
2106 mlxbf_i2c_smbus_process_call_func(&request, &command,
2107 (u8 *)&data->word, pec);
2108 dev_dbg(&adap->dev, "process call, wr/rd at 0x%02x, slave 0x%02x.\n",
2112 case I2C_FUNC_SMBUS_BLOCK_PROC_CALL:
2113 byte_cnt = data->block[0];
2114 mlxbf_i2c_smbus_blk_process_call_func(&request, &command,
2115 data->block, &byte_cnt,
2117 dev_dbg(&adap->dev, "block process call, wr/rd %d bytes, slave 0x%02x.\n",
2122 dev_dbg(&adap->dev, "Unsupported I2C/SMBus command %d\n",
2127 priv = i2c_get_adapdata(adap);
2129 return mlxbf_i2c_smbus_start_transaction(priv, &request);
2132 static int mlxbf_i2c_reg_slave(struct i2c_client *slave)
2134 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
2141 * Do not support ten bit chip address and do not use Packet Error
2144 if (slave->flags & (I2C_CLIENT_TEN | I2C_CLIENT_PEC))
2145 return -EAFNOSUPPORT;
2147 ret = mlxbf_slave_enable(priv, slave->addr);
2151 priv->slave = slave;
2156 static int mlxbf_i2c_unreg_slave(struct i2c_client *slave)
2158 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
2161 WARN_ON(!priv->slave);
2163 /* Unregister slave, i.e. disable the slave address in hardware. */
2164 ret = mlxbf_slave_disable(priv);
2173 static u32 mlxbf_i2c_functionality(struct i2c_adapter *adap)
2175 return MLXBF_I2C_FUNC_ALL;
2178 static struct mlxbf_i2c_chip_info mlxbf_i2c_chip[] = {
2179 [MLXBF_I2C_CHIP_TYPE_1] = {
2180 .type = MLXBF_I2C_CHIP_TYPE_1,
2182 [0] = &mlxbf_i2c_coalesce_res[MLXBF_I2C_CHIP_TYPE_1],
2183 [1] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_1],
2184 [2] = &mlxbf_i2c_gpio_res[MLXBF_I2C_CHIP_TYPE_1]
2186 .calculate_freq = mlxbf_calculate_freq_from_tyu
2188 [MLXBF_I2C_CHIP_TYPE_2] = {
2189 .type = MLXBF_I2C_CHIP_TYPE_2,
2191 [0] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_2]
2193 .calculate_freq = mlxbf_calculate_freq_from_yu
2197 static const struct i2c_algorithm mlxbf_i2c_algo = {
2198 .smbus_xfer = mlxbf_i2c_smbus_xfer,
2199 .functionality = mlxbf_i2c_functionality,
2200 .reg_slave = mlxbf_i2c_reg_slave,
2201 .unreg_slave = mlxbf_i2c_unreg_slave,
2204 static struct i2c_adapter_quirks mlxbf_i2c_quirks = {
2205 .max_read_len = MLXBF_I2C_MASTER_DATA_R_LENGTH,
2206 .max_write_len = MLXBF_I2C_MASTER_DATA_W_LENGTH,
2209 static const struct of_device_id mlxbf_i2c_dt_ids[] = {
2211 .compatible = "mellanox,i2c-mlxbf1",
2212 .data = &mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1]
2215 .compatible = "mellanox,i2c-mlxbf2",
2216 .data = &mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2]
2221 MODULE_DEVICE_TABLE(of, mlxbf_i2c_dt_ids);
2224 static const struct acpi_device_id mlxbf_i2c_acpi_ids[] = {
2225 { "MLNXBF03", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1] },
2226 { "MLNXBF23", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2] },
2230 MODULE_DEVICE_TABLE(acpi, mlxbf_i2c_acpi_ids);
2232 static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv)
2234 const struct acpi_device_id *aid;
2235 struct acpi_device *adev;
2236 unsigned long bus_id = 0;
2243 adev = ACPI_COMPANION(dev);
2247 aid = acpi_match_device(mlxbf_i2c_acpi_ids, dev);
2251 priv->chip = (struct mlxbf_i2c_chip_info *)aid->driver_data;
2253 uid = acpi_device_uid(adev);
2254 if (!uid || !(*uid)) {
2255 dev_err(dev, "Cannot retrieve UID\n");
2259 ret = kstrtoul(uid, 0, &bus_id);
2266 static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv)
2270 #endif /* CONFIG_ACPI */
2272 static int mlxbf_i2c_of_probe(struct device *dev, struct mlxbf_i2c_priv *priv)
2274 const struct of_device_id *oid;
2277 if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
2278 oid = of_match_node(mlxbf_i2c_dt_ids, dev->of_node);
2282 priv->chip = oid->data;
2284 bus_id = of_alias_get_id(dev->of_node, "i2c");
2290 dev_err(dev, "Cannot get bus id");
2297 static int mlxbf_i2c_probe(struct platform_device *pdev)
2299 struct device *dev = &pdev->dev;
2300 struct mlxbf_i2c_priv *priv;
2301 struct i2c_adapter *adap;
2304 priv = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_priv), GFP_KERNEL);
2308 ret = mlxbf_i2c_acpi_probe(dev, priv);
2309 if (ret < 0 && ret != -ENOENT && ret != -ENXIO)
2310 ret = mlxbf_i2c_of_probe(dev, priv);
2315 ret = mlxbf_i2c_init_resource(pdev, &priv->smbus,
2316 MLXBF_I2C_SMBUS_RES);
2318 dev_err(dev, "Cannot fetch smbus resource info");
2322 ret = mlxbf_i2c_init_resource(pdev, &priv->mst_cause,
2323 MLXBF_I2C_MST_CAUSE_RES);
2325 dev_err(dev, "Cannot fetch cause master resource info");
2329 ret = mlxbf_i2c_init_resource(pdev, &priv->slv_cause,
2330 MLXBF_I2C_SLV_CAUSE_RES);
2332 dev_err(dev, "Cannot fetch cause slave resource info");
2337 adap->owner = THIS_MODULE;
2338 adap->class = I2C_CLASS_HWMON;
2339 adap->algo = &mlxbf_i2c_algo;
2340 adap->quirks = &mlxbf_i2c_quirks;
2341 adap->dev.parent = dev;
2342 adap->dev.of_node = dev->of_node;
2343 adap->nr = priv->bus;
2345 snprintf(adap->name, sizeof(adap->name), "i2c%d", adap->nr);
2346 i2c_set_adapdata(adap, priv);
2348 /* Read Core PLL frequency. */
2349 ret = mlxbf_i2c_calculate_corepll_freq(pdev, priv);
2351 dev_err(dev, "cannot get core clock frequency\n");
2352 /* Set to default value. */
2353 priv->frequency = MLXBF_I2C_COREPLL_FREQ;
2357 * Initialize master.
2358 * Note that a physical bus might be shared among Linux and firmware
2359 * (e.g., ATF). Thus, the bus should be initialized and ready and
2360 * bus initialization would be unnecessary. This requires additional
2361 * knowledge about physical busses. But, since an extra initialization
2362 * does not really hurt, then keep the code as is.
2364 ret = mlxbf_i2c_init_master(pdev, priv);
2366 dev_err(dev, "failed to initialize smbus master %d",
2371 mlxbf_i2c_init_timings(pdev, priv);
2373 mlxbf_i2c_init_slave(pdev, priv);
2375 irq = platform_get_irq(pdev, 0);
2378 ret = devm_request_irq(dev, irq, mlxbf_smbus_irq,
2379 IRQF_ONESHOT | IRQF_SHARED | IRQF_PROBE_SHARED,
2380 dev_name(dev), priv);
2382 dev_err(dev, "Cannot get irq %d\n", irq);
2388 platform_set_drvdata(pdev, priv);
2390 ret = i2c_add_numbered_adapter(adap);
2394 mutex_lock(&mlxbf_i2c_bus_lock);
2395 mlxbf_i2c_bus_count++;
2396 mutex_unlock(&mlxbf_i2c_bus_lock);
2401 static int mlxbf_i2c_remove(struct platform_device *pdev)
2403 struct mlxbf_i2c_priv *priv = platform_get_drvdata(pdev);
2404 struct device *dev = &pdev->dev;
2405 struct resource *params;
2407 params = priv->smbus->params;
2408 devm_release_mem_region(dev, params->start, resource_size(params));
2410 params = priv->mst_cause->params;
2411 devm_release_mem_region(dev, params->start, resource_size(params));
2413 params = priv->slv_cause->params;
2414 devm_release_mem_region(dev, params->start, resource_size(params));
2417 * Release shared resources. This should be done when releasing
2418 * the I2C controller.
2420 mutex_lock(&mlxbf_i2c_bus_lock);
2421 if (--mlxbf_i2c_bus_count == 0) {
2422 mlxbf_i2c_release_coalesce(pdev, priv);
2423 mlxbf_i2c_release_corepll(pdev, priv);
2424 mlxbf_i2c_release_gpio(pdev, priv);
2426 mutex_unlock(&mlxbf_i2c_bus_lock);
2428 devm_free_irq(dev, priv->irq, priv);
2430 i2c_del_adapter(&priv->adap);
2435 static struct platform_driver mlxbf_i2c_driver = {
2436 .probe = mlxbf_i2c_probe,
2437 .remove = mlxbf_i2c_remove,
2439 .name = "i2c-mlxbf",
2440 .of_match_table = mlxbf_i2c_dt_ids,
2442 .acpi_match_table = ACPI_PTR(mlxbf_i2c_acpi_ids),
2443 #endif /* CONFIG_ACPI */
2447 static int __init mlxbf_i2c_init(void)
2449 mutex_init(&mlxbf_i2c_coalesce_lock);
2450 mutex_init(&mlxbf_i2c_corepll_lock);
2451 mutex_init(&mlxbf_i2c_gpio_lock);
2453 mutex_init(&mlxbf_i2c_bus_lock);
2455 return platform_driver_register(&mlxbf_i2c_driver);
2457 module_init(mlxbf_i2c_init);
2459 static void __exit mlxbf_i2c_exit(void)
2461 platform_driver_unregister(&mlxbf_i2c_driver);
2463 mutex_destroy(&mlxbf_i2c_bus_lock);
2465 mutex_destroy(&mlxbf_i2c_gpio_lock);
2466 mutex_destroy(&mlxbf_i2c_corepll_lock);
2467 mutex_destroy(&mlxbf_i2c_coalesce_lock);
2469 module_exit(mlxbf_i2c_exit);
2471 MODULE_DESCRIPTION("Mellanox BlueField I2C bus driver");
2472 MODULE_AUTHOR("Khalil Blaiech <kblaiech@nvidia.com>");
2473 MODULE_LICENSE("GPL v2");