1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2021 Broadcom Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 #include <linux/kernel.h>
10 #include <linux/errno.h>
11 #include <linux/pci.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/net_tstamp.h>
15 #include <linux/timekeeping.h>
16 #include <linux/ptp_classify.h>
19 #include "bnxt_hwrm.h"
22 static int bnxt_ptp_cfg_settime(struct bnxt *bp, u64 time)
24 struct hwrm_func_ptp_cfg_input *req;
27 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG);
31 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME);
32 req->ptp_set_time = cpu_to_le64(time);
33 return hwrm_req_send(bp, req);
36 int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off)
38 unsigned int ptp_class;
39 struct ptp_header *hdr;
41 ptp_class = ptp_classify_raw(skb);
43 switch (ptp_class & PTP_CLASS_VMASK) {
46 hdr = ptp_parse_header(skb, ptp_class);
50 *hdr_off = (u8 *)hdr - skb->data;
51 *seq_id = ntohs(hdr->sequence_id);
58 static int bnxt_ptp_settime(struct ptp_clock_info *ptp_info,
59 const struct timespec64 *ts)
61 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
63 u64 ns = timespec64_to_ns(ts);
65 if (ptp->bp->fw_cap & BNXT_FW_CAP_PTP_RTC)
66 return bnxt_ptp_cfg_settime(ptp->bp, ns);
68 spin_lock_bh(&ptp->ptp_lock);
69 timecounter_init(&ptp->tc, &ptp->cc, ns);
70 spin_unlock_bh(&ptp->ptp_lock);
74 /* Caller holds ptp_lock */
75 static int bnxt_refclk_read(struct bnxt *bp, struct ptp_system_timestamp *sts,
78 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
79 u32 high_before, high_now, low;
81 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
84 high_before = readl(bp->bar0 + ptp->refclk_mapped_regs[1]);
85 ptp_read_system_prets(sts);
86 low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]);
87 ptp_read_system_postts(sts);
88 high_now = readl(bp->bar0 + ptp->refclk_mapped_regs[1]);
89 if (high_now != high_before) {
90 ptp_read_system_prets(sts);
91 low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]);
92 ptp_read_system_postts(sts);
94 *ns = ((u64)high_now << 32) | low;
99 static void bnxt_ptp_get_current_time(struct bnxt *bp)
101 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
105 spin_lock_bh(&ptp->ptp_lock);
106 WRITE_ONCE(ptp->old_time, ptp->current_time);
107 bnxt_refclk_read(bp, NULL, &ptp->current_time);
108 spin_unlock_bh(&ptp->ptp_lock);
111 static int bnxt_hwrm_port_ts_query(struct bnxt *bp, u32 flags, u64 *ts)
113 struct hwrm_port_ts_query_output *resp;
114 struct hwrm_port_ts_query_input *req;
117 rc = hwrm_req_init(bp, req, HWRM_PORT_TS_QUERY);
121 req->flags = cpu_to_le32(flags);
122 if ((flags & PORT_TS_QUERY_REQ_FLAGS_PATH) ==
123 PORT_TS_QUERY_REQ_FLAGS_PATH_TX) {
124 req->enables = cpu_to_le16(BNXT_PTP_QTS_TX_ENABLES);
125 req->ptp_seq_id = cpu_to_le32(bp->ptp_cfg->tx_seqid);
126 req->ptp_hdr_offset = cpu_to_le16(bp->ptp_cfg->tx_hdr_off);
127 req->ts_req_timeout = cpu_to_le16(BNXT_PTP_QTS_TIMEOUT);
129 resp = hwrm_req_hold(bp, req);
131 rc = hwrm_req_send(bp, req);
133 *ts = le64_to_cpu(resp->ptp_msg_ts);
134 hwrm_req_drop(bp, req);
138 static int bnxt_ptp_gettimex(struct ptp_clock_info *ptp_info,
139 struct timespec64 *ts,
140 struct ptp_system_timestamp *sts)
142 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
147 spin_lock_bh(&ptp->ptp_lock);
148 rc = bnxt_refclk_read(ptp->bp, sts, &cycles);
150 spin_unlock_bh(&ptp->ptp_lock);
153 ns = timecounter_cyc2time(&ptp->tc, cycles);
154 spin_unlock_bh(&ptp->ptp_lock);
155 *ts = ns_to_timespec64(ns);
160 /* Caller holds ptp_lock */
161 void bnxt_ptp_update_current_time(struct bnxt *bp)
163 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
165 bnxt_refclk_read(ptp->bp, NULL, &ptp->current_time);
166 WRITE_ONCE(ptp->old_time, ptp->current_time);
169 static int bnxt_ptp_adjphc(struct bnxt_ptp_cfg *ptp, s64 delta)
171 struct hwrm_port_mac_cfg_input *req;
174 rc = hwrm_req_init(ptp->bp, req, HWRM_PORT_MAC_CFG);
178 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE);
179 req->ptp_adj_phase = cpu_to_le64(delta);
181 rc = hwrm_req_send(ptp->bp, req);
183 netdev_err(ptp->bp->dev, "ptp adjphc failed. rc = %x\n", rc);
185 spin_lock_bh(&ptp->ptp_lock);
186 bnxt_ptp_update_current_time(ptp->bp);
187 spin_unlock_bh(&ptp->ptp_lock);
193 static int bnxt_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta)
195 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
198 if (ptp->bp->fw_cap & BNXT_FW_CAP_PTP_RTC)
199 return bnxt_ptp_adjphc(ptp, delta);
201 spin_lock_bh(&ptp->ptp_lock);
202 timecounter_adjtime(&ptp->tc, delta);
203 spin_unlock_bh(&ptp->ptp_lock);
207 static int bnxt_ptp_adjfreq(struct ptp_clock_info *ptp_info, s32 ppb)
209 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
211 struct hwrm_port_mac_cfg_input *req;
212 struct bnxt *bp = ptp->bp;
215 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);
219 req->ptp_freq_adj_ppb = cpu_to_le32(ppb);
220 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB);
221 rc = hwrm_req_send(ptp->bp, req);
223 netdev_err(ptp->bp->dev,
224 "ptp adjfreq failed. rc = %d\n", rc);
228 void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2)
230 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
231 struct ptp_clock_event event;
234 pps_ts = EVENT_PPS_TS(data2, data1);
235 spin_lock_bh(&ptp->ptp_lock);
236 ns = timecounter_cyc2time(&ptp->tc, pps_ts);
237 spin_unlock_bh(&ptp->ptp_lock);
239 switch (EVENT_DATA2_PPS_EVENT_TYPE(data2)) {
240 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL:
241 event.pps_times.ts_real = ns_to_timespec64(ns);
242 event.type = PTP_CLOCK_PPSUSR;
243 event.index = EVENT_DATA2_PPS_PIN_NUM(data2);
245 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL:
246 event.timestamp = ns;
247 event.type = PTP_CLOCK_EXTTS;
248 event.index = EVENT_DATA2_PPS_PIN_NUM(data2);
252 ptp_clock_event(bp->ptp_cfg->ptp_clock, &event);
255 static int bnxt_ptp_cfg_pin(struct bnxt *bp, u8 pin, u8 usage)
257 struct hwrm_func_ptp_pin_cfg_input *req;
258 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
259 u8 state = usage != BNXT_PPS_PIN_NONE;
260 u8 *pin_state, *pin_usg;
264 if (!TSIO_PIN_VALID(pin)) {
265 netdev_err(ptp->bp->dev, "1PPS: Invalid pin. Check pin-function configuration\n");
269 rc = hwrm_req_init(ptp->bp, req, HWRM_FUNC_PTP_PIN_CFG);
273 enables = (FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE |
274 FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE) << (pin * 2);
275 req->enables = cpu_to_le32(enables);
277 pin_state = &req->pin0_state;
278 pin_usg = &req->pin0_usage;
280 *(pin_state + (pin * 2)) = state;
281 *(pin_usg + (pin * 2)) = usage;
283 rc = hwrm_req_send(ptp->bp, req);
287 ptp->pps_info.pins[pin].usage = usage;
288 ptp->pps_info.pins[pin].state = state;
293 static int bnxt_ptp_cfg_event(struct bnxt *bp, u8 event)
295 struct hwrm_func_ptp_cfg_input *req;
298 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG);
302 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT);
303 req->ptp_pps_event = event;
304 return hwrm_req_send(bp, req);
307 void bnxt_ptp_cfg_tstamp_filters(struct bnxt *bp)
309 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
310 struct hwrm_port_mac_cfg_input *req;
312 if (!ptp || !ptp->tstamp_filters)
315 if (hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG))
318 if (!(bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) && (ptp->tstamp_filters &
319 (PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE |
320 PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE))) {
321 ptp->tstamp_filters &= ~(PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE |
322 PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE);
323 netdev_warn(bp->dev, "Unsupported FW for all RX pkts timestamp filter\n");
326 req->flags = cpu_to_le32(ptp->tstamp_filters);
327 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
328 req->rx_ts_capture_ptp_msg_type = cpu_to_le16(ptp->rxctl);
330 if (!hwrm_req_send(bp, req)) {
331 bp->ptp_all_rx_tstamp = !!(ptp->tstamp_filters &
332 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE);
335 ptp->tstamp_filters = 0;
337 bp->ptp_all_rx_tstamp = 0;
338 netdev_warn(bp->dev, "Failed to configure HW packet timestamp filters\n");
341 void bnxt_ptp_reapply_pps(struct bnxt *bp)
343 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
344 struct bnxt_pps *pps;
348 if (!ptp || !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) ||
349 !(ptp->ptp_info.pin_config))
351 pps = &ptp->pps_info;
352 for (pin = 0; pin < BNXT_MAX_TSIO_PINS; pin++) {
353 if (pps->pins[pin].state) {
354 rc = bnxt_ptp_cfg_pin(bp, pin, pps->pins[pin].usage);
355 if (!rc && pps->pins[pin].event)
356 rc = bnxt_ptp_cfg_event(bp,
357 pps->pins[pin].event);
359 netdev_err(bp->dev, "1PPS: Failed to configure pin%d\n",
365 static int bnxt_get_target_cycles(struct bnxt_ptp_cfg *ptp, u64 target_ns,
369 u64 nsec_now, nsec_delta;
372 spin_lock_bh(&ptp->ptp_lock);
373 rc = bnxt_refclk_read(ptp->bp, NULL, &cycles_now);
375 spin_unlock_bh(&ptp->ptp_lock);
378 nsec_now = timecounter_cyc2time(&ptp->tc, cycles_now);
379 spin_unlock_bh(&ptp->ptp_lock);
381 nsec_delta = target_ns - nsec_now;
382 *cycles_delta = div64_u64(nsec_delta << ptp->cc.shift, ptp->cc.mult);
386 static int bnxt_ptp_perout_cfg(struct bnxt_ptp_cfg *ptp,
387 struct ptp_clock_request *rq)
389 struct hwrm_func_ptp_cfg_input *req;
390 struct bnxt *bp = ptp->bp;
391 struct timespec64 ts;
392 u64 target_ns, delta;
396 ts.tv_sec = rq->perout.start.sec;
397 ts.tv_nsec = rq->perout.start.nsec;
398 target_ns = timespec64_to_ns(&ts);
400 rc = bnxt_get_target_cycles(ptp, target_ns, &delta);
404 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG);
408 enables = FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD |
409 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP |
410 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE;
411 req->enables = cpu_to_le16(enables);
412 req->ptp_pps_event = 0;
413 req->ptp_freq_adj_dll_source = 0;
414 req->ptp_freq_adj_dll_phase = 0;
415 req->ptp_freq_adj_ext_period = cpu_to_le32(NSEC_PER_SEC);
416 req->ptp_freq_adj_ext_up = 0;
417 req->ptp_freq_adj_ext_phase_lower = cpu_to_le32(delta);
419 return hwrm_req_send(bp, req);
422 static int bnxt_ptp_enable(struct ptp_clock_info *ptp_info,
423 struct ptp_clock_request *rq, int on)
425 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
427 struct bnxt *bp = ptp->bp;
432 case PTP_CLK_REQ_EXTTS:
433 /* Configure an External PPS IN */
434 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_EXTTS,
436 if (!TSIO_PIN_VALID(pin_id))
440 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_IN);
443 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_EXTERNAL);
445 ptp->pps_info.pins[pin_id].event = BNXT_PPS_EVENT_EXTERNAL;
447 case PTP_CLK_REQ_PEROUT:
448 /* Configure a Periodic PPS OUT */
449 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_PEROUT,
451 if (!TSIO_PIN_VALID(pin_id))
456 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_OUT);
458 rc = bnxt_ptp_perout_cfg(ptp, rq);
461 case PTP_CLK_REQ_PPS:
462 /* Configure PHC PPS IN */
463 rc = bnxt_ptp_cfg_pin(bp, 0, BNXT_PPS_PIN_PPS_IN);
466 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_INTERNAL);
468 ptp->pps_info.pins[0].event = BNXT_PPS_EVENT_INTERNAL;
471 netdev_err(ptp->bp->dev, "Unrecognized PIN function\n");
475 return bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_NONE);
478 static int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
480 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
484 switch (ptp->rx_filter) {
485 case HWTSTAMP_FILTER_ALL:
486 flags = PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE;
488 case HWTSTAMP_FILTER_NONE:
489 flags = PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
490 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS)
491 flags |= PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE;
493 case HWTSTAMP_FILTER_PTP_V2_EVENT:
494 case HWTSTAMP_FILTER_PTP_V2_SYNC:
495 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
496 flags = PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
500 if (ptp->tx_tstamp_en)
501 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
503 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
505 ptp->tstamp_filters = flags;
507 if (netif_running(bp->dev)) {
508 rc = bnxt_close_nic(bp, false, false);
510 rc = bnxt_open_nic(bp, false, false);
511 if (!rc && !ptp->tstamp_filters)
518 int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
520 struct bnxt *bp = netdev_priv(dev);
521 struct hwtstamp_config stmpconf;
522 struct bnxt_ptp_cfg *ptp;
524 int old_rx_filter, rc;
531 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
534 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
535 stmpconf.tx_type != HWTSTAMP_TX_OFF)
538 old_rx_filter = ptp->rx_filter;
539 old_rxctl = ptp->rxctl;
540 old_tx_tstamp_en = ptp->tx_tstamp_en;
541 switch (stmpconf.rx_filter) {
542 case HWTSTAMP_FILTER_NONE:
544 ptp->rx_filter = HWTSTAMP_FILTER_NONE;
546 case HWTSTAMP_FILTER_ALL:
547 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) {
548 ptp->rx_filter = HWTSTAMP_FILTER_ALL;
552 case HWTSTAMP_FILTER_PTP_V2_EVENT:
553 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
554 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
555 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
556 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
558 case HWTSTAMP_FILTER_PTP_V2_SYNC:
559 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
560 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
561 ptp->rxctl = BNXT_PTP_MSG_SYNC;
562 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
564 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
565 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
566 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
567 ptp->rxctl = BNXT_PTP_MSG_DELAY_REQ;
568 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
574 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
575 ptp->tx_tstamp_en = 1;
577 ptp->tx_tstamp_en = 0;
579 rc = bnxt_hwrm_ptp_cfg(bp);
583 stmpconf.rx_filter = ptp->rx_filter;
584 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
588 ptp->rx_filter = old_rx_filter;
589 ptp->rxctl = old_rxctl;
590 ptp->tx_tstamp_en = old_tx_tstamp_en;
594 int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
596 struct bnxt *bp = netdev_priv(dev);
597 struct hwtstamp_config stmpconf;
598 struct bnxt_ptp_cfg *ptp;
605 stmpconf.tx_type = ptp->tx_tstamp_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
607 stmpconf.rx_filter = ptp->rx_filter;
608 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
612 static int bnxt_map_regs(struct bnxt *bp, u32 *reg_arr, int count, int reg_win)
614 u32 reg_base = *reg_arr & BNXT_GRC_BASE_MASK;
618 for (i = 0; i < count; i++) {
619 if ((reg_arr[i] & BNXT_GRC_BASE_MASK) != reg_base)
622 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
623 writel(reg_base, bp->bar0 + win_off);
627 static int bnxt_map_ptp_regs(struct bnxt *bp)
629 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
633 reg_arr = ptp->refclk_regs;
634 if (bp->flags & BNXT_FLAG_CHIP_P5) {
635 rc = bnxt_map_regs(bp, reg_arr, 2, BNXT_PTP_GRC_WIN);
638 for (i = 0; i < 2; i++)
639 ptp->refclk_mapped_regs[i] = BNXT_PTP_GRC_WIN_BASE +
640 (ptp->refclk_regs[i] & BNXT_GRC_OFFSET_MASK);
646 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
648 writel(0, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT +
649 (BNXT_PTP_GRC_WIN - 1) * 4);
652 static u64 bnxt_cc_read(const struct cyclecounter *cc)
654 struct bnxt_ptp_cfg *ptp = container_of(cc, struct bnxt_ptp_cfg, cc);
657 bnxt_refclk_read(ptp->bp, NULL, &ns);
661 static void bnxt_stamp_tx_skb(struct bnxt *bp, struct sk_buff *skb)
663 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
664 struct skb_shared_hwtstamps timestamp;
668 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_PATH_TX, &ts);
670 memset(×tamp, 0, sizeof(timestamp));
671 spin_lock_bh(&ptp->ptp_lock);
672 ns = timecounter_cyc2time(&ptp->tc, ts);
673 spin_unlock_bh(&ptp->ptp_lock);
674 timestamp.hwtstamp = ns_to_ktime(ns);
675 skb_tstamp_tx(ptp->tx_skb, ×tamp);
677 netdev_err(bp->dev, "TS query for TX timer failed rc = %x\n",
681 dev_kfree_skb_any(ptp->tx_skb);
683 atomic_inc(&ptp->tx_avail);
686 static long bnxt_ptp_ts_aux_work(struct ptp_clock_info *ptp_info)
688 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
690 unsigned long now = jiffies;
691 struct bnxt *bp = ptp->bp;
694 bnxt_stamp_tx_skb(bp, ptp->tx_skb);
696 if (!time_after_eq(now, ptp->next_period))
697 return ptp->next_period - now;
699 bnxt_ptp_get_current_time(bp);
700 ptp->next_period = now + HZ;
701 if (time_after_eq(now, ptp->next_overflow_check)) {
702 spin_lock_bh(&ptp->ptp_lock);
703 timecounter_read(&ptp->tc);
704 spin_unlock_bh(&ptp->ptp_lock);
705 ptp->next_overflow_check = now + BNXT_PHC_OVERFLOW_PERIOD;
710 int bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb)
712 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
715 netdev_err(bp->dev, "deferring skb:one SKB is still outstanding\n");
719 ptp_schedule_worker(ptp->ptp_clock, 0);
723 int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts)
725 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
731 BNXT_READ_TIME64(ptp, time, ptp->old_time);
732 *ts = (time & BNXT_HI_TIMER_MASK) | pkt_ts;
733 if (pkt_ts < (time & BNXT_LO_TIMER_MASK))
734 *ts += BNXT_LO_TIMER_MASK + 1;
739 static const struct ptp_clock_info bnxt_ptp_caps = {
740 .owner = THIS_MODULE,
741 .name = "bnxt clock",
742 .max_adj = BNXT_MAX_PHC_DRIFT,
748 .adjfreq = bnxt_ptp_adjfreq,
749 .adjtime = bnxt_ptp_adjtime,
750 .do_aux_work = bnxt_ptp_ts_aux_work,
751 .gettimex64 = bnxt_ptp_gettimex,
752 .settime64 = bnxt_ptp_settime,
753 .enable = bnxt_ptp_enable,
756 static int bnxt_ptp_verify(struct ptp_clock_info *ptp_info, unsigned int pin,
757 enum ptp_pin_function func, unsigned int chan)
759 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
761 /* Allow only PPS pin function configuration */
762 if (ptp->pps_info.pins[pin].usage <= BNXT_PPS_PIN_PPS_OUT &&
763 func != PTP_PF_PHYSYNC)
769 static int bnxt_ptp_pps_init(struct bnxt *bp)
771 struct hwrm_func_ptp_pin_qcfg_output *resp;
772 struct hwrm_func_ptp_pin_qcfg_input *req;
773 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
774 struct ptp_clock_info *ptp_info;
775 struct bnxt_pps *pps_info;
779 /* Query current/default PIN CFG */
780 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_PIN_QCFG);
784 resp = hwrm_req_hold(bp, req);
785 rc = hwrm_req_send(bp, req);
786 if (rc || !resp->num_pins) {
787 hwrm_req_drop(bp, req);
791 ptp_info = &ptp->ptp_info;
792 pps_info = &ptp->pps_info;
793 pps_info->num_pins = resp->num_pins;
794 ptp_info->n_pins = pps_info->num_pins;
795 ptp_info->pin_config = kcalloc(ptp_info->n_pins,
796 sizeof(*ptp_info->pin_config),
798 if (!ptp_info->pin_config) {
799 hwrm_req_drop(bp, req);
803 /* Report the TSIO capability to kernel */
804 pin_usg = &resp->pin0_usage;
805 for (i = 0; i < pps_info->num_pins; i++, pin_usg++) {
806 snprintf(ptp_info->pin_config[i].name,
807 sizeof(ptp_info->pin_config[i].name), "bnxt_pps%d", i);
808 ptp_info->pin_config[i].index = i;
809 ptp_info->pin_config[i].chan = i;
810 if (*pin_usg == BNXT_PPS_PIN_PPS_IN)
811 ptp_info->pin_config[i].func = PTP_PF_EXTTS;
812 else if (*pin_usg == BNXT_PPS_PIN_PPS_OUT)
813 ptp_info->pin_config[i].func = PTP_PF_PEROUT;
815 ptp_info->pin_config[i].func = PTP_PF_NONE;
817 pps_info->pins[i].usage = *pin_usg;
819 hwrm_req_drop(bp, req);
821 /* Only 1 each of ext_ts and per_out pins is available in HW */
822 ptp_info->n_ext_ts = 1;
823 ptp_info->n_per_out = 1;
825 ptp_info->verify = bnxt_ptp_verify;
830 static bool bnxt_pps_config_ok(struct bnxt *bp)
832 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
834 return !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) == !ptp->ptp_info.pin_config;
837 static void bnxt_ptp_timecounter_init(struct bnxt *bp, bool init_tc)
839 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
841 if (!ptp->ptp_clock) {
842 memset(&ptp->cc, 0, sizeof(ptp->cc));
843 ptp->cc.read = bnxt_cc_read;
844 ptp->cc.mask = CYCLECOUNTER_MASK(48);
847 ptp->next_overflow_check = jiffies + BNXT_PHC_OVERFLOW_PERIOD;
850 timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real()));
853 /* Caller holds ptp_lock */
854 void bnxt_ptp_rtc_timecounter_init(struct bnxt_ptp_cfg *ptp, u64 ns)
856 timecounter_init(&ptp->tc, &ptp->cc, ns);
857 /* For RTC, cycle_last must be in sync with the timecounter value. */
858 ptp->tc.cycle_last = ns & ptp->cc.mask;
861 int bnxt_ptp_init_rtc(struct bnxt *bp, bool phc_cfg)
863 struct timespec64 tsp;
867 if (!bp->ptp_cfg || !(bp->fw_cap & BNXT_FW_CAP_PTP_RTC))
871 ktime_get_real_ts64(&tsp);
872 ns = timespec64_to_ns(&tsp);
873 rc = bnxt_ptp_cfg_settime(bp, ns);
877 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME, &ns);
881 spin_lock_bh(&bp->ptp_cfg->ptp_lock);
882 bnxt_ptp_rtc_timecounter_init(bp->ptp_cfg, ns);
883 spin_unlock_bh(&bp->ptp_cfg->ptp_lock);
888 static void bnxt_ptp_free(struct bnxt *bp)
890 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
892 if (ptp->ptp_clock) {
893 ptp_clock_unregister(ptp->ptp_clock);
894 ptp->ptp_clock = NULL;
895 kfree(ptp->ptp_info.pin_config);
896 ptp->ptp_info.pin_config = NULL;
900 int bnxt_ptp_init(struct bnxt *bp, bool phc_cfg)
902 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
908 rc = bnxt_map_ptp_regs(bp);
912 if (ptp->ptp_clock && bnxt_pps_config_ok(bp))
917 atomic_set(&ptp->tx_avail, BNXT_MAX_TX_TS);
918 spin_lock_init(&ptp->ptp_lock);
920 if (bp->fw_cap & BNXT_FW_CAP_PTP_RTC) {
921 bnxt_ptp_timecounter_init(bp, false);
922 rc = bnxt_ptp_init_rtc(bp, phc_cfg);
926 bnxt_ptp_timecounter_init(bp, true);
929 ptp->ptp_info = bnxt_ptp_caps;
930 if ((bp->fw_cap & BNXT_FW_CAP_PTP_PPS)) {
931 if (bnxt_ptp_pps_init(bp))
932 netdev_err(bp->dev, "1pps not initialized, continuing without 1pps support\n");
934 ptp->ptp_clock = ptp_clock_register(&ptp->ptp_info, &bp->pdev->dev);
935 if (IS_ERR(ptp->ptp_clock)) {
936 int err = PTR_ERR(ptp->ptp_clock);
938 ptp->ptp_clock = NULL;
942 if (bp->flags & BNXT_FLAG_CHIP_P5) {
943 spin_lock_bh(&ptp->ptp_lock);
944 bnxt_refclk_read(bp, NULL, &ptp->current_time);
945 WRITE_ONCE(ptp->old_time, ptp->current_time);
946 spin_unlock_bh(&ptp->ptp_lock);
947 ptp_schedule_worker(ptp->ptp_clock, 0);
953 bnxt_unmap_ptp_regs(bp);
957 void bnxt_ptp_clear(struct bnxt *bp)
959 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
965 ptp_clock_unregister(ptp->ptp_clock);
967 ptp->ptp_clock = NULL;
968 kfree(ptp->ptp_info.pin_config);
969 ptp->ptp_info.pin_config = NULL;
972 dev_kfree_skb_any(ptp->tx_skb);
975 bnxt_unmap_ptp_regs(bp);