1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* Copyright 2017-2019 NXP */
4 #include <asm/unaligned.h>
5 #include <linux/mdio.h>
6 #include <linux/module.h>
7 #include <linux/fsl/enetc_mdio.h>
8 #include <linux/of_platform.h>
9 #include <linux/of_mdio.h>
10 #include <linux/of_net.h>
11 #include <linux/pcs-lynx.h>
12 #include "enetc_ierb.h"
15 #define ENETC_DRV_NAME_STR "ENETC PF driver"
17 static void enetc_pf_get_primary_mac_addr(struct enetc_hw *hw, int si, u8 *addr)
19 u32 upper = __raw_readl(hw->port + ENETC_PSIPMAR0(si));
20 u16 lower = __raw_readw(hw->port + ENETC_PSIPMAR1(si));
22 put_unaligned_le32(upper, addr);
23 put_unaligned_le16(lower, addr + 4);
26 static void enetc_pf_set_primary_mac_addr(struct enetc_hw *hw, int si,
29 u32 upper = get_unaligned_le32(addr);
30 u16 lower = get_unaligned_le16(addr + 4);
32 __raw_writel(upper, hw->port + ENETC_PSIPMAR0(si));
33 __raw_writew(lower, hw->port + ENETC_PSIPMAR1(si));
36 static int enetc_pf_set_mac_addr(struct net_device *ndev, void *addr)
38 struct enetc_ndev_priv *priv = netdev_priv(ndev);
39 struct sockaddr *saddr = addr;
41 if (!is_valid_ether_addr(saddr->sa_data))
42 return -EADDRNOTAVAIL;
44 eth_hw_addr_set(ndev, saddr->sa_data);
45 enetc_pf_set_primary_mac_addr(&priv->si->hw, 0, saddr->sa_data);
50 static void enetc_set_vlan_promisc(struct enetc_hw *hw, char si_map)
52 u32 val = enetc_port_rd(hw, ENETC_PSIPVMR);
54 val &= ~ENETC_PSIPVMR_SET_VP(ENETC_VLAN_PROMISC_MAP_ALL);
55 enetc_port_wr(hw, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VP(si_map) | val);
58 static void enetc_enable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
60 pf->vlan_promisc_simap |= BIT(si_idx);
61 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
64 static void enetc_disable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
66 pf->vlan_promisc_simap &= ~BIT(si_idx);
67 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
70 static void enetc_set_isol_vlan(struct enetc_hw *hw, int si, u16 vlan, u8 qos)
75 val = ENETC_PSIVLAN_EN | ENETC_PSIVLAN_SET_QOS(qos) | vlan;
77 enetc_port_wr(hw, ENETC_PSIVLANR(si), val);
80 static int enetc_mac_addr_hash_idx(const u8 *addr)
82 u64 fold = __swab64(ether_addr_to_u64(addr)) >> 16;
87 for (i = 0; i < 8; i++)
88 mask |= BIT_ULL(i * 6);
90 for (i = 0; i < 6; i++)
91 res |= (hweight64(fold & (mask << i)) & 0x1) << i;
96 static void enetc_reset_mac_addr_filter(struct enetc_mac_filter *filter)
98 filter->mac_addr_cnt = 0;
100 bitmap_zero(filter->mac_hash_table,
101 ENETC_MADDR_HASH_TBL_SZ);
104 static void enetc_add_mac_addr_em_filter(struct enetc_mac_filter *filter,
105 const unsigned char *addr)
107 /* add exact match addr */
108 ether_addr_copy(filter->mac_addr, addr);
109 filter->mac_addr_cnt++;
112 static void enetc_add_mac_addr_ht_filter(struct enetc_mac_filter *filter,
113 const unsigned char *addr)
115 int idx = enetc_mac_addr_hash_idx(addr);
117 /* add hash table entry */
118 __set_bit(idx, filter->mac_hash_table);
119 filter->mac_addr_cnt++;
122 static void enetc_clear_mac_ht_flt(struct enetc_si *si, int si_idx, int type)
124 bool err = si->errata & ENETC_ERR_UCMCSWP;
127 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), 0);
128 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), 0);
130 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), 0);
131 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), 0);
135 static void enetc_set_mac_ht_flt(struct enetc_si *si, int si_idx, int type,
138 bool err = si->errata & ENETC_ERR_UCMCSWP;
141 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err),
142 lower_32_bits(hash));
143 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx),
144 upper_32_bits(hash));
146 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err),
147 lower_32_bits(hash));
148 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx),
149 upper_32_bits(hash));
153 static void enetc_sync_mac_filters(struct enetc_pf *pf)
155 struct enetc_mac_filter *f = pf->mac_filter;
156 struct enetc_si *si = pf->si;
159 pos = EMETC_MAC_ADDR_FILT_RES;
161 for (i = 0; i < MADDR_TYPE; i++, f++) {
162 bool em = (f->mac_addr_cnt == 1) && (i == UC);
163 bool clear = !f->mac_addr_cnt;
167 enetc_clear_mac_flt_entry(si, pos);
169 enetc_clear_mac_ht_flt(si, 0, i);
173 /* exact match filter */
177 enetc_clear_mac_ht_flt(si, 0, UC);
179 err = enetc_set_mac_flt_entry(si, pos, f->mac_addr,
184 /* fallback to HT filtering */
185 dev_warn(&si->pdev->dev, "fallback to HT filt (%d)\n",
189 /* hash table filter, clear EM filter for UC entries */
191 enetc_clear_mac_flt_entry(si, pos);
193 enetc_set_mac_ht_flt(si, 0, i, *f->mac_hash_table);
197 static void enetc_pf_set_rx_mode(struct net_device *ndev)
199 struct enetc_ndev_priv *priv = netdev_priv(ndev);
200 struct enetc_pf *pf = enetc_si_priv(priv->si);
201 struct enetc_hw *hw = &priv->si->hw;
202 bool uprom = false, mprom = false;
203 struct enetc_mac_filter *filter;
204 struct netdev_hw_addr *ha;
208 if (ndev->flags & IFF_PROMISC) {
209 /* enable promisc mode for SI0 (PF) */
210 psipmr = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0);
213 } else if (ndev->flags & IFF_ALLMULTI) {
214 /* enable multi cast promisc mode for SI0 (PF) */
215 psipmr = ENETC_PSIPMR_SET_MP(0);
219 /* first 2 filter entries belong to PF */
221 /* Update unicast filters */
222 filter = &pf->mac_filter[UC];
223 enetc_reset_mac_addr_filter(filter);
225 em = (netdev_uc_count(ndev) == 1);
226 netdev_for_each_uc_addr(ha, ndev) {
228 enetc_add_mac_addr_em_filter(filter, ha->addr);
232 enetc_add_mac_addr_ht_filter(filter, ha->addr);
237 /* Update multicast filters */
238 filter = &pf->mac_filter[MC];
239 enetc_reset_mac_addr_filter(filter);
241 netdev_for_each_mc_addr(ha, ndev) {
242 if (!is_multicast_ether_addr(ha->addr))
245 enetc_add_mac_addr_ht_filter(filter, ha->addr);
249 if (!uprom || !mprom)
250 /* update PF entries */
251 enetc_sync_mac_filters(pf);
253 psipmr |= enetc_port_rd(hw, ENETC_PSIPMR) &
254 ~(ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0));
255 enetc_port_wr(hw, ENETC_PSIPMR, psipmr);
258 static void enetc_set_vlan_ht_filter(struct enetc_hw *hw, int si_idx,
261 enetc_port_wr(hw, ENETC_PSIVHFR0(si_idx), lower_32_bits(hash));
262 enetc_port_wr(hw, ENETC_PSIVHFR1(si_idx), upper_32_bits(hash));
265 static int enetc_vid_hash_idx(unsigned int vid)
270 for (i = 0; i < 6; i++)
271 res |= (hweight8(vid & (BIT(i) | BIT(i + 6))) & 0x1) << i;
276 static void enetc_sync_vlan_ht_filter(struct enetc_pf *pf, bool rehash)
281 bitmap_zero(pf->vlan_ht_filter, ENETC_VLAN_HT_SIZE);
283 for_each_set_bit(i, pf->active_vlans, VLAN_N_VID) {
284 int hidx = enetc_vid_hash_idx(i);
286 __set_bit(hidx, pf->vlan_ht_filter);
290 enetc_set_vlan_ht_filter(&pf->si->hw, 0, *pf->vlan_ht_filter);
293 static int enetc_vlan_rx_add_vid(struct net_device *ndev, __be16 prot, u16 vid)
295 struct enetc_ndev_priv *priv = netdev_priv(ndev);
296 struct enetc_pf *pf = enetc_si_priv(priv->si);
299 __set_bit(vid, pf->active_vlans);
301 idx = enetc_vid_hash_idx(vid);
302 if (!__test_and_set_bit(idx, pf->vlan_ht_filter))
303 enetc_sync_vlan_ht_filter(pf, false);
308 static int enetc_vlan_rx_del_vid(struct net_device *ndev, __be16 prot, u16 vid)
310 struct enetc_ndev_priv *priv = netdev_priv(ndev);
311 struct enetc_pf *pf = enetc_si_priv(priv->si);
313 __clear_bit(vid, pf->active_vlans);
314 enetc_sync_vlan_ht_filter(pf, true);
319 static void enetc_set_loopback(struct net_device *ndev, bool en)
321 struct enetc_ndev_priv *priv = netdev_priv(ndev);
322 struct enetc_hw *hw = &priv->si->hw;
325 reg = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
326 if (reg & ENETC_PM0_IFM_RG) {
328 reg = (reg & ~ENETC_PM0_IFM_RLP) |
329 (en ? ENETC_PM0_IFM_RLP : 0);
330 enetc_port_wr(hw, ENETC_PM0_IF_MODE, reg);
332 /* assume SGMII mode */
333 reg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
334 reg = (reg & ~ENETC_PM0_CMD_XGLP) |
335 (en ? ENETC_PM0_CMD_XGLP : 0);
336 reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) |
337 (en ? ENETC_PM0_CMD_PHY_TX_EN : 0);
338 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, reg);
339 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, reg);
343 static int enetc_pf_set_vf_mac(struct net_device *ndev, int vf, u8 *mac)
345 struct enetc_ndev_priv *priv = netdev_priv(ndev);
346 struct enetc_pf *pf = enetc_si_priv(priv->si);
347 struct enetc_vf_state *vf_state;
349 if (vf >= pf->total_vfs)
352 if (!is_valid_ether_addr(mac))
353 return -EADDRNOTAVAIL;
355 vf_state = &pf->vf_state[vf];
356 vf_state->flags |= ENETC_VF_FLAG_PF_SET_MAC;
357 enetc_pf_set_primary_mac_addr(&priv->si->hw, vf + 1, mac);
361 static int enetc_pf_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan,
362 u8 qos, __be16 proto)
364 struct enetc_ndev_priv *priv = netdev_priv(ndev);
365 struct enetc_pf *pf = enetc_si_priv(priv->si);
367 if (priv->si->errata & ENETC_ERR_VLAN_ISOL)
370 if (vf >= pf->total_vfs)
373 if (proto != htons(ETH_P_8021Q))
374 /* only C-tags supported for now */
375 return -EPROTONOSUPPORT;
377 enetc_set_isol_vlan(&priv->si->hw, vf + 1, vlan, qos);
381 static int enetc_pf_set_vf_spoofchk(struct net_device *ndev, int vf, bool en)
383 struct enetc_ndev_priv *priv = netdev_priv(ndev);
384 struct enetc_pf *pf = enetc_si_priv(priv->si);
387 if (vf >= pf->total_vfs)
390 cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1));
391 cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0);
392 enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr);
397 static int enetc_setup_mac_address(struct device_node *np, struct enetc_pf *pf,
400 struct device *dev = &pf->si->pdev->dev;
401 struct enetc_hw *hw = &pf->si->hw;
402 u8 mac_addr[ETH_ALEN] = { 0 };
405 /* (1) try to get the MAC address from the device tree */
407 err = of_get_mac_address(np, mac_addr);
408 if (err == -EPROBE_DEFER)
412 /* (2) bootloader supplied MAC address */
413 if (is_zero_ether_addr(mac_addr))
414 enetc_pf_get_primary_mac_addr(hw, si, mac_addr);
416 /* (3) choose a random one */
417 if (is_zero_ether_addr(mac_addr)) {
418 eth_random_addr(mac_addr);
419 dev_info(dev, "no MAC address specified for SI%d, using %pM\n",
423 enetc_pf_set_primary_mac_addr(hw, si, mac_addr);
428 static int enetc_setup_mac_addresses(struct device_node *np,
433 /* The PF might take its MAC from the device tree */
434 err = enetc_setup_mac_address(np, pf, 0);
438 for (i = 0; i < pf->total_vfs; i++) {
439 err = enetc_setup_mac_address(NULL, pf, i + 1);
447 static void enetc_port_assign_rfs_entries(struct enetc_si *si)
449 struct enetc_pf *pf = enetc_si_priv(si);
450 struct enetc_hw *hw = &si->hw;
451 int num_entries, vf_entries, i;
454 /* split RFS entries between functions */
455 val = enetc_port_rd(hw, ENETC_PRFSCAPR);
456 num_entries = ENETC_PRFSCAPR_GET_NUM_RFS(val);
457 vf_entries = num_entries / (pf->total_vfs + 1);
459 for (i = 0; i < pf->total_vfs; i++)
460 enetc_port_wr(hw, ENETC_PSIRFSCFGR(i + 1), vf_entries);
461 enetc_port_wr(hw, ENETC_PSIRFSCFGR(0),
462 num_entries - vf_entries * pf->total_vfs);
464 /* enable RFS on port */
465 enetc_port_wr(hw, ENETC_PRFSMR, ENETC_PRFSMR_RFSE);
468 static void enetc_port_si_configure(struct enetc_si *si)
470 struct enetc_pf *pf = enetc_si_priv(si);
471 struct enetc_hw *hw = &si->hw;
475 val = enetc_port_rd(hw, ENETC_PCAPR0);
476 num_rings = min(ENETC_PCAPR0_RXBDR(val), ENETC_PCAPR0_TXBDR(val));
478 val = ENETC_PSICFGR0_SET_TXBDR(ENETC_PF_NUM_RINGS);
479 val |= ENETC_PSICFGR0_SET_RXBDR(ENETC_PF_NUM_RINGS);
481 if (unlikely(num_rings < ENETC_PF_NUM_RINGS)) {
482 val = ENETC_PSICFGR0_SET_TXBDR(num_rings);
483 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
485 dev_warn(&si->pdev->dev, "Found %d rings, expected %d!\n",
486 num_rings, ENETC_PF_NUM_RINGS);
491 /* Add default one-time settings for SI0 (PF) */
492 val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
494 enetc_port_wr(hw, ENETC_PSICFGR0(0), val);
497 num_rings -= ENETC_PF_NUM_RINGS;
499 /* Configure the SIs for each available VF */
500 val = ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
501 val |= ENETC_PSICFGR0_VTE | ENETC_PSICFGR0_SIVIE;
504 num_rings /= pf->total_vfs;
505 val |= ENETC_PSICFGR0_SET_TXBDR(num_rings);
506 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
509 for (i = 0; i < pf->total_vfs; i++)
510 enetc_port_wr(hw, ENETC_PSICFGR0(i + 1), val);
512 /* Port level VLAN settings */
513 val = ENETC_PVCLCTR_OVTPIDL(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
514 enetc_port_wr(hw, ENETC_PVCLCTR, val);
515 /* use outer tag for VLAN filtering */
516 enetc_port_wr(hw, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS);
519 static void enetc_configure_port_mac(struct enetc_hw *hw)
523 enetc_port_wr(hw, ENETC_PM0_MAXFRM,
524 ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE));
526 for (tc = 0; tc < 8; tc++)
527 enetc_port_wr(hw, ENETC_PTCMSDUR(tc), ENETC_MAC_MAXFRM_SIZE);
529 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
530 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
532 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
533 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
535 /* On LS1028A, the MAC RX FIFO defaults to 2, which is too high
536 * and may lead to RX lock-up under traffic. Set it to 1 instead,
537 * as recommended by the hardware team.
539 enetc_port_wr(hw, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL);
542 static void enetc_mac_config(struct enetc_hw *hw, phy_interface_t phy_mode)
546 if (phy_interface_mode_is_rgmii(phy_mode)) {
547 val = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
548 val &= ~(ENETC_PM0_IFM_EN_AUTO | ENETC_PM0_IFM_IFMODE_MASK);
549 val |= ENETC_PM0_IFM_IFMODE_GMII | ENETC_PM0_IFM_RG;
550 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
553 if (phy_mode == PHY_INTERFACE_MODE_USXGMII) {
554 val = ENETC_PM0_IFM_FULL_DPX | ENETC_PM0_IFM_IFMODE_XGMII;
555 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
559 static void enetc_mac_enable(struct enetc_hw *hw, bool en)
561 u32 val = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
563 val &= ~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
564 val |= en ? (ENETC_PM0_TX_EN | ENETC_PM0_RX_EN) : 0;
566 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, val);
567 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, val);
570 static void enetc_configure_port_pmac(struct enetc_hw *hw)
574 /* Set pMAC step lock */
575 temp = enetc_port_rd(hw, ENETC_PFPMR);
576 enetc_port_wr(hw, ENETC_PFPMR,
577 temp | ENETC_PFPMR_PMACE | ENETC_PFPMR_MWLM);
579 temp = enetc_port_rd(hw, ENETC_MMCSR);
580 enetc_port_wr(hw, ENETC_MMCSR, temp | ENETC_MMCSR_ME);
583 static void enetc_configure_port(struct enetc_pf *pf)
585 u8 hash_key[ENETC_RSSHASH_KEY_SIZE];
586 struct enetc_hw *hw = &pf->si->hw;
588 enetc_configure_port_pmac(hw);
590 enetc_configure_port_mac(hw);
592 enetc_port_si_configure(pf->si);
594 /* set up hash key */
595 get_random_bytes(hash_key, ENETC_RSSHASH_KEY_SIZE);
596 enetc_set_rss_key(hw, hash_key);
598 /* split up RFS entries */
599 enetc_port_assign_rfs_entries(pf->si);
601 /* enforce VLAN promisc mode for all SIs */
602 pf->vlan_promisc_simap = ENETC_VLAN_PROMISC_MAP_ALL;
603 enetc_set_vlan_promisc(hw, pf->vlan_promisc_simap);
605 enetc_port_wr(hw, ENETC_PSIPMR, 0);
608 enetc_port_wr(hw, ENETC_PMR, ENETC_PMR_EN);
612 static u16 enetc_msg_pf_set_vf_primary_mac_addr(struct enetc_pf *pf,
615 struct enetc_vf_state *vf_state = &pf->vf_state[vf_id];
616 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
617 struct enetc_msg_cmd_set_primary_mac *cmd;
618 struct device *dev = &pf->si->pdev->dev;
622 cmd = (struct enetc_msg_cmd_set_primary_mac *)msg->vaddr;
623 cmd_id = cmd->header.id;
624 if (cmd_id != ENETC_MSG_CMD_MNG_ADD)
625 return ENETC_MSG_CMD_STATUS_FAIL;
627 addr = cmd->mac.sa_data;
628 if (vf_state->flags & ENETC_VF_FLAG_PF_SET_MAC)
629 dev_warn(dev, "Attempt to override PF set mac addr for VF%d\n",
632 enetc_pf_set_primary_mac_addr(&pf->si->hw, vf_id + 1, addr);
634 return ENETC_MSG_CMD_STATUS_OK;
637 void enetc_msg_handle_rxmsg(struct enetc_pf *pf, int vf_id, u16 *status)
639 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
640 struct device *dev = &pf->si->pdev->dev;
641 struct enetc_msg_cmd_header *cmd_hdr;
644 *status = ENETC_MSG_CMD_STATUS_OK;
645 cmd_hdr = (struct enetc_msg_cmd_header *)msg->vaddr;
646 cmd_type = cmd_hdr->type;
649 case ENETC_MSG_CMD_MNG_MAC:
650 *status = enetc_msg_pf_set_vf_primary_mac_addr(pf, vf_id);
653 dev_err(dev, "command not supported (cmd_type: 0x%x)\n",
658 #ifdef CONFIG_PCI_IOV
659 static int enetc_sriov_configure(struct pci_dev *pdev, int num_vfs)
661 struct enetc_si *si = pci_get_drvdata(pdev);
662 struct enetc_pf *pf = enetc_si_priv(si);
666 enetc_msg_psi_free(pf);
669 pci_disable_sriov(pdev);
671 pf->num_vfs = num_vfs;
673 pf->vf_state = kcalloc(num_vfs, sizeof(struct enetc_vf_state),
680 err = enetc_msg_psi_init(pf);
682 dev_err(&pdev->dev, "enetc_msg_psi_init (%d)\n", err);
686 err = pci_enable_sriov(pdev, num_vfs);
688 dev_err(&pdev->dev, "pci_enable_sriov err %d\n", err);
696 enetc_msg_psi_free(pf);
704 #define enetc_sriov_configure(pdev, num_vfs) (void)0
707 static int enetc_pf_set_features(struct net_device *ndev,
708 netdev_features_t features)
710 netdev_features_t changed = ndev->features ^ features;
711 struct enetc_ndev_priv *priv = netdev_priv(ndev);
714 if (changed & NETIF_F_HW_TC) {
715 err = enetc_set_psfp(ndev, !!(features & NETIF_F_HW_TC));
720 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
721 struct enetc_pf *pf = enetc_si_priv(priv->si);
723 if (!!(features & NETIF_F_HW_VLAN_CTAG_FILTER))
724 enetc_disable_si_vlan_promisc(pf, 0);
726 enetc_enable_si_vlan_promisc(pf, 0);
729 if (changed & NETIF_F_LOOPBACK)
730 enetc_set_loopback(ndev, !!(features & NETIF_F_LOOPBACK));
732 enetc_set_features(ndev, features);
737 static int enetc_pf_setup_tc(struct net_device *ndev, enum tc_setup_type type,
741 case TC_SETUP_QDISC_MQPRIO:
742 return enetc_setup_tc_mqprio(ndev, type_data);
743 case TC_SETUP_QDISC_TAPRIO:
744 return enetc_setup_tc_taprio(ndev, type_data);
745 case TC_SETUP_QDISC_CBS:
746 return enetc_setup_tc_cbs(ndev, type_data);
747 case TC_SETUP_QDISC_ETF:
748 return enetc_setup_tc_txtime(ndev, type_data);
750 return enetc_setup_tc_psfp(ndev, type_data);
756 static const struct net_device_ops enetc_ndev_ops = {
757 .ndo_open = enetc_open,
758 .ndo_stop = enetc_close,
759 .ndo_start_xmit = enetc_xmit,
760 .ndo_get_stats = enetc_get_stats,
761 .ndo_set_mac_address = enetc_pf_set_mac_addr,
762 .ndo_set_rx_mode = enetc_pf_set_rx_mode,
763 .ndo_vlan_rx_add_vid = enetc_vlan_rx_add_vid,
764 .ndo_vlan_rx_kill_vid = enetc_vlan_rx_del_vid,
765 .ndo_set_vf_mac = enetc_pf_set_vf_mac,
766 .ndo_set_vf_vlan = enetc_pf_set_vf_vlan,
767 .ndo_set_vf_spoofchk = enetc_pf_set_vf_spoofchk,
768 .ndo_set_features = enetc_pf_set_features,
769 .ndo_eth_ioctl = enetc_ioctl,
770 .ndo_setup_tc = enetc_pf_setup_tc,
771 .ndo_bpf = enetc_setup_bpf,
772 .ndo_xdp_xmit = enetc_xdp_xmit,
775 static void enetc_pf_netdev_setup(struct enetc_si *si, struct net_device *ndev,
776 const struct net_device_ops *ndev_ops)
778 struct enetc_ndev_priv *priv = netdev_priv(ndev);
780 SET_NETDEV_DEV(ndev, &si->pdev->dev);
783 priv->dev = &si->pdev->dev;
786 priv->msg_enable = (NETIF_MSG_WOL << 1) - 1;
787 ndev->netdev_ops = ndev_ops;
788 enetc_set_ethtool_ops(ndev);
789 ndev->watchdog_timeo = 5 * HZ;
790 ndev->max_mtu = ENETC_MAX_MTU;
792 ndev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
793 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
794 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_LOOPBACK |
795 NETIF_F_HW_CSUM | NETIF_F_TSO | NETIF_F_TSO6;
796 ndev->features = NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_RXCSUM |
797 NETIF_F_HW_VLAN_CTAG_TX |
798 NETIF_F_HW_VLAN_CTAG_RX |
799 NETIF_F_HW_CSUM | NETIF_F_TSO | NETIF_F_TSO6;
800 ndev->vlan_features = NETIF_F_SG | NETIF_F_HW_CSUM |
801 NETIF_F_TSO | NETIF_F_TSO6;
804 ndev->hw_features |= NETIF_F_RXHASH;
806 ndev->priv_flags |= IFF_UNICAST_FLT;
808 if (si->hw_features & ENETC_SI_F_PSFP && !enetc_psfp_enable(priv)) {
809 priv->active_offloads |= ENETC_F_QCI;
810 ndev->features |= NETIF_F_HW_TC;
811 ndev->hw_features |= NETIF_F_HW_TC;
814 /* pick up primary MAC address from SI */
815 enetc_load_primary_mac_addr(&si->hw, ndev);
818 static int enetc_mdio_probe(struct enetc_pf *pf, struct device_node *np)
820 struct device *dev = &pf->si->pdev->dev;
821 struct enetc_mdio_priv *mdio_priv;
825 bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv));
829 bus->name = "Freescale ENETC MDIO Bus";
830 bus->read = enetc_mdio_read;
831 bus->write = enetc_mdio_write;
833 mdio_priv = bus->priv;
834 mdio_priv->hw = &pf->si->hw;
835 mdio_priv->mdio_base = ENETC_EMDIO_BASE;
836 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev));
838 err = of_mdiobus_register(bus, np);
840 return dev_err_probe(dev, err, "cannot register MDIO bus\n");
847 static void enetc_mdio_remove(struct enetc_pf *pf)
850 mdiobus_unregister(pf->mdio);
853 static int enetc_imdio_create(struct enetc_pf *pf)
855 struct device *dev = &pf->si->pdev->dev;
856 struct enetc_mdio_priv *mdio_priv;
857 struct phylink_pcs *phylink_pcs;
858 struct mdio_device *mdio_device;
862 bus = mdiobus_alloc_size(sizeof(*mdio_priv));
866 bus->name = "Freescale ENETC internal MDIO Bus";
867 bus->read = enetc_mdio_read;
868 bus->write = enetc_mdio_write;
871 mdio_priv = bus->priv;
872 mdio_priv->hw = &pf->si->hw;
873 mdio_priv->mdio_base = ENETC_PM_IMDIO_BASE;
874 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
876 err = mdiobus_register(bus);
878 dev_err(dev, "cannot register internal MDIO bus (%d)\n", err);
882 mdio_device = mdio_device_create(bus, 0);
883 if (IS_ERR(mdio_device)) {
884 err = PTR_ERR(mdio_device);
885 dev_err(dev, "cannot create mdio device (%d)\n", err);
886 goto unregister_mdiobus;
889 phylink_pcs = lynx_pcs_create(mdio_device);
891 mdio_device_free(mdio_device);
893 dev_err(dev, "cannot create lynx pcs (%d)\n", err);
894 goto unregister_mdiobus;
898 pf->pcs = phylink_pcs;
903 mdiobus_unregister(bus);
909 static void enetc_imdio_remove(struct enetc_pf *pf)
911 struct mdio_device *mdio_device;
914 mdio_device = lynx_get_mdio_device(pf->pcs);
915 mdio_device_free(mdio_device);
916 lynx_pcs_destroy(pf->pcs);
919 mdiobus_unregister(pf->imdio);
920 mdiobus_free(pf->imdio);
924 static bool enetc_port_has_pcs(struct enetc_pf *pf)
926 return (pf->if_mode == PHY_INTERFACE_MODE_SGMII ||
927 pf->if_mode == PHY_INTERFACE_MODE_2500BASEX ||
928 pf->if_mode == PHY_INTERFACE_MODE_USXGMII);
931 static int enetc_mdiobus_create(struct enetc_pf *pf, struct device_node *node)
933 struct device_node *mdio_np;
936 mdio_np = of_get_child_by_name(node, "mdio");
938 err = enetc_mdio_probe(pf, mdio_np);
940 of_node_put(mdio_np);
945 if (enetc_port_has_pcs(pf)) {
946 err = enetc_imdio_create(pf);
948 enetc_mdio_remove(pf);
956 static void enetc_mdiobus_destroy(struct enetc_pf *pf)
958 enetc_mdio_remove(pf);
959 enetc_imdio_remove(pf);
962 static struct phylink_pcs *
963 enetc_pl_mac_select_pcs(struct phylink_config *config, phy_interface_t iface)
965 struct enetc_pf *pf = phylink_to_enetc_pf(config);
970 static void enetc_pl_mac_config(struct phylink_config *config,
972 const struct phylink_link_state *state)
974 struct enetc_pf *pf = phylink_to_enetc_pf(config);
976 enetc_mac_config(&pf->si->hw, state->interface);
979 static void enetc_force_rgmii_mac(struct enetc_hw *hw, int speed, int duplex)
983 old_val = val = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
985 if (speed == SPEED_1000) {
986 val &= ~ENETC_PM0_IFM_SSP_MASK;
987 val |= ENETC_PM0_IFM_SSP_1000;
988 } else if (speed == SPEED_100) {
989 val &= ~ENETC_PM0_IFM_SSP_MASK;
990 val |= ENETC_PM0_IFM_SSP_100;
991 } else if (speed == SPEED_10) {
992 val &= ~ENETC_PM0_IFM_SSP_MASK;
993 val |= ENETC_PM0_IFM_SSP_10;
996 if (duplex == DUPLEX_FULL)
997 val |= ENETC_PM0_IFM_FULL_DPX;
999 val &= ~ENETC_PM0_IFM_FULL_DPX;
1004 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
1007 static void enetc_pl_mac_link_up(struct phylink_config *config,
1008 struct phy_device *phy, unsigned int mode,
1009 phy_interface_t interface, int speed,
1010 int duplex, bool tx_pause, bool rx_pause)
1012 struct enetc_pf *pf = phylink_to_enetc_pf(config);
1013 u32 pause_off_thresh = 0, pause_on_thresh = 0;
1014 u32 init_quanta = 0, refresh_quanta = 0;
1015 struct enetc_hw *hw = &pf->si->hw;
1016 struct enetc_ndev_priv *priv;
1020 priv = netdev_priv(pf->si->ndev);
1022 if (pf->si->hw_features & ENETC_SI_F_QBV)
1023 enetc_sched_speed_set(priv, speed);
1025 if (!phylink_autoneg_inband(mode) &&
1026 phy_interface_mode_is_rgmii(interface))
1027 enetc_force_rgmii_mac(hw, speed, duplex);
1030 for (idx = 0; idx < priv->num_rx_rings; idx++) {
1031 rbmr = enetc_rxbdr_rd(hw, idx, ENETC_RBMR);
1034 rbmr |= ENETC_RBMR_CM;
1036 rbmr &= ~ENETC_RBMR_CM;
1038 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr);
1042 /* When the port first enters congestion, send a PAUSE request
1043 * with the maximum number of quanta. When the port exits
1044 * congestion, it will automatically send a PAUSE frame with
1047 init_quanta = 0xffff;
1049 /* Also, set up the refresh timer to send follow-up PAUSE
1050 * frames at half the quanta value, in case the congestion
1051 * condition persists.
1053 refresh_quanta = 0xffff / 2;
1055 /* Start emitting PAUSE frames when 3 large frames (or more
1056 * smaller frames) have accumulated in the FIFO waiting to be
1057 * DMAed to the RX ring.
1059 pause_on_thresh = 3 * ENETC_MAC_MAXFRM_SIZE;
1060 pause_off_thresh = 1 * ENETC_MAC_MAXFRM_SIZE;
1063 enetc_port_wr(hw, ENETC_PM0_PAUSE_QUANTA, init_quanta);
1064 enetc_port_wr(hw, ENETC_PM1_PAUSE_QUANTA, init_quanta);
1065 enetc_port_wr(hw, ENETC_PM0_PAUSE_THRESH, refresh_quanta);
1066 enetc_port_wr(hw, ENETC_PM1_PAUSE_THRESH, refresh_quanta);
1067 enetc_port_wr(hw, ENETC_PPAUONTR, pause_on_thresh);
1068 enetc_port_wr(hw, ENETC_PPAUOFFTR, pause_off_thresh);
1070 cmd_cfg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
1073 cmd_cfg &= ~ENETC_PM0_PAUSE_IGN;
1075 cmd_cfg |= ENETC_PM0_PAUSE_IGN;
1077 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, cmd_cfg);
1078 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, cmd_cfg);
1080 enetc_mac_enable(hw, true);
1083 static void enetc_pl_mac_link_down(struct phylink_config *config,
1085 phy_interface_t interface)
1087 struct enetc_pf *pf = phylink_to_enetc_pf(config);
1089 enetc_mac_enable(&pf->si->hw, false);
1092 static const struct phylink_mac_ops enetc_mac_phylink_ops = {
1093 .validate = phylink_generic_validate,
1094 .mac_select_pcs = enetc_pl_mac_select_pcs,
1095 .mac_config = enetc_pl_mac_config,
1096 .mac_link_up = enetc_pl_mac_link_up,
1097 .mac_link_down = enetc_pl_mac_link_down,
1100 static int enetc_phylink_create(struct enetc_ndev_priv *priv,
1101 struct device_node *node)
1103 struct enetc_pf *pf = enetc_si_priv(priv->si);
1104 struct phylink *phylink;
1107 pf->phylink_config.dev = &priv->ndev->dev;
1108 pf->phylink_config.type = PHYLINK_NETDEV;
1109 pf->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1110 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
1112 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1113 pf->phylink_config.supported_interfaces);
1114 __set_bit(PHY_INTERFACE_MODE_SGMII,
1115 pf->phylink_config.supported_interfaces);
1116 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
1117 pf->phylink_config.supported_interfaces);
1118 __set_bit(PHY_INTERFACE_MODE_USXGMII,
1119 pf->phylink_config.supported_interfaces);
1120 phy_interface_set_rgmii(pf->phylink_config.supported_interfaces);
1122 phylink = phylink_create(&pf->phylink_config, of_fwnode_handle(node),
1123 pf->if_mode, &enetc_mac_phylink_ops);
1124 if (IS_ERR(phylink)) {
1125 err = PTR_ERR(phylink);
1129 priv->phylink = phylink;
1134 static void enetc_phylink_destroy(struct enetc_ndev_priv *priv)
1136 phylink_destroy(priv->phylink);
1139 /* Initialize the entire shared memory for the flow steering entries
1140 * of this port (PF + VFs)
1142 static int enetc_init_port_rfs_memory(struct enetc_si *si)
1144 struct enetc_cmd_rfse rfse = {0};
1145 struct enetc_hw *hw = &si->hw;
1146 int num_rfs, i, err = 0;
1149 val = enetc_port_rd(hw, ENETC_PRFSCAPR);
1150 num_rfs = ENETC_PRFSCAPR_GET_NUM_RFS(val);
1152 for (i = 0; i < num_rfs; i++) {
1153 err = enetc_set_fs_entry(si, &rfse, i);
1161 static int enetc_init_port_rss_memory(struct enetc_si *si)
1163 struct enetc_hw *hw = &si->hw;
1168 val = enetc_port_rd(hw, ENETC_PRSSCAPR);
1169 num_rss = ENETC_PRSSCAPR_GET_NUM_RSS(val);
1173 rss_table = kcalloc(num_rss, sizeof(*rss_table), GFP_KERNEL);
1177 err = enetc_set_rss_table(si, rss_table, num_rss);
1184 static int enetc_pf_register_with_ierb(struct pci_dev *pdev)
1186 struct device_node *node = pdev->dev.of_node;
1187 struct platform_device *ierb_pdev;
1188 struct device_node *ierb_node;
1190 /* Don't register with the IERB if the PF itself is disabled */
1191 if (!node || !of_device_is_available(node))
1194 ierb_node = of_find_compatible_node(NULL, NULL,
1195 "fsl,ls1028a-enetc-ierb");
1196 if (!ierb_node || !of_device_is_available(ierb_node))
1199 ierb_pdev = of_find_device_by_node(ierb_node);
1200 of_node_put(ierb_node);
1203 return -EPROBE_DEFER;
1205 return enetc_ierb_register_pf(ierb_pdev, pdev);
1208 static int enetc_pf_probe(struct pci_dev *pdev,
1209 const struct pci_device_id *ent)
1211 struct device_node *node = pdev->dev.of_node;
1212 struct enetc_ndev_priv *priv;
1213 struct net_device *ndev;
1214 struct enetc_si *si;
1215 struct enetc_pf *pf;
1218 err = enetc_pf_register_with_ierb(pdev);
1219 if (err == -EPROBE_DEFER)
1222 dev_warn(&pdev->dev,
1223 "Could not register with IERB driver: %pe, please update the device tree\n",
1226 err = enetc_pci_probe(pdev, KBUILD_MODNAME, sizeof(*pf));
1228 return dev_err_probe(&pdev->dev, err, "PCI probing failed\n");
1230 si = pci_get_drvdata(pdev);
1231 if (!si->hw.port || !si->hw.global) {
1233 dev_err(&pdev->dev, "could not map PF space, probing a VF?\n");
1234 goto err_map_pf_space;
1237 err = enetc_setup_cbdr(&pdev->dev, &si->hw, ENETC_CBDR_DEFAULT_SIZE,
1240 goto err_setup_cbdr;
1242 err = enetc_init_port_rfs_memory(si);
1244 dev_err(&pdev->dev, "Failed to initialize RFS memory\n");
1245 goto err_init_port_rfs;
1248 err = enetc_init_port_rss_memory(si);
1250 dev_err(&pdev->dev, "Failed to initialize RSS memory\n");
1251 goto err_init_port_rss;
1254 if (node && !of_device_is_available(node)) {
1255 dev_info(&pdev->dev, "device is disabled, skipping\n");
1257 goto err_device_disabled;
1260 pf = enetc_si_priv(si);
1262 pf->total_vfs = pci_sriov_get_totalvfs(pdev);
1264 err = enetc_setup_mac_addresses(node, pf);
1266 goto err_setup_mac_addresses;
1268 enetc_configure_port(pf);
1270 enetc_get_si_caps(si);
1272 ndev = alloc_etherdev_mq(sizeof(*priv), ENETC_MAX_NUM_TXQS);
1275 dev_err(&pdev->dev, "netdev creation failed\n");
1276 goto err_alloc_netdev;
1279 enetc_pf_netdev_setup(si, ndev, &enetc_ndev_ops);
1281 priv = netdev_priv(ndev);
1283 enetc_init_si_rings_params(priv);
1285 err = enetc_alloc_si_resources(priv);
1287 dev_err(&pdev->dev, "SI resource alloc failed\n");
1288 goto err_alloc_si_res;
1291 err = enetc_configure_si(priv);
1293 dev_err(&pdev->dev, "Failed to configure SI\n");
1297 err = enetc_alloc_msix(priv);
1299 dev_err(&pdev->dev, "MSIX alloc failed\n");
1300 goto err_alloc_msix;
1303 err = of_get_phy_mode(node, &pf->if_mode);
1305 dev_err(&pdev->dev, "Failed to read PHY mode\n");
1309 err = enetc_mdiobus_create(pf, node);
1311 goto err_mdiobus_create;
1313 err = enetc_phylink_create(priv, node);
1315 goto err_phylink_create;
1317 err = register_netdev(ndev);
1319 goto err_reg_netdev;
1324 enetc_phylink_destroy(priv);
1326 enetc_mdiobus_destroy(pf);
1329 enetc_free_msix(priv);
1332 enetc_free_si_resources(priv);
1339 err_device_disabled:
1340 err_setup_mac_addresses:
1341 enetc_teardown_cbdr(&si->cbd_ring);
1344 enetc_pci_remove(pdev);
1349 static void enetc_pf_remove(struct pci_dev *pdev)
1351 struct enetc_si *si = pci_get_drvdata(pdev);
1352 struct enetc_pf *pf = enetc_si_priv(si);
1353 struct enetc_ndev_priv *priv;
1355 priv = netdev_priv(si->ndev);
1358 enetc_sriov_configure(pdev, 0);
1360 unregister_netdev(si->ndev);
1362 enetc_phylink_destroy(priv);
1363 enetc_mdiobus_destroy(pf);
1365 enetc_free_msix(priv);
1367 enetc_free_si_resources(priv);
1368 enetc_teardown_cbdr(&si->cbd_ring);
1370 free_netdev(si->ndev);
1372 enetc_pci_remove(pdev);
1375 static const struct pci_device_id enetc_pf_id_table[] = {
1376 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF) },
1377 { 0, } /* End of table. */
1379 MODULE_DEVICE_TABLE(pci, enetc_pf_id_table);
1381 static struct pci_driver enetc_pf_driver = {
1382 .name = KBUILD_MODNAME,
1383 .id_table = enetc_pf_id_table,
1384 .probe = enetc_pf_probe,
1385 .remove = enetc_pf_remove,
1386 #ifdef CONFIG_PCI_IOV
1387 .sriov_configure = enetc_sriov_configure,
1390 module_pci_driver(enetc_pf_driver);
1392 MODULE_DESCRIPTION(ENETC_DRV_NAME_STR);
1393 MODULE_LICENSE("Dual BSD/GPL");