1 // SPDX-License-Identifier: GPL-2.0
2 /* Renesas Ethernet AVB device driver
4 * Copyright (C) 2014-2019 Renesas Electronics Corporation
5 * Copyright (C) 2015 Renesas Solutions Corp.
6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
8 * Based on the SuperH Ethernet driver
11 #include <linux/cache.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/if_vlan.h>
19 #include <linux/kernel.h>
20 #include <linux/list.h>
21 #include <linux/module.h>
22 #include <linux/net_tstamp.h>
24 #include <linux/of_device.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_mdio.h>
27 #include <linux/of_net.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/sys_soc.h>
32 #include <linux/reset.h>
33 #include <linux/math64.h>
37 #define RAVB_DEF_MSG_ENABLE \
43 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
48 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
53 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
56 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
59 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
63 for (i = 0; i < 10000; i++) {
64 if ((ravb_read(ndev, reg) & mask) == value)
71 static int ravb_config(struct net_device *ndev)
76 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
77 /* Check if the operating mode is changed to the config mode */
78 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
80 netdev_err(ndev, "failed to switch device to config mode\n");
85 static void ravb_set_rate_gbeth(struct net_device *ndev)
87 struct ravb_private *priv = netdev_priv(ndev);
89 switch (priv->speed) {
91 ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR);
93 case 100: /* 100BASE */
94 ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR);
96 case 1000: /* 1000BASE */
97 ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR);
102 static void ravb_set_rate_rcar(struct net_device *ndev)
104 struct ravb_private *priv = netdev_priv(ndev);
106 switch (priv->speed) {
107 case 100: /* 100BASE */
108 ravb_write(ndev, GECMR_SPEED_100, GECMR);
110 case 1000: /* 1000BASE */
111 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
116 static void ravb_set_buffer_align(struct sk_buff *skb)
118 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
121 skb_reserve(skb, RAVB_ALIGN - reserve);
124 /* Get MAC address from the MAC address registers
126 * Ethernet AVB device doesn't have ROM for MAC address.
127 * This function gets the MAC address that was used by a bootloader.
129 static void ravb_read_mac_address(struct device_node *np,
130 struct net_device *ndev)
134 ret = of_get_ethdev_address(np, ndev);
136 u32 mahr = ravb_read(ndev, MAHR);
137 u32 malr = ravb_read(ndev, MALR);
140 addr[0] = (mahr >> 24) & 0xFF;
141 addr[1] = (mahr >> 16) & 0xFF;
142 addr[2] = (mahr >> 8) & 0xFF;
143 addr[3] = (mahr >> 0) & 0xFF;
144 addr[4] = (malr >> 8) & 0xFF;
145 addr[5] = (malr >> 0) & 0xFF;
146 eth_hw_addr_set(ndev, addr);
150 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
152 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
155 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
158 /* MDC pin control */
159 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
161 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
164 /* Data I/O pin control */
165 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
167 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
171 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
173 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
177 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
179 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
182 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
185 /* MDIO bus control struct */
186 static const struct mdiobb_ops bb_ops = {
187 .owner = THIS_MODULE,
188 .set_mdc = ravb_set_mdc,
189 .set_mdio_dir = ravb_set_mdio_dir,
190 .set_mdio_data = ravb_set_mdio_data,
191 .get_mdio_data = ravb_get_mdio_data,
194 /* Free TX skb function for AVB-IP */
195 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
197 struct ravb_private *priv = netdev_priv(ndev);
198 struct net_device_stats *stats = &priv->stats[q];
199 unsigned int num_tx_desc = priv->num_tx_desc;
200 struct ravb_tx_desc *desc;
205 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
208 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
210 desc = &priv->tx_ring[q][entry];
211 txed = desc->die_dt == DT_FEMPTY;
212 if (free_txed_only && !txed)
214 /* Descriptor type must be checked before all other reads */
216 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
217 /* Free the original skb. */
218 if (priv->tx_skb[q][entry / num_tx_desc]) {
219 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
220 size, DMA_TO_DEVICE);
221 /* Last packet descriptor? */
222 if (entry % num_tx_desc == num_tx_desc - 1) {
223 entry /= num_tx_desc;
224 dev_kfree_skb_any(priv->tx_skb[q][entry]);
225 priv->tx_skb[q][entry] = NULL;
232 stats->tx_bytes += size;
233 desc->die_dt = DT_EEMPTY;
238 static void ravb_rx_ring_free_gbeth(struct net_device *ndev, int q)
240 struct ravb_private *priv = netdev_priv(ndev);
241 unsigned int ring_size;
244 if (!priv->gbeth_rx_ring)
247 for (i = 0; i < priv->num_rx_ring[q]; i++) {
248 struct ravb_rx_desc *desc = &priv->gbeth_rx_ring[i];
250 if (!dma_mapping_error(ndev->dev.parent,
251 le32_to_cpu(desc->dptr)))
252 dma_unmap_single(ndev->dev.parent,
253 le32_to_cpu(desc->dptr),
257 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1);
258 dma_free_coherent(ndev->dev.parent, ring_size, priv->gbeth_rx_ring,
259 priv->rx_desc_dma[q]);
260 priv->gbeth_rx_ring = NULL;
263 static void ravb_rx_ring_free_rcar(struct net_device *ndev, int q)
265 struct ravb_private *priv = netdev_priv(ndev);
266 unsigned int ring_size;
269 if (!priv->rx_ring[q])
272 for (i = 0; i < priv->num_rx_ring[q]; i++) {
273 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i];
275 if (!dma_mapping_error(ndev->dev.parent,
276 le32_to_cpu(desc->dptr)))
277 dma_unmap_single(ndev->dev.parent,
278 le32_to_cpu(desc->dptr),
282 ring_size = sizeof(struct ravb_ex_rx_desc) *
283 (priv->num_rx_ring[q] + 1);
284 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
285 priv->rx_desc_dma[q]);
286 priv->rx_ring[q] = NULL;
289 /* Free skb's and DMA buffers for Ethernet AVB */
290 static void ravb_ring_free(struct net_device *ndev, int q)
292 struct ravb_private *priv = netdev_priv(ndev);
293 const struct ravb_hw_info *info = priv->info;
294 unsigned int num_tx_desc = priv->num_tx_desc;
295 unsigned int ring_size;
298 info->rx_ring_free(ndev, q);
300 if (priv->tx_ring[q]) {
301 ravb_tx_free(ndev, q, false);
303 ring_size = sizeof(struct ravb_tx_desc) *
304 (priv->num_tx_ring[q] * num_tx_desc + 1);
305 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
306 priv->tx_desc_dma[q]);
307 priv->tx_ring[q] = NULL;
310 /* Free RX skb ringbuffer */
311 if (priv->rx_skb[q]) {
312 for (i = 0; i < priv->num_rx_ring[q]; i++)
313 dev_kfree_skb(priv->rx_skb[q][i]);
315 kfree(priv->rx_skb[q]);
316 priv->rx_skb[q] = NULL;
318 /* Free aligned TX buffers */
319 kfree(priv->tx_align[q]);
320 priv->tx_align[q] = NULL;
322 /* Free TX skb ringbuffer.
323 * SKBs are freed by ravb_tx_free() call above.
325 kfree(priv->tx_skb[q]);
326 priv->tx_skb[q] = NULL;
329 static void ravb_rx_ring_format_gbeth(struct net_device *ndev, int q)
331 struct ravb_private *priv = netdev_priv(ndev);
332 struct ravb_rx_desc *rx_desc;
333 unsigned int rx_ring_size;
337 rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
338 memset(priv->gbeth_rx_ring, 0, rx_ring_size);
339 /* Build RX ring buffer */
340 for (i = 0; i < priv->num_rx_ring[q]; i++) {
342 rx_desc = &priv->gbeth_rx_ring[i];
343 rx_desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE);
344 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
347 /* We just set the data size to 0 for a failed mapping which
348 * should prevent DMA from happening...
350 if (dma_mapping_error(ndev->dev.parent, dma_addr))
351 rx_desc->ds_cc = cpu_to_le16(0);
352 rx_desc->dptr = cpu_to_le32(dma_addr);
353 rx_desc->die_dt = DT_FEMPTY;
355 rx_desc = &priv->gbeth_rx_ring[i];
356 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
357 rx_desc->die_dt = DT_LINKFIX; /* type */
360 static void ravb_rx_ring_format_rcar(struct net_device *ndev, int q)
362 struct ravb_private *priv = netdev_priv(ndev);
363 struct ravb_ex_rx_desc *rx_desc;
364 unsigned int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
368 memset(priv->rx_ring[q], 0, rx_ring_size);
369 /* Build RX ring buffer */
370 for (i = 0; i < priv->num_rx_ring[q]; i++) {
372 rx_desc = &priv->rx_ring[q][i];
373 rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
374 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
377 /* We just set the data size to 0 for a failed mapping which
378 * should prevent DMA from happening...
380 if (dma_mapping_error(ndev->dev.parent, dma_addr))
381 rx_desc->ds_cc = cpu_to_le16(0);
382 rx_desc->dptr = cpu_to_le32(dma_addr);
383 rx_desc->die_dt = DT_FEMPTY;
385 rx_desc = &priv->rx_ring[q][i];
386 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
387 rx_desc->die_dt = DT_LINKFIX; /* type */
390 /* Format skb and descriptor buffer for Ethernet AVB */
391 static void ravb_ring_format(struct net_device *ndev, int q)
393 struct ravb_private *priv = netdev_priv(ndev);
394 const struct ravb_hw_info *info = priv->info;
395 unsigned int num_tx_desc = priv->num_tx_desc;
396 struct ravb_tx_desc *tx_desc;
397 struct ravb_desc *desc;
398 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
404 priv->dirty_rx[q] = 0;
405 priv->dirty_tx[q] = 0;
407 info->rx_ring_format(ndev, q);
409 memset(priv->tx_ring[q], 0, tx_ring_size);
410 /* Build TX ring buffer */
411 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
413 tx_desc->die_dt = DT_EEMPTY;
414 if (num_tx_desc > 1) {
416 tx_desc->die_dt = DT_EEMPTY;
419 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
420 tx_desc->die_dt = DT_LINKFIX; /* type */
422 /* RX descriptor base address for best effort */
423 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
424 desc->die_dt = DT_LINKFIX; /* type */
425 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
427 /* TX descriptor base address for best effort */
428 desc = &priv->desc_bat[q];
429 desc->die_dt = DT_LINKFIX; /* type */
430 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
433 static void *ravb_alloc_rx_desc_gbeth(struct net_device *ndev, int q)
435 struct ravb_private *priv = netdev_priv(ndev);
436 unsigned int ring_size;
438 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1);
440 priv->gbeth_rx_ring = dma_alloc_coherent(ndev->dev.parent, ring_size,
441 &priv->rx_desc_dma[q],
443 return priv->gbeth_rx_ring;
446 static void *ravb_alloc_rx_desc_rcar(struct net_device *ndev, int q)
448 struct ravb_private *priv = netdev_priv(ndev);
449 unsigned int ring_size;
451 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
453 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
454 &priv->rx_desc_dma[q],
456 return priv->rx_ring[q];
459 /* Init skb and descriptor buffer for Ethernet AVB */
460 static int ravb_ring_init(struct net_device *ndev, int q)
462 struct ravb_private *priv = netdev_priv(ndev);
463 const struct ravb_hw_info *info = priv->info;
464 unsigned int num_tx_desc = priv->num_tx_desc;
465 unsigned int ring_size;
469 /* Allocate RX and TX skb rings */
470 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
471 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
472 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
473 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
474 if (!priv->rx_skb[q] || !priv->tx_skb[q])
477 for (i = 0; i < priv->num_rx_ring[q]; i++) {
478 skb = __netdev_alloc_skb(ndev, info->max_rx_len, GFP_KERNEL);
481 ravb_set_buffer_align(skb);
482 priv->rx_skb[q][i] = skb;
485 if (num_tx_desc > 1) {
486 /* Allocate rings for the aligned buffers */
487 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
488 DPTR_ALIGN - 1, GFP_KERNEL);
489 if (!priv->tx_align[q])
493 /* Allocate all RX descriptors. */
494 if (!info->alloc_rx_desc(ndev, q))
497 priv->dirty_rx[q] = 0;
499 /* Allocate all TX descriptors. */
500 ring_size = sizeof(struct ravb_tx_desc) *
501 (priv->num_tx_ring[q] * num_tx_desc + 1);
502 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
503 &priv->tx_desc_dma[q],
505 if (!priv->tx_ring[q])
511 ravb_ring_free(ndev, q);
516 static void ravb_emac_init_gbeth(struct net_device *ndev)
518 struct ravb_private *priv = netdev_priv(ndev);
520 /* Receive frame limit set register */
521 ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR);
523 /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */
524 ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) |
525 ECMR_TE | ECMR_RE | ECMR_RCPT |
526 ECMR_TXF | ECMR_RXF, ECMR);
528 ravb_set_rate_gbeth(ndev);
530 /* Set MAC address */
532 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
533 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
534 ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
536 /* E-MAC status register clear */
537 ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR);
538 ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0);
540 /* E-MAC interrupt enable register */
541 ravb_write(ndev, ECSIPR_ICDIP, ECSIPR);
543 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, CXR31_SEL_LINK0);
546 static void ravb_emac_init_rcar(struct net_device *ndev)
548 /* Receive frame limit set register */
549 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
551 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
552 ravb_write(ndev, ECMR_ZPF | ECMR_DM |
553 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
554 ECMR_TE | ECMR_RE, ECMR);
556 ravb_set_rate_rcar(ndev);
558 /* Set MAC address */
560 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
561 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
563 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
565 /* E-MAC status register clear */
566 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
568 /* E-MAC interrupt enable register */
569 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
572 /* E-MAC init function */
573 static void ravb_emac_init(struct net_device *ndev)
575 struct ravb_private *priv = netdev_priv(ndev);
576 const struct ravb_hw_info *info = priv->info;
578 info->emac_init(ndev);
581 static int ravb_dmac_init_gbeth(struct net_device *ndev)
585 error = ravb_ring_init(ndev, RAVB_BE);
589 /* Descriptor format */
590 ravb_ring_format(ndev, RAVB_BE);
593 ravb_write(ndev, 0x60000000, RCR);
595 /* Set Max Frame Length (RTC) */
596 ravb_write(ndev, 0x7ffc0000 | GBETH_RX_BUFF_MAX, RTC);
599 ravb_write(ndev, 0x00222200, TGC);
601 ravb_write(ndev, 0, TCCR);
604 ravb_write(ndev, RIC0_FRE0, RIC0);
605 /* Disable FIFO full warning */
606 ravb_write(ndev, 0x0, RIC1);
607 /* Receive FIFO full error, descriptor empty */
608 ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2);
610 ravb_write(ndev, TIC_FTE0, TIC);
615 static int ravb_dmac_init_rcar(struct net_device *ndev)
617 struct ravb_private *priv = netdev_priv(ndev);
618 const struct ravb_hw_info *info = priv->info;
621 error = ravb_ring_init(ndev, RAVB_BE);
624 error = ravb_ring_init(ndev, RAVB_NC);
626 ravb_ring_free(ndev, RAVB_BE);
630 /* Descriptor format */
631 ravb_ring_format(ndev, RAVB_BE);
632 ravb_ring_format(ndev, RAVB_NC);
636 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
639 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC);
641 /* Timestamp enable */
642 ravb_write(ndev, TCCR_TFEN, TCCR);
644 /* Interrupt init: */
645 if (info->multi_irqs) {
647 ravb_write(ndev, 0, DIL);
648 /* Set queue specific interrupt */
649 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
652 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
653 /* Disable FIFO full warning */
654 ravb_write(ndev, 0, RIC1);
655 /* Receive FIFO full error, descriptor empty */
656 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
657 /* Frame transmitted, timestamp FIFO updated */
658 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
663 /* Device init function for Ethernet AVB */
664 static int ravb_dmac_init(struct net_device *ndev)
666 struct ravb_private *priv = netdev_priv(ndev);
667 const struct ravb_hw_info *info = priv->info;
670 /* Set CONFIG mode */
671 error = ravb_config(ndev);
675 error = info->dmac_init(ndev);
679 /* Setting the control will start the AVB-DMAC process. */
680 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
685 static void ravb_get_tx_tstamp(struct net_device *ndev)
687 struct ravb_private *priv = netdev_priv(ndev);
688 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
689 struct skb_shared_hwtstamps shhwtstamps;
691 struct timespec64 ts;
696 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
698 tfa2 = ravb_read(ndev, TFA2);
699 tfa_tag = (tfa2 & TFA2_TST) >> 16;
700 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
701 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
702 ravb_read(ndev, TFA1);
703 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
704 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
705 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
709 list_del(&ts_skb->list);
711 if (tag == tfa_tag) {
712 skb_tstamp_tx(skb, &shhwtstamps);
713 dev_consume_skb_any(skb);
716 dev_kfree_skb_any(skb);
719 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
723 static void ravb_rx_csum(struct sk_buff *skb)
727 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes
728 * appended to packet data
730 if (unlikely(skb->len < sizeof(__sum16)))
732 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
733 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
734 skb->ip_summed = CHECKSUM_COMPLETE;
735 skb_trim(skb, skb->len - sizeof(__sum16));
738 static struct sk_buff *ravb_get_skb_gbeth(struct net_device *ndev, int entry,
739 struct ravb_rx_desc *desc)
741 struct ravb_private *priv = netdev_priv(ndev);
744 skb = priv->rx_skb[RAVB_BE][entry];
745 priv->rx_skb[RAVB_BE][entry] = NULL;
746 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
747 ALIGN(GBETH_RX_BUFF_MAX, 16), DMA_FROM_DEVICE);
752 /* Packet receive function for Gigabit Ethernet */
753 static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q)
755 struct ravb_private *priv = netdev_priv(ndev);
756 const struct ravb_hw_info *info = priv->info;
757 struct net_device_stats *stats;
758 struct ravb_rx_desc *desc;
768 entry = priv->cur_rx[q] % priv->num_rx_ring[q];
769 boguscnt = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q];
770 stats = &priv->stats[q];
772 boguscnt = min(boguscnt, *quota);
774 desc = &priv->gbeth_rx_ring[entry];
775 while (desc->die_dt != DT_FEMPTY) {
776 /* Descriptor type must be checked before all other reads */
778 desc_status = desc->msc;
779 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
784 /* We use 0-byte descriptors to mark the DMA mapping errors */
788 if (desc_status & MSC_MC)
791 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | MSC_CEEF)) {
793 if (desc_status & MSC_CRC)
794 stats->rx_crc_errors++;
795 if (desc_status & MSC_RFE)
796 stats->rx_frame_errors++;
797 if (desc_status & (MSC_RTLF | MSC_RTSF))
798 stats->rx_length_errors++;
799 if (desc_status & MSC_CEEF)
800 stats->rx_missed_errors++;
802 die_dt = desc->die_dt & 0xF0;
805 skb = ravb_get_skb_gbeth(ndev, entry, desc);
806 skb_put(skb, pkt_len);
807 skb->protocol = eth_type_trans(skb, ndev);
808 napi_gro_receive(&priv->napi[q], skb);
810 stats->rx_bytes += pkt_len;
813 priv->rx_1st_skb = ravb_get_skb_gbeth(ndev, entry, desc);
814 skb_put(priv->rx_1st_skb, pkt_len);
817 skb = ravb_get_skb_gbeth(ndev, entry, desc);
818 skb_copy_to_linear_data_offset(priv->rx_1st_skb,
819 priv->rx_1st_skb->len,
822 skb_put(priv->rx_1st_skb, pkt_len);
826 skb = ravb_get_skb_gbeth(ndev, entry, desc);
827 skb_copy_to_linear_data_offset(priv->rx_1st_skb,
828 priv->rx_1st_skb->len,
831 skb_put(priv->rx_1st_skb, pkt_len);
833 priv->rx_1st_skb->protocol =
834 eth_type_trans(priv->rx_1st_skb, ndev);
835 napi_gro_receive(&priv->napi[q],
838 stats->rx_bytes += priv->rx_1st_skb->len;
843 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
844 desc = &priv->gbeth_rx_ring[entry];
847 /* Refill the RX ring buffers. */
848 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
849 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
850 desc = &priv->gbeth_rx_ring[entry];
851 desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE);
853 if (!priv->rx_skb[q][entry]) {
854 skb = netdev_alloc_skb(ndev, info->max_rx_len);
857 ravb_set_buffer_align(skb);
858 dma_addr = dma_map_single(ndev->dev.parent,
862 skb_checksum_none_assert(skb);
863 /* We just set the data size to 0 for a failed mapping
864 * which should prevent DMA from happening...
866 if (dma_mapping_error(ndev->dev.parent, dma_addr))
867 desc->ds_cc = cpu_to_le16(0);
868 desc->dptr = cpu_to_le32(dma_addr);
869 priv->rx_skb[q][entry] = skb;
871 /* Descriptor type must be set after all the above writes */
873 desc->die_dt = DT_FEMPTY;
876 *quota -= limit - (++boguscnt);
878 return boguscnt <= 0;
881 /* Packet receive function for Ethernet AVB */
882 static bool ravb_rx_rcar(struct net_device *ndev, int *quota, int q)
884 struct ravb_private *priv = netdev_priv(ndev);
885 const struct ravb_hw_info *info = priv->info;
886 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
887 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
889 struct net_device_stats *stats = &priv->stats[q];
890 struct ravb_ex_rx_desc *desc;
893 struct timespec64 ts;
898 boguscnt = min(boguscnt, *quota);
900 desc = &priv->rx_ring[q][entry];
901 while (desc->die_dt != DT_FEMPTY) {
902 /* Descriptor type must be checked before all other reads */
904 desc_status = desc->msc;
905 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
910 /* We use 0-byte descriptors to mark the DMA mapping errors */
914 if (desc_status & MSC_MC)
917 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
920 if (desc_status & MSC_CRC)
921 stats->rx_crc_errors++;
922 if (desc_status & MSC_RFE)
923 stats->rx_frame_errors++;
924 if (desc_status & (MSC_RTLF | MSC_RTSF))
925 stats->rx_length_errors++;
926 if (desc_status & MSC_CEEF)
927 stats->rx_missed_errors++;
929 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
931 skb = priv->rx_skb[q][entry];
932 priv->rx_skb[q][entry] = NULL;
933 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
936 get_ts &= (q == RAVB_NC) ?
937 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
938 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
940 struct skb_shared_hwtstamps *shhwtstamps;
942 shhwtstamps = skb_hwtstamps(skb);
943 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
944 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
945 32) | le32_to_cpu(desc->ts_sl);
946 ts.tv_nsec = le32_to_cpu(desc->ts_n);
947 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
950 skb_put(skb, pkt_len);
951 skb->protocol = eth_type_trans(skb, ndev);
952 if (ndev->features & NETIF_F_RXCSUM)
954 napi_gro_receive(&priv->napi[q], skb);
956 stats->rx_bytes += pkt_len;
959 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
960 desc = &priv->rx_ring[q][entry];
963 /* Refill the RX ring buffers. */
964 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
965 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
966 desc = &priv->rx_ring[q][entry];
967 desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
969 if (!priv->rx_skb[q][entry]) {
970 skb = netdev_alloc_skb(ndev, info->max_rx_len);
972 break; /* Better luck next round. */
973 ravb_set_buffer_align(skb);
974 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
975 le16_to_cpu(desc->ds_cc),
977 skb_checksum_none_assert(skb);
978 /* We just set the data size to 0 for a failed mapping
979 * which should prevent DMA from happening...
981 if (dma_mapping_error(ndev->dev.parent, dma_addr))
982 desc->ds_cc = cpu_to_le16(0);
983 desc->dptr = cpu_to_le32(dma_addr);
984 priv->rx_skb[q][entry] = skb;
986 /* Descriptor type must be set after all the above writes */
988 desc->die_dt = DT_FEMPTY;
991 *quota -= limit - (++boguscnt);
993 return boguscnt <= 0;
996 /* Packet receive function for Ethernet AVB */
997 static bool ravb_rx(struct net_device *ndev, int *quota, int q)
999 struct ravb_private *priv = netdev_priv(ndev);
1000 const struct ravb_hw_info *info = priv->info;
1002 return info->receive(ndev, quota, q);
1005 static void ravb_rcv_snd_disable(struct net_device *ndev)
1007 /* Disable TX and RX */
1008 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1011 static void ravb_rcv_snd_enable(struct net_device *ndev)
1013 /* Enable TX and RX */
1014 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1017 /* function for waiting dma process finished */
1018 static int ravb_stop_dma(struct net_device *ndev)
1020 struct ravb_private *priv = netdev_priv(ndev);
1021 const struct ravb_hw_info *info = priv->info;
1024 /* Wait for stopping the hardware TX process */
1025 error = ravb_wait(ndev, TCCR, info->tccr_mask, 0);
1030 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
1035 /* Stop the E-MAC's RX/TX processes. */
1036 ravb_rcv_snd_disable(ndev);
1038 /* Wait for stopping the RX DMA process */
1039 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
1043 /* Stop AVB-DMAC process */
1044 return ravb_config(ndev);
1047 /* E-MAC interrupt handler */
1048 static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
1050 struct ravb_private *priv = netdev_priv(ndev);
1053 ecsr = ravb_read(ndev, ECSR);
1054 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
1056 if (ecsr & ECSR_MPD)
1057 pm_wakeup_event(&priv->pdev->dev, 0);
1058 if (ecsr & ECSR_ICD)
1059 ndev->stats.tx_carrier_errors++;
1060 if (ecsr & ECSR_LCHNG) {
1062 if (priv->no_avb_link)
1064 psr = ravb_read(ndev, PSR);
1065 if (priv->avb_link_active_low)
1067 if (!(psr & PSR_LMON)) {
1068 /* DIsable RX and TX */
1069 ravb_rcv_snd_disable(ndev);
1071 /* Enable RX and TX */
1072 ravb_rcv_snd_enable(ndev);
1077 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
1079 struct net_device *ndev = dev_id;
1080 struct ravb_private *priv = netdev_priv(ndev);
1082 spin_lock(&priv->lock);
1083 ravb_emac_interrupt_unlocked(ndev);
1084 spin_unlock(&priv->lock);
1088 /* Error interrupt handler */
1089 static void ravb_error_interrupt(struct net_device *ndev)
1091 struct ravb_private *priv = netdev_priv(ndev);
1094 eis = ravb_read(ndev, EIS);
1095 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS);
1096 if (eis & EIS_QFS) {
1097 ris2 = ravb_read(ndev, RIS2);
1098 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF | RIS2_RESERVED),
1101 /* Receive Descriptor Empty int */
1102 if (ris2 & RIS2_QFF0)
1103 priv->stats[RAVB_BE].rx_over_errors++;
1105 /* Receive Descriptor Empty int */
1106 if (ris2 & RIS2_QFF1)
1107 priv->stats[RAVB_NC].rx_over_errors++;
1109 /* Receive FIFO Overflow int */
1110 if (ris2 & RIS2_RFFF)
1111 priv->rx_fifo_errors++;
1115 static bool ravb_queue_interrupt(struct net_device *ndev, int q)
1117 struct ravb_private *priv = netdev_priv(ndev);
1118 const struct ravb_hw_info *info = priv->info;
1119 u32 ris0 = ravb_read(ndev, RIS0);
1120 u32 ric0 = ravb_read(ndev, RIC0);
1121 u32 tis = ravb_read(ndev, TIS);
1122 u32 tic = ravb_read(ndev, TIC);
1124 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) {
1125 if (napi_schedule_prep(&priv->napi[q])) {
1126 /* Mask RX and TX interrupts */
1127 if (!info->irq_en_dis) {
1128 ravb_write(ndev, ric0 & ~BIT(q), RIC0);
1129 ravb_write(ndev, tic & ~BIT(q), TIC);
1131 ravb_write(ndev, BIT(q), RID0);
1132 ravb_write(ndev, BIT(q), TID);
1134 __napi_schedule(&priv->napi[q]);
1137 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
1140 " tx status 0x%08x, tx mask 0x%08x.\n",
1148 static bool ravb_timestamp_interrupt(struct net_device *ndev)
1150 u32 tis = ravb_read(ndev, TIS);
1152 if (tis & TIS_TFUF) {
1153 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS);
1154 ravb_get_tx_tstamp(ndev);
1160 static irqreturn_t ravb_interrupt(int irq, void *dev_id)
1162 struct net_device *ndev = dev_id;
1163 struct ravb_private *priv = netdev_priv(ndev);
1164 const struct ravb_hw_info *info = priv->info;
1165 irqreturn_t result = IRQ_NONE;
1168 spin_lock(&priv->lock);
1169 /* Get interrupt status */
1170 iss = ravb_read(ndev, ISS);
1172 /* Received and transmitted interrupts */
1173 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
1176 /* Timestamp updated */
1177 if (ravb_timestamp_interrupt(ndev))
1178 result = IRQ_HANDLED;
1180 /* Network control and best effort queue RX/TX */
1181 if (info->nc_queues) {
1182 for (q = RAVB_NC; q >= RAVB_BE; q--) {
1183 if (ravb_queue_interrupt(ndev, q))
1184 result = IRQ_HANDLED;
1187 if (ravb_queue_interrupt(ndev, RAVB_BE))
1188 result = IRQ_HANDLED;
1192 /* E-MAC status summary */
1194 ravb_emac_interrupt_unlocked(ndev);
1195 result = IRQ_HANDLED;
1198 /* Error status summary */
1200 ravb_error_interrupt(ndev);
1201 result = IRQ_HANDLED;
1204 /* gPTP interrupt status summary */
1205 if (iss & ISS_CGIS) {
1206 ravb_ptp_interrupt(ndev);
1207 result = IRQ_HANDLED;
1210 spin_unlock(&priv->lock);
1214 /* Timestamp/Error/gPTP interrupt handler */
1215 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
1217 struct net_device *ndev = dev_id;
1218 struct ravb_private *priv = netdev_priv(ndev);
1219 irqreturn_t result = IRQ_NONE;
1222 spin_lock(&priv->lock);
1223 /* Get interrupt status */
1224 iss = ravb_read(ndev, ISS);
1226 /* Timestamp updated */
1227 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
1228 result = IRQ_HANDLED;
1230 /* Error status summary */
1232 ravb_error_interrupt(ndev);
1233 result = IRQ_HANDLED;
1236 /* gPTP interrupt status summary */
1237 if (iss & ISS_CGIS) {
1238 ravb_ptp_interrupt(ndev);
1239 result = IRQ_HANDLED;
1242 spin_unlock(&priv->lock);
1246 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
1248 struct net_device *ndev = dev_id;
1249 struct ravb_private *priv = netdev_priv(ndev);
1250 irqreturn_t result = IRQ_NONE;
1252 spin_lock(&priv->lock);
1254 /* Network control/Best effort queue RX/TX */
1255 if (ravb_queue_interrupt(ndev, q))
1256 result = IRQ_HANDLED;
1258 spin_unlock(&priv->lock);
1262 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
1264 return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
1267 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
1269 return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
1272 static int ravb_poll(struct napi_struct *napi, int budget)
1274 struct net_device *ndev = napi->dev;
1275 struct ravb_private *priv = netdev_priv(ndev);
1276 const struct ravb_hw_info *info = priv->info;
1277 bool gptp = info->gptp || info->ccc_gac;
1278 struct ravb_rx_desc *desc;
1279 unsigned long flags;
1280 int q = napi - priv->napi;
1286 entry = priv->cur_rx[q] % priv->num_rx_ring[q];
1287 desc = &priv->gbeth_rx_ring[entry];
1289 /* Processing RX Descriptor Ring */
1290 /* Clear RX interrupt */
1291 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0);
1292 if (gptp || desc->die_dt != DT_FEMPTY) {
1293 if (ravb_rx(ndev, "a, q))
1297 /* Processing TX Descriptor Ring */
1298 spin_lock_irqsave(&priv->lock, flags);
1299 /* Clear TX interrupt */
1300 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS);
1301 ravb_tx_free(ndev, q, true);
1302 netif_wake_subqueue(ndev, q);
1303 spin_unlock_irqrestore(&priv->lock, flags);
1305 napi_complete(napi);
1307 /* Re-enable RX/TX interrupts */
1308 spin_lock_irqsave(&priv->lock, flags);
1309 if (!info->irq_en_dis) {
1310 ravb_modify(ndev, RIC0, mask, mask);
1311 ravb_modify(ndev, TIC, mask, mask);
1313 ravb_write(ndev, mask, RIE0);
1314 ravb_write(ndev, mask, TIE);
1316 spin_unlock_irqrestore(&priv->lock, flags);
1318 /* Receive error message handling */
1319 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
1320 if (info->nc_queues)
1321 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
1322 if (priv->rx_over_errors != ndev->stats.rx_over_errors)
1323 ndev->stats.rx_over_errors = priv->rx_over_errors;
1324 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
1325 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
1327 return budget - quota;
1330 static void ravb_set_duplex_gbeth(struct net_device *ndev)
1332 struct ravb_private *priv = netdev_priv(ndev);
1334 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0);
1337 /* PHY state control function */
1338 static void ravb_adjust_link(struct net_device *ndev)
1340 struct ravb_private *priv = netdev_priv(ndev);
1341 const struct ravb_hw_info *info = priv->info;
1342 struct phy_device *phydev = ndev->phydev;
1343 bool new_state = false;
1344 unsigned long flags;
1346 spin_lock_irqsave(&priv->lock, flags);
1348 /* Disable TX and RX right over here, if E-MAC change is ignored */
1349 if (priv->no_avb_link)
1350 ravb_rcv_snd_disable(ndev);
1353 if (info->half_duplex && phydev->duplex != priv->duplex) {
1355 priv->duplex = phydev->duplex;
1356 ravb_set_duplex_gbeth(ndev);
1359 if (phydev->speed != priv->speed) {
1361 priv->speed = phydev->speed;
1362 info->set_rate(ndev);
1365 ravb_modify(ndev, ECMR, ECMR_TXF, 0);
1367 priv->link = phydev->link;
1369 } else if (priv->link) {
1373 if (info->half_duplex)
1377 /* Enable TX and RX right over here, if E-MAC change is ignored */
1378 if (priv->no_avb_link && phydev->link)
1379 ravb_rcv_snd_enable(ndev);
1381 spin_unlock_irqrestore(&priv->lock, flags);
1383 if (new_state && netif_msg_link(priv))
1384 phy_print_status(phydev);
1387 static const struct soc_device_attribute r8a7795es10[] = {
1388 { .soc_id = "r8a7795", .revision = "ES1.0", },
1392 /* PHY init function */
1393 static int ravb_phy_init(struct net_device *ndev)
1395 struct device_node *np = ndev->dev.parent->of_node;
1396 struct ravb_private *priv = netdev_priv(ndev);
1397 const struct ravb_hw_info *info = priv->info;
1398 struct phy_device *phydev;
1399 struct device_node *pn;
1400 phy_interface_t iface;
1407 /* Try connecting to PHY */
1408 pn = of_parse_phandle(np, "phy-handle", 0);
1410 /* In the case of a fixed PHY, the DT node associated
1411 * to the PHY is the Ethernet MAC DT node.
1413 if (of_phy_is_fixed_link(np)) {
1414 err = of_phy_register_fixed_link(np);
1418 pn = of_node_get(np);
1421 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII
1422 : priv->phy_interface;
1423 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface);
1426 netdev_err(ndev, "failed to connect PHY\n");
1428 goto err_deregister_fixed_link;
1431 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0
1434 if (soc_device_match(r8a7795es10)) {
1435 phy_set_max_speed(phydev, SPEED_100);
1437 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
1440 if (!info->half_duplex) {
1441 /* 10BASE, Pause and Asym Pause is not supported */
1442 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
1443 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT);
1444 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT);
1445 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT);
1447 /* Half Duplex is not supported */
1448 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1449 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
1452 /* Indicate that the MAC is responsible for managing PHY PM */
1453 phydev->mac_managed_pm = true;
1454 phy_attached_info(phydev);
1458 err_deregister_fixed_link:
1459 if (of_phy_is_fixed_link(np))
1460 of_phy_deregister_fixed_link(np);
1465 /* PHY control start function */
1466 static int ravb_phy_start(struct net_device *ndev)
1470 error = ravb_phy_init(ndev);
1474 phy_start(ndev->phydev);
1479 static u32 ravb_get_msglevel(struct net_device *ndev)
1481 struct ravb_private *priv = netdev_priv(ndev);
1483 return priv->msg_enable;
1486 static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1488 struct ravb_private *priv = netdev_priv(ndev);
1490 priv->msg_enable = value;
1493 static const char ravb_gstrings_stats_gbeth[][ETH_GSTRING_LEN] = {
1494 "rx_queue_0_current",
1495 "tx_queue_0_current",
1498 "rx_queue_0_packets",
1499 "tx_queue_0_packets",
1502 "rx_queue_0_mcast_packets",
1503 "rx_queue_0_errors",
1504 "rx_queue_0_crc_errors",
1505 "rx_queue_0_frame_errors",
1506 "rx_queue_0_length_errors",
1507 "rx_queue_0_csum_offload_errors",
1508 "rx_queue_0_over_errors",
1511 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1512 "rx_queue_0_current",
1513 "tx_queue_0_current",
1516 "rx_queue_0_packets",
1517 "tx_queue_0_packets",
1520 "rx_queue_0_mcast_packets",
1521 "rx_queue_0_errors",
1522 "rx_queue_0_crc_errors",
1523 "rx_queue_0_frame_errors",
1524 "rx_queue_0_length_errors",
1525 "rx_queue_0_missed_errors",
1526 "rx_queue_0_over_errors",
1528 "rx_queue_1_current",
1529 "tx_queue_1_current",
1532 "rx_queue_1_packets",
1533 "tx_queue_1_packets",
1536 "rx_queue_1_mcast_packets",
1537 "rx_queue_1_errors",
1538 "rx_queue_1_crc_errors",
1539 "rx_queue_1_frame_errors",
1540 "rx_queue_1_length_errors",
1541 "rx_queue_1_missed_errors",
1542 "rx_queue_1_over_errors",
1545 static int ravb_get_sset_count(struct net_device *netdev, int sset)
1547 struct ravb_private *priv = netdev_priv(netdev);
1548 const struct ravb_hw_info *info = priv->info;
1552 return info->stats_len;
1558 static void ravb_get_ethtool_stats(struct net_device *ndev,
1559 struct ethtool_stats *estats, u64 *data)
1561 struct ravb_private *priv = netdev_priv(ndev);
1562 const struct ravb_hw_info *info = priv->info;
1567 num_rx_q = info->nc_queues ? NUM_RX_QUEUE : 1;
1568 /* Device-specific stats */
1569 for (q = RAVB_BE; q < num_rx_q; q++) {
1570 struct net_device_stats *stats = &priv->stats[q];
1572 data[i++] = priv->cur_rx[q];
1573 data[i++] = priv->cur_tx[q];
1574 data[i++] = priv->dirty_rx[q];
1575 data[i++] = priv->dirty_tx[q];
1576 data[i++] = stats->rx_packets;
1577 data[i++] = stats->tx_packets;
1578 data[i++] = stats->rx_bytes;
1579 data[i++] = stats->tx_bytes;
1580 data[i++] = stats->multicast;
1581 data[i++] = stats->rx_errors;
1582 data[i++] = stats->rx_crc_errors;
1583 data[i++] = stats->rx_frame_errors;
1584 data[i++] = stats->rx_length_errors;
1585 data[i++] = stats->rx_missed_errors;
1586 data[i++] = stats->rx_over_errors;
1590 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1592 struct ravb_private *priv = netdev_priv(ndev);
1593 const struct ravb_hw_info *info = priv->info;
1595 switch (stringset) {
1597 memcpy(data, info->gstrings_stats, info->gstrings_size);
1602 static void ravb_get_ringparam(struct net_device *ndev,
1603 struct ethtool_ringparam *ring,
1604 struct kernel_ethtool_ringparam *kernel_ring,
1605 struct netlink_ext_ack *extack)
1607 struct ravb_private *priv = netdev_priv(ndev);
1609 ring->rx_max_pending = BE_RX_RING_MAX;
1610 ring->tx_max_pending = BE_TX_RING_MAX;
1611 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1612 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1615 static int ravb_set_ringparam(struct net_device *ndev,
1616 struct ethtool_ringparam *ring,
1617 struct kernel_ethtool_ringparam *kernel_ring,
1618 struct netlink_ext_ack *extack)
1620 struct ravb_private *priv = netdev_priv(ndev);
1621 const struct ravb_hw_info *info = priv->info;
1624 if (ring->tx_pending > BE_TX_RING_MAX ||
1625 ring->rx_pending > BE_RX_RING_MAX ||
1626 ring->tx_pending < BE_TX_RING_MIN ||
1627 ring->rx_pending < BE_RX_RING_MIN)
1629 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1632 if (netif_running(ndev)) {
1633 netif_device_detach(ndev);
1634 /* Stop PTP Clock driver */
1636 ravb_ptp_stop(ndev);
1637 /* Wait for DMA stopping */
1638 error = ravb_stop_dma(ndev);
1641 "cannot set ringparam! Any AVB processes are still running?\n");
1644 synchronize_irq(ndev->irq);
1646 /* Free all the skb's in the RX queue and the DMA buffers. */
1647 ravb_ring_free(ndev, RAVB_BE);
1648 if (info->nc_queues)
1649 ravb_ring_free(ndev, RAVB_NC);
1652 /* Set new parameters */
1653 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1654 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1656 if (netif_running(ndev)) {
1657 error = ravb_dmac_init(ndev);
1660 "%s: ravb_dmac_init() failed, error %d\n",
1665 ravb_emac_init(ndev);
1667 /* Initialise PTP Clock driver */
1669 ravb_ptp_init(ndev, priv->pdev);
1671 netif_device_attach(ndev);
1677 static int ravb_get_ts_info(struct net_device *ndev,
1678 struct ethtool_ts_info *info)
1680 struct ravb_private *priv = netdev_priv(ndev);
1681 const struct ravb_hw_info *hw_info = priv->info;
1683 info->so_timestamping =
1684 SOF_TIMESTAMPING_TX_SOFTWARE |
1685 SOF_TIMESTAMPING_RX_SOFTWARE |
1686 SOF_TIMESTAMPING_SOFTWARE |
1687 SOF_TIMESTAMPING_TX_HARDWARE |
1688 SOF_TIMESTAMPING_RX_HARDWARE |
1689 SOF_TIMESTAMPING_RAW_HARDWARE;
1690 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1692 (1 << HWTSTAMP_FILTER_NONE) |
1693 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1694 (1 << HWTSTAMP_FILTER_ALL);
1695 if (hw_info->gptp || hw_info->ccc_gac)
1696 info->phc_index = ptp_clock_index(priv->ptp.clock);
1701 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1703 struct ravb_private *priv = netdev_priv(ndev);
1705 wol->supported = WAKE_MAGIC;
1706 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0;
1709 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1711 struct ravb_private *priv = netdev_priv(ndev);
1712 const struct ravb_hw_info *info = priv->info;
1714 if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC))
1717 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
1719 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled);
1724 static const struct ethtool_ops ravb_ethtool_ops = {
1725 .nway_reset = phy_ethtool_nway_reset,
1726 .get_msglevel = ravb_get_msglevel,
1727 .set_msglevel = ravb_set_msglevel,
1728 .get_link = ethtool_op_get_link,
1729 .get_strings = ravb_get_strings,
1730 .get_ethtool_stats = ravb_get_ethtool_stats,
1731 .get_sset_count = ravb_get_sset_count,
1732 .get_ringparam = ravb_get_ringparam,
1733 .set_ringparam = ravb_set_ringparam,
1734 .get_ts_info = ravb_get_ts_info,
1735 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1736 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1737 .get_wol = ravb_get_wol,
1738 .set_wol = ravb_set_wol,
1741 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1742 struct net_device *ndev, struct device *dev,
1748 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1751 error = request_irq(irq, handler, 0, name, ndev);
1753 netdev_err(ndev, "cannot request IRQ %s\n", name);
1758 /* Network device open function for Ethernet AVB */
1759 static int ravb_open(struct net_device *ndev)
1761 struct ravb_private *priv = netdev_priv(ndev);
1762 const struct ravb_hw_info *info = priv->info;
1763 struct platform_device *pdev = priv->pdev;
1764 struct device *dev = &pdev->dev;
1767 napi_enable(&priv->napi[RAVB_BE]);
1768 if (info->nc_queues)
1769 napi_enable(&priv->napi[RAVB_NC]);
1771 if (!info->multi_irqs) {
1772 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1775 netdev_err(ndev, "cannot request IRQ\n");
1779 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1783 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1787 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1788 ndev, dev, "ch0:rx_be");
1790 goto out_free_irq_emac;
1791 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1792 ndev, dev, "ch18:tx_be");
1794 goto out_free_irq_be_rx;
1795 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1796 ndev, dev, "ch1:rx_nc");
1798 goto out_free_irq_be_tx;
1799 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1800 ndev, dev, "ch19:tx_nc");
1802 goto out_free_irq_nc_rx;
1804 if (info->err_mgmt_irqs) {
1805 error = ravb_hook_irq(priv->erra_irq, ravb_multi_interrupt,
1806 ndev, dev, "err_a");
1808 goto out_free_irq_nc_tx;
1809 error = ravb_hook_irq(priv->mgmta_irq, ravb_multi_interrupt,
1810 ndev, dev, "mgmt_a");
1812 goto out_free_irq_erra;
1817 error = ravb_dmac_init(ndev);
1819 goto out_free_irq_mgmta;
1820 ravb_emac_init(ndev);
1822 /* Initialise PTP Clock driver */
1824 ravb_ptp_init(ndev, priv->pdev);
1826 netif_tx_start_all_queues(ndev);
1828 /* PHY control start */
1829 error = ravb_phy_start(ndev);
1836 /* Stop PTP Clock driver */
1838 ravb_ptp_stop(ndev);
1840 if (!info->multi_irqs)
1842 if (info->err_mgmt_irqs)
1843 free_irq(priv->mgmta_irq, ndev);
1845 if (info->err_mgmt_irqs)
1846 free_irq(priv->erra_irq, ndev);
1848 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1850 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1852 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1854 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1856 free_irq(priv->emac_irq, ndev);
1858 free_irq(ndev->irq, ndev);
1860 if (info->nc_queues)
1861 napi_disable(&priv->napi[RAVB_NC]);
1862 napi_disable(&priv->napi[RAVB_BE]);
1866 /* Timeout function for Ethernet AVB */
1867 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1869 struct ravb_private *priv = netdev_priv(ndev);
1871 netif_err(priv, tx_err, ndev,
1872 "transmit timed out, status %08x, resetting...\n",
1873 ravb_read(ndev, ISS));
1875 /* tx_errors count up */
1876 ndev->stats.tx_errors++;
1878 schedule_work(&priv->work);
1881 static void ravb_tx_timeout_work(struct work_struct *work)
1883 struct ravb_private *priv = container_of(work, struct ravb_private,
1885 const struct ravb_hw_info *info = priv->info;
1886 struct net_device *ndev = priv->ndev;
1889 netif_tx_stop_all_queues(ndev);
1891 /* Stop PTP Clock driver */
1893 ravb_ptp_stop(ndev);
1895 /* Wait for DMA stopping */
1896 if (ravb_stop_dma(ndev)) {
1897 /* If ravb_stop_dma() fails, the hardware is still operating
1898 * for TX and/or RX. So, this should not call the following
1899 * functions because ravb_dmac_init() is possible to fail too.
1900 * Also, this should not retry ravb_stop_dma() again and again
1901 * here because it's possible to wait forever. So, this just
1902 * re-enables the TX and RX and skip the following
1903 * re-initialization procedure.
1905 ravb_rcv_snd_enable(ndev);
1909 ravb_ring_free(ndev, RAVB_BE);
1910 if (info->nc_queues)
1911 ravb_ring_free(ndev, RAVB_NC);
1914 error = ravb_dmac_init(ndev);
1916 /* If ravb_dmac_init() fails, descriptors are freed. So, this
1917 * should return here to avoid re-enabling the TX and RX in
1920 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n",
1924 ravb_emac_init(ndev);
1927 /* Initialise PTP Clock driver */
1929 ravb_ptp_init(ndev, priv->pdev);
1931 netif_tx_start_all_queues(ndev);
1934 /* Packet transmit function for Ethernet AVB */
1935 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1937 struct ravb_private *priv = netdev_priv(ndev);
1938 const struct ravb_hw_info *info = priv->info;
1939 unsigned int num_tx_desc = priv->num_tx_desc;
1940 u16 q = skb_get_queue_mapping(skb);
1941 struct ravb_tstamp_skb *ts_skb;
1942 struct ravb_tx_desc *desc;
1943 unsigned long flags;
1949 spin_lock_irqsave(&priv->lock, flags);
1950 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1952 netif_err(priv, tx_queued, ndev,
1953 "still transmitting with the full ring!\n");
1954 netif_stop_subqueue(ndev, q);
1955 spin_unlock_irqrestore(&priv->lock, flags);
1956 return NETDEV_TX_BUSY;
1959 if (skb_put_padto(skb, ETH_ZLEN))
1962 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc);
1963 priv->tx_skb[q][entry / num_tx_desc] = skb;
1965 if (num_tx_desc > 1) {
1966 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1967 entry / num_tx_desc * DPTR_ALIGN;
1968 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1970 /* Zero length DMA descriptors are problematic as they seem
1971 * to terminate DMA transfers. Avoid them by simply using a
1972 * length of DPTR_ALIGN (4) when skb data is aligned to
1975 * As skb is guaranteed to have at least ETH_ZLEN (60)
1976 * bytes of data by the call to skb_put_padto() above this
1977 * is safe with respect to both the length of the first DMA
1978 * descriptor (len) overflowing the available data and the
1979 * length of the second DMA descriptor (skb->len - len)
1985 memcpy(buffer, skb->data, len);
1986 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
1988 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1991 desc = &priv->tx_ring[q][entry];
1992 desc->ds_tagl = cpu_to_le16(len);
1993 desc->dptr = cpu_to_le32(dma_addr);
1995 buffer = skb->data + len;
1996 len = skb->len - len;
1997 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
1999 if (dma_mapping_error(ndev->dev.parent, dma_addr))
2004 desc = &priv->tx_ring[q][entry];
2006 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len,
2008 if (dma_mapping_error(ndev->dev.parent, dma_addr))
2011 desc->ds_tagl = cpu_to_le16(len);
2012 desc->dptr = cpu_to_le32(dma_addr);
2014 /* TX timestamp required */
2015 if (info->gptp || info->ccc_gac) {
2017 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
2019 if (num_tx_desc > 1) {
2021 dma_unmap_single(ndev->dev.parent, dma_addr,
2022 len, DMA_TO_DEVICE);
2026 ts_skb->skb = skb_get(skb);
2027 ts_skb->tag = priv->ts_skb_tag++;
2028 priv->ts_skb_tag &= 0x3ff;
2029 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
2031 /* TAG and timestamp required flag */
2032 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2033 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
2034 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12);
2037 skb_tx_timestamp(skb);
2039 /* Descriptor type must be set after all the above writes */
2041 if (num_tx_desc > 1) {
2042 desc->die_dt = DT_FEND;
2044 desc->die_dt = DT_FSTART;
2046 desc->die_dt = DT_FSINGLE;
2048 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
2050 priv->cur_tx[q] += num_tx_desc;
2051 if (priv->cur_tx[q] - priv->dirty_tx[q] >
2052 (priv->num_tx_ring[q] - 1) * num_tx_desc &&
2053 !ravb_tx_free(ndev, q, true))
2054 netif_stop_subqueue(ndev, q);
2057 spin_unlock_irqrestore(&priv->lock, flags);
2058 return NETDEV_TX_OK;
2061 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
2062 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
2064 dev_kfree_skb_any(skb);
2065 priv->tx_skb[q][entry / num_tx_desc] = NULL;
2069 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
2070 struct net_device *sb_dev)
2072 /* If skb needs TX timestamp, it is handled in network control queue */
2073 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
2078 static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
2080 struct ravb_private *priv = netdev_priv(ndev);
2081 const struct ravb_hw_info *info = priv->info;
2082 struct net_device_stats *nstats, *stats0, *stats1;
2084 nstats = &ndev->stats;
2085 stats0 = &priv->stats[RAVB_BE];
2087 if (info->tx_counters) {
2088 nstats->tx_dropped += ravb_read(ndev, TROCR);
2089 ravb_write(ndev, 0, TROCR); /* (write clear) */
2092 if (info->carrier_counters) {
2093 nstats->collisions += ravb_read(ndev, CXR41);
2094 ravb_write(ndev, 0, CXR41); /* (write clear) */
2095 nstats->tx_carrier_errors += ravb_read(ndev, CXR42);
2096 ravb_write(ndev, 0, CXR42); /* (write clear) */
2099 nstats->rx_packets = stats0->rx_packets;
2100 nstats->tx_packets = stats0->tx_packets;
2101 nstats->rx_bytes = stats0->rx_bytes;
2102 nstats->tx_bytes = stats0->tx_bytes;
2103 nstats->multicast = stats0->multicast;
2104 nstats->rx_errors = stats0->rx_errors;
2105 nstats->rx_crc_errors = stats0->rx_crc_errors;
2106 nstats->rx_frame_errors = stats0->rx_frame_errors;
2107 nstats->rx_length_errors = stats0->rx_length_errors;
2108 nstats->rx_missed_errors = stats0->rx_missed_errors;
2109 nstats->rx_over_errors = stats0->rx_over_errors;
2110 if (info->nc_queues) {
2111 stats1 = &priv->stats[RAVB_NC];
2113 nstats->rx_packets += stats1->rx_packets;
2114 nstats->tx_packets += stats1->tx_packets;
2115 nstats->rx_bytes += stats1->rx_bytes;
2116 nstats->tx_bytes += stats1->tx_bytes;
2117 nstats->multicast += stats1->multicast;
2118 nstats->rx_errors += stats1->rx_errors;
2119 nstats->rx_crc_errors += stats1->rx_crc_errors;
2120 nstats->rx_frame_errors += stats1->rx_frame_errors;
2121 nstats->rx_length_errors += stats1->rx_length_errors;
2122 nstats->rx_missed_errors += stats1->rx_missed_errors;
2123 nstats->rx_over_errors += stats1->rx_over_errors;
2129 /* Update promiscuous bit */
2130 static void ravb_set_rx_mode(struct net_device *ndev)
2132 struct ravb_private *priv = netdev_priv(ndev);
2133 unsigned long flags;
2135 spin_lock_irqsave(&priv->lock, flags);
2136 ravb_modify(ndev, ECMR, ECMR_PRM,
2137 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
2138 spin_unlock_irqrestore(&priv->lock, flags);
2141 /* Device close function for Ethernet AVB */
2142 static int ravb_close(struct net_device *ndev)
2144 struct device_node *np = ndev->dev.parent->of_node;
2145 struct ravb_private *priv = netdev_priv(ndev);
2146 const struct ravb_hw_info *info = priv->info;
2147 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
2149 netif_tx_stop_all_queues(ndev);
2151 /* Disable interrupts by clearing the interrupt masks. */
2152 ravb_write(ndev, 0, RIC0);
2153 ravb_write(ndev, 0, RIC2);
2154 ravb_write(ndev, 0, TIC);
2156 /* Stop PTP Clock driver */
2158 ravb_ptp_stop(ndev);
2160 /* Set the config mode to stop the AVB-DMAC's processes */
2161 if (ravb_stop_dma(ndev) < 0)
2163 "device will be stopped after h/w processes are done.\n");
2165 /* Clear the timestamp list */
2166 if (info->gptp || info->ccc_gac) {
2167 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
2168 list_del(&ts_skb->list);
2169 kfree_skb(ts_skb->skb);
2174 /* PHY disconnect */
2176 phy_stop(ndev->phydev);
2177 phy_disconnect(ndev->phydev);
2178 if (of_phy_is_fixed_link(np))
2179 of_phy_deregister_fixed_link(np);
2182 if (info->multi_irqs) {
2183 free_irq(priv->tx_irqs[RAVB_NC], ndev);
2184 free_irq(priv->rx_irqs[RAVB_NC], ndev);
2185 free_irq(priv->tx_irqs[RAVB_BE], ndev);
2186 free_irq(priv->rx_irqs[RAVB_BE], ndev);
2187 free_irq(priv->emac_irq, ndev);
2188 if (info->err_mgmt_irqs) {
2189 free_irq(priv->erra_irq, ndev);
2190 free_irq(priv->mgmta_irq, ndev);
2193 free_irq(ndev->irq, ndev);
2195 if (info->nc_queues)
2196 napi_disable(&priv->napi[RAVB_NC]);
2197 napi_disable(&priv->napi[RAVB_BE]);
2199 /* Free all the skb's in the RX queue and the DMA buffers. */
2200 ravb_ring_free(ndev, RAVB_BE);
2201 if (info->nc_queues)
2202 ravb_ring_free(ndev, RAVB_NC);
2207 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
2209 struct ravb_private *priv = netdev_priv(ndev);
2210 struct hwtstamp_config config;
2213 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
2215 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) {
2216 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT:
2217 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
2219 case RAVB_RXTSTAMP_TYPE_ALL:
2220 config.rx_filter = HWTSTAMP_FILTER_ALL;
2223 config.rx_filter = HWTSTAMP_FILTER_NONE;
2226 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
2230 /* Control hardware time stamping */
2231 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
2233 struct ravb_private *priv = netdev_priv(ndev);
2234 struct hwtstamp_config config;
2235 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
2238 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
2241 switch (config.tx_type) {
2242 case HWTSTAMP_TX_OFF:
2245 case HWTSTAMP_TX_ON:
2246 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
2252 switch (config.rx_filter) {
2253 case HWTSTAMP_FILTER_NONE:
2256 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2257 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
2260 config.rx_filter = HWTSTAMP_FILTER_ALL;
2261 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
2264 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
2265 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
2267 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
2271 /* ioctl to device function */
2272 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
2274 struct phy_device *phydev = ndev->phydev;
2276 if (!netif_running(ndev))
2284 return ravb_hwtstamp_get(ndev, req);
2286 return ravb_hwtstamp_set(ndev, req);
2289 return phy_mii_ioctl(phydev, req, cmd);
2292 static int ravb_change_mtu(struct net_device *ndev, int new_mtu)
2294 struct ravb_private *priv = netdev_priv(ndev);
2296 ndev->mtu = new_mtu;
2298 if (netif_running(ndev)) {
2299 synchronize_irq(priv->emac_irq);
2300 ravb_emac_init(ndev);
2303 netdev_update_features(ndev);
2308 static void ravb_set_rx_csum(struct net_device *ndev, bool enable)
2310 struct ravb_private *priv = netdev_priv(ndev);
2311 unsigned long flags;
2313 spin_lock_irqsave(&priv->lock, flags);
2315 /* Disable TX and RX */
2316 ravb_rcv_snd_disable(ndev);
2318 /* Modify RX Checksum setting */
2319 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
2321 /* Enable TX and RX */
2322 ravb_rcv_snd_enable(ndev);
2324 spin_unlock_irqrestore(&priv->lock, flags);
2327 static int ravb_set_features_gbeth(struct net_device *ndev,
2328 netdev_features_t features)
2334 static int ravb_set_features_rcar(struct net_device *ndev,
2335 netdev_features_t features)
2337 netdev_features_t changed = ndev->features ^ features;
2339 if (changed & NETIF_F_RXCSUM)
2340 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
2342 ndev->features = features;
2347 static int ravb_set_features(struct net_device *ndev,
2348 netdev_features_t features)
2350 struct ravb_private *priv = netdev_priv(ndev);
2351 const struct ravb_hw_info *info = priv->info;
2353 return info->set_feature(ndev, features);
2356 static const struct net_device_ops ravb_netdev_ops = {
2357 .ndo_open = ravb_open,
2358 .ndo_stop = ravb_close,
2359 .ndo_start_xmit = ravb_start_xmit,
2360 .ndo_select_queue = ravb_select_queue,
2361 .ndo_get_stats = ravb_get_stats,
2362 .ndo_set_rx_mode = ravb_set_rx_mode,
2363 .ndo_tx_timeout = ravb_tx_timeout,
2364 .ndo_eth_ioctl = ravb_do_ioctl,
2365 .ndo_change_mtu = ravb_change_mtu,
2366 .ndo_validate_addr = eth_validate_addr,
2367 .ndo_set_mac_address = eth_mac_addr,
2368 .ndo_set_features = ravb_set_features,
2371 /* MDIO bus init function */
2372 static int ravb_mdio_init(struct ravb_private *priv)
2374 struct platform_device *pdev = priv->pdev;
2375 struct device *dev = &pdev->dev;
2379 priv->mdiobb.ops = &bb_ops;
2381 /* MII controller setting */
2382 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
2386 /* Hook up MII support for ethtool */
2387 priv->mii_bus->name = "ravb_mii";
2388 priv->mii_bus->parent = dev;
2389 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2390 pdev->name, pdev->id);
2392 /* Register MDIO bus */
2393 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
2400 free_mdio_bitbang(priv->mii_bus);
2404 /* MDIO bus release function */
2405 static int ravb_mdio_release(struct ravb_private *priv)
2407 /* Unregister mdio bus */
2408 mdiobus_unregister(priv->mii_bus);
2410 /* Free bitbang info */
2411 free_mdio_bitbang(priv->mii_bus);
2416 static const struct ravb_hw_info ravb_gen3_hw_info = {
2417 .rx_ring_free = ravb_rx_ring_free_rcar,
2418 .rx_ring_format = ravb_rx_ring_format_rcar,
2419 .alloc_rx_desc = ravb_alloc_rx_desc_rcar,
2420 .receive = ravb_rx_rcar,
2421 .set_rate = ravb_set_rate_rcar,
2422 .set_feature = ravb_set_features_rcar,
2423 .dmac_init = ravb_dmac_init_rcar,
2424 .emac_init = ravb_emac_init_rcar,
2425 .gstrings_stats = ravb_gstrings_stats,
2426 .gstrings_size = sizeof(ravb_gstrings_stats),
2427 .net_hw_features = NETIF_F_RXCSUM,
2428 .net_features = NETIF_F_RXCSUM,
2429 .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
2430 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
2431 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
2432 .rx_max_buf_size = SZ_2K,
2433 .internal_delay = 1,
2442 static const struct ravb_hw_info ravb_gen2_hw_info = {
2443 .rx_ring_free = ravb_rx_ring_free_rcar,
2444 .rx_ring_format = ravb_rx_ring_format_rcar,
2445 .alloc_rx_desc = ravb_alloc_rx_desc_rcar,
2446 .receive = ravb_rx_rcar,
2447 .set_rate = ravb_set_rate_rcar,
2448 .set_feature = ravb_set_features_rcar,
2449 .dmac_init = ravb_dmac_init_rcar,
2450 .emac_init = ravb_emac_init_rcar,
2451 .gstrings_stats = ravb_gstrings_stats,
2452 .gstrings_size = sizeof(ravb_gstrings_stats),
2453 .net_hw_features = NETIF_F_RXCSUM,
2454 .net_features = NETIF_F_RXCSUM,
2455 .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
2456 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
2457 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
2458 .rx_max_buf_size = SZ_2K,
2465 static const struct ravb_hw_info ravb_rzv2m_hw_info = {
2466 .rx_ring_free = ravb_rx_ring_free_rcar,
2467 .rx_ring_format = ravb_rx_ring_format_rcar,
2468 .alloc_rx_desc = ravb_alloc_rx_desc_rcar,
2469 .receive = ravb_rx_rcar,
2470 .set_rate = ravb_set_rate_rcar,
2471 .set_feature = ravb_set_features_rcar,
2472 .dmac_init = ravb_dmac_init_rcar,
2473 .emac_init = ravb_emac_init_rcar,
2474 .gstrings_stats = ravb_gstrings_stats,
2475 .gstrings_size = sizeof(ravb_gstrings_stats),
2476 .net_hw_features = NETIF_F_RXCSUM,
2477 .net_features = NETIF_F_RXCSUM,
2478 .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
2479 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
2480 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
2481 .rx_max_buf_size = SZ_2K,
2490 static const struct ravb_hw_info gbeth_hw_info = {
2491 .rx_ring_free = ravb_rx_ring_free_gbeth,
2492 .rx_ring_format = ravb_rx_ring_format_gbeth,
2493 .alloc_rx_desc = ravb_alloc_rx_desc_gbeth,
2494 .receive = ravb_rx_gbeth,
2495 .set_rate = ravb_set_rate_gbeth,
2496 .set_feature = ravb_set_features_gbeth,
2497 .dmac_init = ravb_dmac_init_gbeth,
2498 .emac_init = ravb_emac_init_gbeth,
2499 .gstrings_stats = ravb_gstrings_stats_gbeth,
2500 .gstrings_size = sizeof(ravb_gstrings_stats_gbeth),
2501 .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth),
2502 .max_rx_len = ALIGN(GBETH_RX_BUFF_MAX, RAVB_ALIGN),
2503 .tccr_mask = TCCR_TSRQ0,
2504 .rx_max_buf_size = SZ_8K,
2507 .carrier_counters = 1,
2511 static const struct of_device_id ravb_match_table[] = {
2512 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info },
2513 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info },
2514 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info },
2515 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info },
2516 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info },
2517 { .compatible = "renesas,etheravb-rzv2m", .data = &ravb_rzv2m_hw_info },
2518 { .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info },
2521 MODULE_DEVICE_TABLE(of, ravb_match_table);
2523 static int ravb_set_gti(struct net_device *ndev)
2525 struct ravb_private *priv = netdev_priv(ndev);
2526 const struct ravb_hw_info *info = priv->info;
2527 struct device *dev = ndev->dev.parent;
2531 if (info->gptp_ref_clk)
2532 rate = clk_get_rate(priv->gptp_clk);
2534 rate = clk_get_rate(priv->clk);
2538 inc = div64_ul(1000000000ULL << 20, rate);
2540 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
2541 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
2542 inc, GTI_TIV_MIN, GTI_TIV_MAX);
2546 ravb_write(ndev, inc, GTI);
2551 static void ravb_set_config_mode(struct net_device *ndev)
2553 struct ravb_private *priv = netdev_priv(ndev);
2554 const struct ravb_hw_info *info = priv->info;
2557 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
2558 /* Set CSEL value */
2559 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
2560 } else if (info->ccc_gac) {
2561 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
2562 CCC_GAC | CCC_CSEL_HPB);
2564 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
2568 /* Set tx and rx clock internal delay modes */
2569 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev)
2571 struct ravb_private *priv = netdev_priv(ndev);
2572 bool explicit_delay = false;
2575 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) {
2576 /* Valid values are 0 and 1800, according to DT bindings */
2577 priv->rxcidm = !!delay;
2578 explicit_delay = true;
2580 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) {
2581 /* Valid values are 0 and 2000, according to DT bindings */
2582 priv->txcidm = !!delay;
2583 explicit_delay = true;
2589 /* Fall back to legacy rgmii-*id behavior */
2590 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
2591 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) {
2593 priv->rgmii_override = 1;
2596 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
2597 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
2599 priv->rgmii_override = 1;
2603 static void ravb_set_delay_mode(struct net_device *ndev)
2605 struct ravb_private *priv = netdev_priv(ndev);
2612 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set);
2615 static int ravb_probe(struct platform_device *pdev)
2617 struct device_node *np = pdev->dev.of_node;
2618 const struct ravb_hw_info *info;
2619 struct reset_control *rstc;
2620 struct ravb_private *priv;
2621 struct net_device *ndev;
2623 struct resource *res;
2628 "this driver is required to be instantiated from device tree\n");
2632 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
2634 return dev_err_probe(&pdev->dev, PTR_ERR(rstc),
2635 "failed to get cpg reset\n");
2637 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
2638 NUM_TX_QUEUE, NUM_RX_QUEUE);
2642 info = of_device_get_match_data(&pdev->dev);
2644 ndev->features = info->net_features;
2645 ndev->hw_features = info->net_hw_features;
2647 reset_control_deassert(rstc);
2648 pm_runtime_enable(&pdev->dev);
2649 pm_runtime_get_sync(&pdev->dev);
2651 if (info->multi_irqs) {
2652 if (info->err_mgmt_irqs)
2653 irq = platform_get_irq_byname(pdev, "dia");
2655 irq = platform_get_irq_byname(pdev, "ch22");
2657 irq = platform_get_irq(pdev, 0);
2665 SET_NETDEV_DEV(ndev, &pdev->dev);
2667 priv = netdev_priv(ndev);
2672 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
2673 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
2674 if (info->nc_queues) {
2675 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
2676 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
2679 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2680 if (IS_ERR(priv->addr)) {
2681 error = PTR_ERR(priv->addr);
2685 /* The Ether-specific entries in the device structure. */
2686 ndev->base_addr = res->start;
2688 spin_lock_init(&priv->lock);
2689 INIT_WORK(&priv->work, ravb_tx_timeout_work);
2691 error = of_get_phy_mode(np, &priv->phy_interface);
2692 if (error && error != -ENODEV)
2695 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
2696 priv->avb_link_active_low =
2697 of_property_read_bool(np, "renesas,ether-link-active-low");
2699 if (info->multi_irqs) {
2700 if (info->err_mgmt_irqs)
2701 irq = platform_get_irq_byname(pdev, "line3");
2703 irq = platform_get_irq_byname(pdev, "ch24");
2708 priv->emac_irq = irq;
2709 for (i = 0; i < NUM_RX_QUEUE; i++) {
2710 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
2715 priv->rx_irqs[i] = irq;
2717 for (i = 0; i < NUM_TX_QUEUE; i++) {
2718 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
2723 priv->tx_irqs[i] = irq;
2726 if (info->err_mgmt_irqs) {
2727 irq = platform_get_irq_byname(pdev, "err_a");
2732 priv->erra_irq = irq;
2734 irq = platform_get_irq_byname(pdev, "mgmt_a");
2739 priv->mgmta_irq = irq;
2743 priv->clk = devm_clk_get(&pdev->dev, NULL);
2744 if (IS_ERR(priv->clk)) {
2745 error = PTR_ERR(priv->clk);
2749 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk");
2750 if (IS_ERR(priv->refclk)) {
2751 error = PTR_ERR(priv->refclk);
2754 clk_prepare_enable(priv->refclk);
2756 if (info->gptp_ref_clk) {
2757 priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp");
2758 if (IS_ERR(priv->gptp_clk)) {
2759 error = PTR_ERR(priv->gptp_clk);
2760 goto out_disable_refclk;
2762 clk_prepare_enable(priv->gptp_clk);
2765 ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
2766 ndev->min_mtu = ETH_MIN_MTU;
2768 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer
2769 * Use two descriptor to handle such situation. First descriptor to
2770 * handle aligned data buffer and second descriptor to handle the
2771 * overflow data because of alignment.
2773 priv->num_tx_desc = info->aligned_tx ? 2 : 1;
2776 ndev->netdev_ops = &ravb_netdev_ops;
2777 ndev->ethtool_ops = &ravb_ethtool_ops;
2779 /* Set AVB config mode */
2780 ravb_set_config_mode(ndev);
2782 if (info->gptp || info->ccc_gac) {
2784 error = ravb_set_gti(ndev);
2786 goto out_disable_gptp_clk;
2788 /* Request GTI loading */
2789 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2792 if (info->internal_delay) {
2793 ravb_parse_delay_mode(np, ndev);
2794 ravb_set_delay_mode(ndev);
2797 /* Allocate descriptor base address table */
2798 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
2799 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
2800 &priv->desc_bat_dma, GFP_KERNEL);
2801 if (!priv->desc_bat) {
2803 "Cannot allocate desc base address table (size %d bytes)\n",
2804 priv->desc_bat_size);
2806 goto out_disable_gptp_clk;
2808 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2809 priv->desc_bat[q].die_dt = DT_EOS;
2810 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2812 /* Initialise HW timestamp list */
2813 INIT_LIST_HEAD(&priv->ts_skb_list);
2815 /* Initialise PTP Clock driver */
2817 ravb_ptp_init(ndev, pdev);
2819 /* Debug message level */
2820 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2822 /* Read and set MAC address */
2823 ravb_read_mac_address(np, ndev);
2824 if (!is_valid_ether_addr(ndev->dev_addr)) {
2825 dev_warn(&pdev->dev,
2826 "no valid MAC address supplied, using a random one\n");
2827 eth_hw_addr_random(ndev);
2831 error = ravb_mdio_init(priv);
2833 dev_err(&pdev->dev, "failed to initialize MDIO\n");
2837 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
2838 if (info->nc_queues)
2839 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
2841 /* Network device register */
2842 error = register_netdev(ndev);
2846 device_set_wakeup_capable(&pdev->dev, 1);
2848 /* Print device information */
2849 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2850 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2852 platform_set_drvdata(pdev, ndev);
2857 if (info->nc_queues)
2858 netif_napi_del(&priv->napi[RAVB_NC]);
2860 netif_napi_del(&priv->napi[RAVB_BE]);
2861 ravb_mdio_release(priv);
2863 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2864 priv->desc_bat_dma);
2866 /* Stop PTP Clock driver */
2868 ravb_ptp_stop(ndev);
2869 out_disable_gptp_clk:
2870 clk_disable_unprepare(priv->gptp_clk);
2872 clk_disable_unprepare(priv->refclk);
2876 pm_runtime_put(&pdev->dev);
2877 pm_runtime_disable(&pdev->dev);
2878 reset_control_assert(rstc);
2882 static int ravb_remove(struct platform_device *pdev)
2884 struct net_device *ndev = platform_get_drvdata(pdev);
2885 struct ravb_private *priv = netdev_priv(ndev);
2886 const struct ravb_hw_info *info = priv->info;
2888 /* Stop PTP Clock driver */
2890 ravb_ptp_stop(ndev);
2892 clk_disable_unprepare(priv->gptp_clk);
2893 clk_disable_unprepare(priv->refclk);
2895 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2896 priv->desc_bat_dma);
2897 /* Set reset mode */
2898 ravb_write(ndev, CCC_OPC_RESET, CCC);
2899 pm_runtime_put_sync(&pdev->dev);
2900 unregister_netdev(ndev);
2901 if (info->nc_queues)
2902 netif_napi_del(&priv->napi[RAVB_NC]);
2903 netif_napi_del(&priv->napi[RAVB_BE]);
2904 ravb_mdio_release(priv);
2905 pm_runtime_disable(&pdev->dev);
2906 reset_control_assert(priv->rstc);
2908 platform_set_drvdata(pdev, NULL);
2913 static int ravb_wol_setup(struct net_device *ndev)
2915 struct ravb_private *priv = netdev_priv(ndev);
2916 const struct ravb_hw_info *info = priv->info;
2918 /* Disable interrupts by clearing the interrupt masks. */
2919 ravb_write(ndev, 0, RIC0);
2920 ravb_write(ndev, 0, RIC2);
2921 ravb_write(ndev, 0, TIC);
2923 /* Only allow ECI interrupts */
2924 synchronize_irq(priv->emac_irq);
2925 if (info->nc_queues)
2926 napi_disable(&priv->napi[RAVB_NC]);
2927 napi_disable(&priv->napi[RAVB_BE]);
2928 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR);
2930 /* Enable MagicPacket */
2931 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
2933 return enable_irq_wake(priv->emac_irq);
2936 static int ravb_wol_restore(struct net_device *ndev)
2938 struct ravb_private *priv = netdev_priv(ndev);
2939 const struct ravb_hw_info *info = priv->info;
2941 if (info->nc_queues)
2942 napi_enable(&priv->napi[RAVB_NC]);
2943 napi_enable(&priv->napi[RAVB_BE]);
2945 /* Disable MagicPacket */
2946 ravb_modify(ndev, ECMR, ECMR_MPDE, 0);
2950 return disable_irq_wake(priv->emac_irq);
2953 static int __maybe_unused ravb_suspend(struct device *dev)
2955 struct net_device *ndev = dev_get_drvdata(dev);
2956 struct ravb_private *priv = netdev_priv(ndev);
2959 if (!netif_running(ndev))
2962 netif_device_detach(ndev);
2964 if (priv->wol_enabled)
2965 ret = ravb_wol_setup(ndev);
2967 ret = ravb_close(ndev);
2972 static int __maybe_unused ravb_resume(struct device *dev)
2974 struct net_device *ndev = dev_get_drvdata(dev);
2975 struct ravb_private *priv = netdev_priv(ndev);
2976 const struct ravb_hw_info *info = priv->info;
2979 /* If WoL is enabled set reset mode to rearm the WoL logic */
2980 if (priv->wol_enabled)
2981 ravb_write(ndev, CCC_OPC_RESET, CCC);
2983 /* All register have been reset to default values.
2984 * Restore all registers which where setup at probe time and
2985 * reopen device if it was running before system suspended.
2988 /* Set AVB config mode */
2989 ravb_set_config_mode(ndev);
2991 if (info->gptp || info->ccc_gac) {
2993 ret = ravb_set_gti(ndev);
2997 /* Request GTI loading */
2998 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
3001 if (info->internal_delay)
3002 ravb_set_delay_mode(ndev);
3004 /* Restore descriptor base address table */
3005 ravb_write(ndev, priv->desc_bat_dma, DBAT);
3007 if (netif_running(ndev)) {
3008 if (priv->wol_enabled) {
3009 ret = ravb_wol_restore(ndev);
3013 ret = ravb_open(ndev);
3016 netif_device_attach(ndev);
3022 static int __maybe_unused ravb_runtime_nop(struct device *dev)
3024 /* Runtime PM callback shared between ->runtime_suspend()
3025 * and ->runtime_resume(). Simply returns success.
3027 * This driver re-initializes all registers after
3028 * pm_runtime_get_sync() anyway so there is no need
3029 * to save and restore registers here.
3034 static const struct dev_pm_ops ravb_dev_pm_ops = {
3035 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
3036 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL)
3039 static struct platform_driver ravb_driver = {
3040 .probe = ravb_probe,
3041 .remove = ravb_remove,
3044 .pm = &ravb_dev_pm_ops,
3045 .of_match_table = ravb_match_table,
3049 module_platform_driver(ravb_driver);
3051 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
3052 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
3053 MODULE_LICENSE("GPL v2");