1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/micrel.c
5 * Driver for Micrel PHYs
7 * Author: David J. Choi
9 * Copyright (c) 2010-2013 Micrel, Inc.
10 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
12 * Support : Micrel Phys:
13 * Giga phys: ksz9021, ksz9031, ksz9131
14 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
15 * ksz8021, ksz8031, ksz8051,
18 * Switch : ksz8873, ksz886x
22 #include <linux/bitfield.h>
23 #include <linux/ethtool_netlink.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/phy.h>
27 #include <linux/micrel_phy.h>
29 #include <linux/clk.h>
30 #include <linux/delay.h>
31 #include <linux/ptp_clock_kernel.h>
32 #include <linux/ptp_clock.h>
33 #include <linux/ptp_classify.h>
34 #include <linux/net_tstamp.h>
35 #include <linux/gpio/consumer.h>
37 /* Operation Mode Strap Override */
38 #define MII_KSZPHY_OMSO 0x16
39 #define KSZPHY_OMSO_FACTORY_TEST BIT(15)
40 #define KSZPHY_OMSO_B_CAST_OFF BIT(9)
41 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
42 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
43 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
45 /* general Interrupt control/status reg in vendor specific block. */
46 #define MII_KSZPHY_INTCS 0x1B
47 #define KSZPHY_INTCS_JABBER BIT(15)
48 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
49 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
50 #define KSZPHY_INTCS_PARELLEL BIT(12)
51 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
52 #define KSZPHY_INTCS_LINK_DOWN BIT(10)
53 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
54 #define KSZPHY_INTCS_LINK_UP BIT(8)
55 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
56 KSZPHY_INTCS_LINK_DOWN)
57 #define KSZPHY_INTCS_LINK_DOWN_STATUS BIT(2)
58 #define KSZPHY_INTCS_LINK_UP_STATUS BIT(0)
59 #define KSZPHY_INTCS_STATUS (KSZPHY_INTCS_LINK_DOWN_STATUS |\
60 KSZPHY_INTCS_LINK_UP_STATUS)
62 /* LinkMD Control/Status */
63 #define KSZ8081_LMD 0x1d
64 #define KSZ8081_LMD_ENABLE_TEST BIT(15)
65 #define KSZ8081_LMD_STAT_NORMAL 0
66 #define KSZ8081_LMD_STAT_OPEN 1
67 #define KSZ8081_LMD_STAT_SHORT 2
68 #define KSZ8081_LMD_STAT_FAIL 3
69 #define KSZ8081_LMD_STAT_MASK GENMASK(14, 13)
70 /* Short cable (<10 meter) has been detected by LinkMD */
71 #define KSZ8081_LMD_SHORT_INDICATOR BIT(12)
72 #define KSZ8081_LMD_DELTA_TIME_MASK GENMASK(8, 0)
74 #define KSZ9x31_LMD 0x12
75 #define KSZ9x31_LMD_VCT_EN BIT(15)
76 #define KSZ9x31_LMD_VCT_DIS_TX BIT(14)
77 #define KSZ9x31_LMD_VCT_PAIR(n) (((n) & 0x3) << 12)
78 #define KSZ9x31_LMD_VCT_SEL_RESULT 0
79 #define KSZ9x31_LMD_VCT_SEL_THRES_HI BIT(10)
80 #define KSZ9x31_LMD_VCT_SEL_THRES_LO BIT(11)
81 #define KSZ9x31_LMD_VCT_SEL_MASK GENMASK(11, 10)
82 #define KSZ9x31_LMD_VCT_ST_NORMAL 0
83 #define KSZ9x31_LMD_VCT_ST_OPEN 1
84 #define KSZ9x31_LMD_VCT_ST_SHORT 2
85 #define KSZ9x31_LMD_VCT_ST_FAIL 3
86 #define KSZ9x31_LMD_VCT_ST_MASK GENMASK(9, 8)
87 #define KSZ9x31_LMD_VCT_DATA_REFLECTED_INVALID BIT(7)
88 #define KSZ9x31_LMD_VCT_DATA_SIG_WAIT_TOO_LONG BIT(6)
89 #define KSZ9x31_LMD_VCT_DATA_MASK100 BIT(5)
90 #define KSZ9x31_LMD_VCT_DATA_NLP_FLP BIT(4)
91 #define KSZ9x31_LMD_VCT_DATA_LO_PULSE_MASK GENMASK(3, 2)
92 #define KSZ9x31_LMD_VCT_DATA_HI_PULSE_MASK GENMASK(1, 0)
93 #define KSZ9x31_LMD_VCT_DATA_MASK GENMASK(7, 0)
95 /* Lan8814 general Interrupt control/status reg in GPHY specific block. */
96 #define LAN8814_INTC 0x18
97 #define LAN8814_INTS 0x1B
99 #define LAN8814_INT_LINK_DOWN BIT(2)
100 #define LAN8814_INT_LINK_UP BIT(0)
101 #define LAN8814_INT_LINK (LAN8814_INT_LINK_UP |\
102 LAN8814_INT_LINK_DOWN)
104 #define LAN8814_INTR_CTRL_REG 0x34
105 #define LAN8814_INTR_CTRL_REG_POLARITY BIT(1)
106 #define LAN8814_INTR_CTRL_REG_INTR_ENABLE BIT(0)
108 /* Represents 1ppm adjustment in 2^32 format with
109 * each nsec contains 4 clock cycles.
110 * The value is calculated as following: (1/1000000)/((2^-32)/4)
112 #define LAN8814_1PPM_FORMAT 17179
114 #define PTP_RX_MOD 0x024F
115 #define PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
116 #define PTP_RX_TIMESTAMP_EN 0x024D
117 #define PTP_TX_TIMESTAMP_EN 0x028D
119 #define PTP_TIMESTAMP_EN_SYNC_ BIT(0)
120 #define PTP_TIMESTAMP_EN_DREQ_ BIT(1)
121 #define PTP_TIMESTAMP_EN_PDREQ_ BIT(2)
122 #define PTP_TIMESTAMP_EN_PDRES_ BIT(3)
124 #define PTP_TX_PARSE_L2_ADDR_EN 0x0284
125 #define PTP_RX_PARSE_L2_ADDR_EN 0x0244
127 #define PTP_TX_PARSE_IP_ADDR_EN 0x0285
128 #define PTP_RX_PARSE_IP_ADDR_EN 0x0245
129 #define LTC_HARD_RESET 0x023F
130 #define LTC_HARD_RESET_ BIT(0)
132 #define TSU_HARD_RESET 0x02C1
133 #define TSU_HARD_RESET_ BIT(0)
135 #define PTP_CMD_CTL 0x0200
136 #define PTP_CMD_CTL_PTP_DISABLE_ BIT(0)
137 #define PTP_CMD_CTL_PTP_ENABLE_ BIT(1)
138 #define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3)
139 #define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4)
140 #define PTP_CMD_CTL_PTP_LTC_STEP_SEC_ BIT(5)
141 #define PTP_CMD_CTL_PTP_LTC_STEP_NSEC_ BIT(6)
143 #define PTP_CLOCK_SET_SEC_MID 0x0206
144 #define PTP_CLOCK_SET_SEC_LO 0x0207
145 #define PTP_CLOCK_SET_NS_HI 0x0208
146 #define PTP_CLOCK_SET_NS_LO 0x0209
148 #define PTP_CLOCK_READ_SEC_MID 0x022A
149 #define PTP_CLOCK_READ_SEC_LO 0x022B
150 #define PTP_CLOCK_READ_NS_HI 0x022C
151 #define PTP_CLOCK_READ_NS_LO 0x022D
153 #define PTP_OPERATING_MODE 0x0241
154 #define PTP_OPERATING_MODE_STANDALONE_ BIT(0)
156 #define PTP_TX_MOD 0x028F
157 #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ BIT(12)
158 #define PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
160 #define PTP_RX_PARSE_CONFIG 0x0242
161 #define PTP_RX_PARSE_CONFIG_LAYER2_EN_ BIT(0)
162 #define PTP_RX_PARSE_CONFIG_IPV4_EN_ BIT(1)
163 #define PTP_RX_PARSE_CONFIG_IPV6_EN_ BIT(2)
165 #define PTP_TX_PARSE_CONFIG 0x0282
166 #define PTP_TX_PARSE_CONFIG_LAYER2_EN_ BIT(0)
167 #define PTP_TX_PARSE_CONFIG_IPV4_EN_ BIT(1)
168 #define PTP_TX_PARSE_CONFIG_IPV6_EN_ BIT(2)
170 #define PTP_CLOCK_RATE_ADJ_HI 0x020C
171 #define PTP_CLOCK_RATE_ADJ_LO 0x020D
172 #define PTP_CLOCK_RATE_ADJ_DIR_ BIT(15)
174 #define PTP_LTC_STEP_ADJ_HI 0x0212
175 #define PTP_LTC_STEP_ADJ_LO 0x0213
176 #define PTP_LTC_STEP_ADJ_DIR_ BIT(15)
178 #define LAN8814_INTR_STS_REG 0x0033
179 #define LAN8814_INTR_STS_REG_1588_TSU0_ BIT(0)
180 #define LAN8814_INTR_STS_REG_1588_TSU1_ BIT(1)
181 #define LAN8814_INTR_STS_REG_1588_TSU2_ BIT(2)
182 #define LAN8814_INTR_STS_REG_1588_TSU3_ BIT(3)
184 #define PTP_CAP_INFO 0x022A
185 #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x0f00) >> 8)
186 #define PTP_CAP_INFO_RX_TS_CNT_GET_(reg_val) ((reg_val) & 0x000f)
188 #define PTP_TX_EGRESS_SEC_HI 0x0296
189 #define PTP_TX_EGRESS_SEC_LO 0x0297
190 #define PTP_TX_EGRESS_NS_HI 0x0294
191 #define PTP_TX_EGRESS_NS_LO 0x0295
192 #define PTP_TX_MSG_HEADER2 0x0299
194 #define PTP_RX_INGRESS_SEC_HI 0x0256
195 #define PTP_RX_INGRESS_SEC_LO 0x0257
196 #define PTP_RX_INGRESS_NS_HI 0x0254
197 #define PTP_RX_INGRESS_NS_LO 0x0255
198 #define PTP_RX_MSG_HEADER2 0x0259
200 #define PTP_TSU_INT_EN 0x0200
201 #define PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ BIT(3)
202 #define PTP_TSU_INT_EN_PTP_TX_TS_EN_ BIT(2)
203 #define PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_ BIT(1)
204 #define PTP_TSU_INT_EN_PTP_RX_TS_EN_ BIT(0)
206 #define PTP_TSU_INT_STS 0x0201
207 #define PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_ BIT(3)
208 #define PTP_TSU_INT_STS_PTP_TX_TS_EN_ BIT(2)
209 #define PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_ BIT(1)
210 #define PTP_TSU_INT_STS_PTP_RX_TS_EN_ BIT(0)
213 #define MII_KSZPHY_CTRL_1 0x1e
214 #define KSZ8081_CTRL1_MDIX_STAT BIT(4)
216 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
217 #define MII_KSZPHY_CTRL_2 0x1f
218 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
219 /* bitmap of PHY register to set interrupt mode */
220 #define KSZ8081_CTRL2_HP_MDIX BIT(15)
221 #define KSZ8081_CTRL2_MDI_MDI_X_SELECT BIT(14)
222 #define KSZ8081_CTRL2_DISABLE_AUTO_MDIX BIT(13)
223 #define KSZ8081_CTRL2_FORCE_LINK BIT(11)
224 #define KSZ8081_CTRL2_POWER_SAVING BIT(10)
225 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
226 #define KSZPHY_RMII_REF_CLK_SEL BIT(7)
228 /* Write/read to/from extended registers */
229 #define MII_KSZPHY_EXTREG 0x0b
230 #define KSZPHY_EXTREG_WRITE 0x8000
232 #define MII_KSZPHY_EXTREG_WRITE 0x0c
233 #define MII_KSZPHY_EXTREG_READ 0x0d
235 /* Extended registers */
236 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
237 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
238 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
240 #define PS_TO_REG 200
243 struct kszphy_hw_stat {
249 static struct kszphy_hw_stat kszphy_hw_stats[] = {
250 { "phy_receive_errors", 21, 16},
251 { "phy_idle_errors", 10, 8 },
256 u16 interrupt_level_mask;
257 bool has_broadcast_disable;
258 bool has_nand_tree_disable;
259 bool has_rmii_ref_clk_sel;
262 /* Shared structure between the PHYs of the same package. */
263 struct lan8814_shared_priv {
264 struct phy_device *phydev;
265 struct ptp_clock *ptp_clock;
266 struct ptp_clock_info ptp_clock_info;
268 /* Reference counter to how many ports in the package are enabling the
273 /* Lock for ptp_clock and ref */
274 struct mutex shared_lock;
277 struct lan8814_ptp_rx_ts {
278 struct list_head list;
284 struct kszphy_ptp_priv {
285 struct mii_timestamper mii_ts;
286 struct phy_device *phydev;
288 struct sk_buff_head tx_queue;
289 struct sk_buff_head rx_queue;
291 struct list_head rx_ts_list;
292 /* Lock for Rx ts fifo */
293 spinlock_t rx_ts_lock;
296 enum hwtstamp_rx_filters rx_filter;
302 struct kszphy_ptp_priv ptp_priv;
303 const struct kszphy_type *type;
306 bool rmii_ref_clk_sel;
307 bool rmii_ref_clk_sel_val;
308 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
311 static const struct kszphy_type ksz8021_type = {
312 .led_mode_reg = MII_KSZPHY_CTRL_2,
313 .has_broadcast_disable = true,
314 .has_nand_tree_disable = true,
315 .has_rmii_ref_clk_sel = true,
318 static const struct kszphy_type ksz8041_type = {
319 .led_mode_reg = MII_KSZPHY_CTRL_1,
322 static const struct kszphy_type ksz8051_type = {
323 .led_mode_reg = MII_KSZPHY_CTRL_2,
324 .has_nand_tree_disable = true,
327 static const struct kszphy_type ksz8081_type = {
328 .led_mode_reg = MII_KSZPHY_CTRL_2,
329 .has_broadcast_disable = true,
330 .has_nand_tree_disable = true,
331 .has_rmii_ref_clk_sel = true,
334 static const struct kszphy_type ks8737_type = {
335 .interrupt_level_mask = BIT(14),
338 static const struct kszphy_type ksz9021_type = {
339 .interrupt_level_mask = BIT(14),
342 static int kszphy_extended_write(struct phy_device *phydev,
345 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
346 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
349 static int kszphy_extended_read(struct phy_device *phydev,
352 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
353 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
356 static int kszphy_ack_interrupt(struct phy_device *phydev)
358 /* bit[7..0] int status, which is a read and clear register. */
361 rc = phy_read(phydev, MII_KSZPHY_INTCS);
363 return (rc < 0) ? rc : 0;
366 static int kszphy_config_intr(struct phy_device *phydev)
368 const struct kszphy_type *type = phydev->drv->driver_data;
372 if (type && type->interrupt_level_mask)
373 mask = type->interrupt_level_mask;
375 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
377 /* set the interrupt pin active low */
378 temp = phy_read(phydev, MII_KSZPHY_CTRL);
382 phy_write(phydev, MII_KSZPHY_CTRL, temp);
384 /* enable / disable interrupts */
385 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
386 err = kszphy_ack_interrupt(phydev);
390 temp = KSZPHY_INTCS_ALL;
391 err = phy_write(phydev, MII_KSZPHY_INTCS, temp);
394 err = phy_write(phydev, MII_KSZPHY_INTCS, temp);
398 err = kszphy_ack_interrupt(phydev);
404 static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev)
408 irq_status = phy_read(phydev, MII_KSZPHY_INTCS);
409 if (irq_status < 0) {
414 if (!(irq_status & KSZPHY_INTCS_STATUS))
417 phy_trigger_machine(phydev);
422 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
426 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
431 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
433 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
435 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
438 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
443 case MII_KSZPHY_CTRL_1:
446 case MII_KSZPHY_CTRL_2:
453 temp = phy_read(phydev, reg);
459 temp &= ~(3 << shift);
460 temp |= val << shift;
461 rc = phy_write(phydev, reg, temp);
464 phydev_err(phydev, "failed to set led mode\n");
469 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
470 * unique (non-broadcast) address on a shared bus.
472 static int kszphy_broadcast_disable(struct phy_device *phydev)
476 ret = phy_read(phydev, MII_KSZPHY_OMSO);
480 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
483 phydev_err(phydev, "failed to disable broadcast address\n");
488 static int kszphy_nand_tree_disable(struct phy_device *phydev)
492 ret = phy_read(phydev, MII_KSZPHY_OMSO);
496 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
499 ret = phy_write(phydev, MII_KSZPHY_OMSO,
500 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
503 phydev_err(phydev, "failed to disable NAND tree mode\n");
508 /* Some config bits need to be set again on resume, handle them here. */
509 static int kszphy_config_reset(struct phy_device *phydev)
511 struct kszphy_priv *priv = phydev->priv;
514 if (priv->rmii_ref_clk_sel) {
515 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
518 "failed to set rmii reference clock\n");
523 if (priv->type && priv->led_mode >= 0)
524 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
529 static int kszphy_config_init(struct phy_device *phydev)
531 struct kszphy_priv *priv = phydev->priv;
532 const struct kszphy_type *type;
539 if (type && type->has_broadcast_disable)
540 kszphy_broadcast_disable(phydev);
542 if (type && type->has_nand_tree_disable)
543 kszphy_nand_tree_disable(phydev);
545 return kszphy_config_reset(phydev);
548 static int ksz8041_fiber_mode(struct phy_device *phydev)
550 struct device_node *of_node = phydev->mdio.dev.of_node;
552 return of_property_read_bool(of_node, "micrel,fiber-mode");
555 static int ksz8041_config_init(struct phy_device *phydev)
557 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
559 /* Limit supported and advertised modes in fiber mode */
560 if (ksz8041_fiber_mode(phydev)) {
561 phydev->dev_flags |= MICREL_PHY_FXEN;
562 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
563 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
565 linkmode_and(phydev->supported, phydev->supported, mask);
566 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
568 linkmode_and(phydev->advertising, phydev->advertising, mask);
569 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
570 phydev->advertising);
571 phydev->autoneg = AUTONEG_DISABLE;
574 return kszphy_config_init(phydev);
577 static int ksz8041_config_aneg(struct phy_device *phydev)
579 /* Skip auto-negotiation in fiber mode */
580 if (phydev->dev_flags & MICREL_PHY_FXEN) {
581 phydev->speed = SPEED_100;
585 return genphy_config_aneg(phydev);
588 static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
593 if ((phydev->phy_id & MICREL_PHY_ID_MASK) != PHY_ID_KSZ8051)
596 ret = phy_read(phydev, MII_BMSR);
600 /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
601 * exact PHY ID. However, they can be told apart by the extended
602 * capability registers presence. The KSZ8051 PHY has them while
603 * the switch does not.
612 static int ksz8051_match_phy_device(struct phy_device *phydev)
614 return ksz8051_ksz8795_match_phy_device(phydev, true);
617 static int ksz8081_config_init(struct phy_device *phydev)
619 /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
620 * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
621 * pull-down is missing, the factory test mode should be cleared by
622 * manually writing a 0.
624 phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
626 return kszphy_config_init(phydev);
629 static int ksz8081_config_mdix(struct phy_device *phydev, u8 ctrl)
635 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX;
638 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX |
639 KSZ8081_CTRL2_MDI_MDI_X_SELECT;
641 case ETH_TP_MDI_AUTO:
648 return phy_modify(phydev, MII_KSZPHY_CTRL_2,
649 KSZ8081_CTRL2_HP_MDIX |
650 KSZ8081_CTRL2_MDI_MDI_X_SELECT |
651 KSZ8081_CTRL2_DISABLE_AUTO_MDIX,
652 KSZ8081_CTRL2_HP_MDIX | val);
655 static int ksz8081_config_aneg(struct phy_device *phydev)
659 ret = genphy_config_aneg(phydev);
663 /* The MDI-X configuration is automatically changed by the PHY after
664 * switching from autoneg off to on. So, take MDI-X configuration under
665 * own control and set it after autoneg configuration was done.
667 return ksz8081_config_mdix(phydev, phydev->mdix_ctrl);
670 static int ksz8081_mdix_update(struct phy_device *phydev)
674 ret = phy_read(phydev, MII_KSZPHY_CTRL_2);
678 if (ret & KSZ8081_CTRL2_DISABLE_AUTO_MDIX) {
679 if (ret & KSZ8081_CTRL2_MDI_MDI_X_SELECT)
680 phydev->mdix_ctrl = ETH_TP_MDI_X;
682 phydev->mdix_ctrl = ETH_TP_MDI;
684 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
687 ret = phy_read(phydev, MII_KSZPHY_CTRL_1);
691 if (ret & KSZ8081_CTRL1_MDIX_STAT)
692 phydev->mdix = ETH_TP_MDI;
694 phydev->mdix = ETH_TP_MDI_X;
699 static int ksz8081_read_status(struct phy_device *phydev)
703 ret = ksz8081_mdix_update(phydev);
707 return genphy_read_status(phydev);
710 static int ksz8061_config_init(struct phy_device *phydev)
714 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
718 return kszphy_config_init(phydev);
721 static int ksz8795_match_phy_device(struct phy_device *phydev)
723 return ksz8051_ksz8795_match_phy_device(phydev, false);
726 static int ksz9021_load_values_from_of(struct phy_device *phydev,
727 const struct device_node *of_node,
729 const char *field1, const char *field2,
730 const char *field3, const char *field4)
739 if (!of_property_read_u32(of_node, field1, &val1))
742 if (!of_property_read_u32(of_node, field2, &val2))
745 if (!of_property_read_u32(of_node, field3, &val3))
748 if (!of_property_read_u32(of_node, field4, &val4))
755 newval = kszphy_extended_read(phydev, reg);
760 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
763 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
766 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
769 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
771 return kszphy_extended_write(phydev, reg, newval);
774 static int ksz9021_config_init(struct phy_device *phydev)
776 const struct device_node *of_node;
777 const struct device *dev_walker;
779 /* The Micrel driver has a deprecated option to place phy OF
780 * properties in the MAC node. Walk up the tree of devices to
781 * find a device with an OF node.
783 dev_walker = &phydev->mdio.dev;
785 of_node = dev_walker->of_node;
786 dev_walker = dev_walker->parent;
788 } while (!of_node && dev_walker);
791 ksz9021_load_values_from_of(phydev, of_node,
792 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
793 "txen-skew-ps", "txc-skew-ps",
794 "rxdv-skew-ps", "rxc-skew-ps");
795 ksz9021_load_values_from_of(phydev, of_node,
796 MII_KSZPHY_RX_DATA_PAD_SKEW,
797 "rxd0-skew-ps", "rxd1-skew-ps",
798 "rxd2-skew-ps", "rxd3-skew-ps");
799 ksz9021_load_values_from_of(phydev, of_node,
800 MII_KSZPHY_TX_DATA_PAD_SKEW,
801 "txd0-skew-ps", "txd1-skew-ps",
802 "txd2-skew-ps", "txd3-skew-ps");
807 #define KSZ9031_PS_TO_REG 60
809 /* Extended registers */
810 /* MMD Address 0x0 */
811 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3
812 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4
814 /* MMD Address 0x2 */
815 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
816 #define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4)
817 #define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0)
819 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
820 #define MII_KSZ9031RN_RXD3 GENMASK(15, 12)
821 #define MII_KSZ9031RN_RXD2 GENMASK(11, 8)
822 #define MII_KSZ9031RN_RXD1 GENMASK(7, 4)
823 #define MII_KSZ9031RN_RXD0 GENMASK(3, 0)
825 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
826 #define MII_KSZ9031RN_TXD3 GENMASK(15, 12)
827 #define MII_KSZ9031RN_TXD2 GENMASK(11, 8)
828 #define MII_KSZ9031RN_TXD1 GENMASK(7, 4)
829 #define MII_KSZ9031RN_TXD0 GENMASK(3, 0)
831 #define MII_KSZ9031RN_CLK_PAD_SKEW 8
832 #define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5)
833 #define MII_KSZ9031RN_RX_CLK GENMASK(4, 0)
835 /* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To
836 * provide different RGMII options we need to configure delay offset
837 * for each pad relative to build in delay.
839 /* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of
843 #define RX_CLK_ID 0x19
845 /* set rx to +0.30ns and rx_clk to -0.90ns to compensate the
846 * internal 1.2ns delay.
849 #define RX_CLK_ND 0x0
851 /* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
853 #define TX_CLK_ID 0x1f
855 /* set tx and tx_clk to "No delay adjustment" to keep 0ns
859 #define TX_CLK_ND 0xf
861 /* MMD Address 0x1C */
862 #define MII_KSZ9031RN_EDPD 0x23
863 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
865 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
866 const struct device_node *of_node,
867 u16 reg, size_t field_sz,
868 const char *field[], u8 numfields,
871 int val[4] = {-1, -2, -3, -4};
878 for (i = 0; i < numfields; i++)
879 if (!of_property_read_u32(of_node, field[i], val + i))
887 if (matches < numfields)
888 newval = phy_read_mmd(phydev, 2, reg);
892 maxval = (field_sz == 4) ? 0xf : 0x1f;
893 for (i = 0; i < numfields; i++)
894 if (val[i] != -(i + 1)) {
896 mask ^= maxval << (field_sz * i);
897 newval = (newval & mask) |
898 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
902 return phy_write_mmd(phydev, 2, reg, newval);
905 /* Center KSZ9031RNX FLP timing at 16ms. */
906 static int ksz9031_center_flp_timing(struct phy_device *phydev)
910 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
915 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
920 return genphy_restart_aneg(phydev);
923 /* Enable energy-detect power-down mode */
924 static int ksz9031_enable_edpd(struct phy_device *phydev)
928 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
931 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
932 reg | MII_KSZ9031RN_EDPD_ENABLE);
935 static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
937 u16 rx, tx, rx_clk, tx_clk;
940 switch (phydev->interface) {
941 case PHY_INTERFACE_MODE_RGMII:
947 case PHY_INTERFACE_MODE_RGMII_ID:
953 case PHY_INTERFACE_MODE_RGMII_RXID:
959 case PHY_INTERFACE_MODE_RGMII_TXID:
969 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,
970 FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) |
971 FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));
975 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,
976 FIELD_PREP(MII_KSZ9031RN_RXD3, rx) |
977 FIELD_PREP(MII_KSZ9031RN_RXD2, rx) |
978 FIELD_PREP(MII_KSZ9031RN_RXD1, rx) |
979 FIELD_PREP(MII_KSZ9031RN_RXD0, rx));
983 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,
984 FIELD_PREP(MII_KSZ9031RN_TXD3, tx) |
985 FIELD_PREP(MII_KSZ9031RN_TXD2, tx) |
986 FIELD_PREP(MII_KSZ9031RN_TXD1, tx) |
987 FIELD_PREP(MII_KSZ9031RN_TXD0, tx));
991 return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW,
992 FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) |
993 FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));
996 static int ksz9031_config_init(struct phy_device *phydev)
998 const struct device_node *of_node;
999 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
1000 static const char *rx_data_skews[4] = {
1001 "rxd0-skew-ps", "rxd1-skew-ps",
1002 "rxd2-skew-ps", "rxd3-skew-ps"
1004 static const char *tx_data_skews[4] = {
1005 "txd0-skew-ps", "txd1-skew-ps",
1006 "txd2-skew-ps", "txd3-skew-ps"
1008 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
1009 const struct device *dev_walker;
1012 result = ksz9031_enable_edpd(phydev);
1016 /* The Micrel driver has a deprecated option to place phy OF
1017 * properties in the MAC node. Walk up the tree of devices to
1018 * find a device with an OF node.
1020 dev_walker = &phydev->mdio.dev;
1022 of_node = dev_walker->of_node;
1023 dev_walker = dev_walker->parent;
1024 } while (!of_node && dev_walker);
1027 bool update = false;
1029 if (phy_interface_is_rgmii(phydev)) {
1030 result = ksz9031_config_rgmii_delay(phydev);
1035 ksz9031_of_load_skew_values(phydev, of_node,
1036 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1037 clk_skews, 2, &update);
1039 ksz9031_of_load_skew_values(phydev, of_node,
1040 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1041 control_skews, 2, &update);
1043 ksz9031_of_load_skew_values(phydev, of_node,
1044 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1045 rx_data_skews, 4, &update);
1047 ksz9031_of_load_skew_values(phydev, of_node,
1048 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1049 tx_data_skews, 4, &update);
1051 if (update && !phy_interface_is_rgmii(phydev))
1053 "*-skew-ps values should be used only with RGMII PHY modes\n");
1055 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1056 * When the device links in the 1000BASE-T slave mode only,
1057 * the optional 125MHz reference output clock (CLK125_NDO)
1058 * has wide duty cycle variation.
1060 * The optional CLK125_NDO clock does not meet the RGMII
1061 * 45/55 percent (min/max) duty cycle requirement and therefore
1062 * cannot be used directly by the MAC side for clocking
1063 * applications that have setup/hold time requirements on
1064 * rising and falling clock edges.
1067 * Force the phy to be the master to receive a stable clock
1068 * which meets the duty cycle requirement.
1070 if (of_property_read_bool(of_node, "micrel,force-master")) {
1071 result = phy_read(phydev, MII_CTRL1000);
1073 goto err_force_master;
1075 /* enable master mode, config & prefer master */
1076 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
1077 result = phy_write(phydev, MII_CTRL1000, result);
1079 goto err_force_master;
1083 return ksz9031_center_flp_timing(phydev);
1086 phydev_err(phydev, "failed to force the phy to master mode\n");
1090 #define KSZ9131_SKEW_5BIT_MAX 2400
1091 #define KSZ9131_SKEW_4BIT_MAX 800
1092 #define KSZ9131_OFFSET 700
1093 #define KSZ9131_STEP 100
1095 static int ksz9131_of_load_skew_values(struct phy_device *phydev,
1096 struct device_node *of_node,
1097 u16 reg, size_t field_sz,
1098 char *field[], u8 numfields)
1100 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
1101 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
1102 int skewval, skewmax = 0;
1109 /* psec properties in dts should mean x pico seconds */
1111 skewmax = KSZ9131_SKEW_5BIT_MAX;
1113 skewmax = KSZ9131_SKEW_4BIT_MAX;
1115 for (i = 0; i < numfields; i++)
1116 if (!of_property_read_s32(of_node, field[i], &skewval)) {
1117 if (skewval < -KSZ9131_OFFSET)
1118 skewval = -KSZ9131_OFFSET;
1119 else if (skewval > skewmax)
1122 val[i] = skewval + KSZ9131_OFFSET;
1129 if (matches < numfields)
1130 newval = phy_read_mmd(phydev, 2, reg);
1134 maxval = (field_sz == 4) ? 0xf : 0x1f;
1135 for (i = 0; i < numfields; i++)
1136 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
1138 mask ^= maxval << (field_sz * i);
1139 newval = (newval & mask) |
1140 (((val[i] / KSZ9131_STEP) & maxval)
1144 return phy_write_mmd(phydev, 2, reg, newval);
1147 #define KSZ9131RN_MMD_COMMON_CTRL_REG 2
1148 #define KSZ9131RN_RXC_DLL_CTRL 76
1149 #define KSZ9131RN_TXC_DLL_CTRL 77
1150 #define KSZ9131RN_DLL_CTRL_BYPASS BIT_MASK(12)
1151 #define KSZ9131RN_DLL_ENABLE_DELAY 0
1152 #define KSZ9131RN_DLL_DISABLE_DELAY BIT(12)
1154 static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
1156 u16 rxcdll_val, txcdll_val;
1159 switch (phydev->interface) {
1160 case PHY_INTERFACE_MODE_RGMII:
1161 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1162 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1164 case PHY_INTERFACE_MODE_RGMII_ID:
1165 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1166 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1168 case PHY_INTERFACE_MODE_RGMII_RXID:
1169 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1170 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1172 case PHY_INTERFACE_MODE_RGMII_TXID:
1173 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1174 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1180 ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1181 KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
1186 return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1187 KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
1191 /* Silicon Errata DS80000693B
1193 * When LEDs are configured in Individual Mode, LED1 is ON in a no-link
1194 * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
1195 * according to the datasheet (off if there is no link).
1197 static int ksz9131_led_errata(struct phy_device *phydev)
1201 reg = phy_read_mmd(phydev, 2, 0);
1205 if (!(reg & BIT(4)))
1208 return phy_set_bits(phydev, 0x1e, BIT(9));
1211 static int ksz9131_config_init(struct phy_device *phydev)
1213 struct device_node *of_node;
1214 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
1215 char *rx_data_skews[4] = {
1216 "rxd0-skew-psec", "rxd1-skew-psec",
1217 "rxd2-skew-psec", "rxd3-skew-psec"
1219 char *tx_data_skews[4] = {
1220 "txd0-skew-psec", "txd1-skew-psec",
1221 "txd2-skew-psec", "txd3-skew-psec"
1223 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
1224 const struct device *dev_walker;
1227 dev_walker = &phydev->mdio.dev;
1229 of_node = dev_walker->of_node;
1230 dev_walker = dev_walker->parent;
1231 } while (!of_node && dev_walker);
1236 if (phy_interface_is_rgmii(phydev)) {
1237 ret = ksz9131_config_rgmii_delay(phydev);
1242 ret = ksz9131_of_load_skew_values(phydev, of_node,
1243 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1248 ret = ksz9131_of_load_skew_values(phydev, of_node,
1249 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1254 ret = ksz9131_of_load_skew_values(phydev, of_node,
1255 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1260 ret = ksz9131_of_load_skew_values(phydev, of_node,
1261 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1266 ret = ksz9131_led_errata(phydev);
1273 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
1274 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
1275 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
1276 static int ksz8873mll_read_status(struct phy_device *phydev)
1281 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1283 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1285 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
1286 phydev->duplex = DUPLEX_HALF;
1288 phydev->duplex = DUPLEX_FULL;
1290 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
1291 phydev->speed = SPEED_10;
1293 phydev->speed = SPEED_100;
1296 phydev->pause = phydev->asym_pause = 0;
1301 static int ksz9031_get_features(struct phy_device *phydev)
1305 ret = genphy_read_abilities(phydev);
1309 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1310 * Whenever the device's Asymmetric Pause capability is set to 1,
1311 * link-up may fail after a link-up to link-down transition.
1313 * The Errata Sheet is for ksz9031, but ksz9021 has the same issue
1316 * Do not enable the Asymmetric Pause capability bit.
1318 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
1320 /* We force setting the Pause capability as the core will force the
1321 * Asymmetric Pause capability to 1 otherwise.
1323 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
1328 static int ksz9031_read_status(struct phy_device *phydev)
1333 err = genphy_read_status(phydev);
1337 /* Make sure the PHY is not broken. Read idle error count,
1338 * and reset the PHY if it is maxed out.
1340 regval = phy_read(phydev, MII_STAT1000);
1341 if ((regval & 0xFF) == 0xFF) {
1342 phy_init_hw(phydev);
1344 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
1345 phydev->drv->config_intr(phydev);
1346 return genphy_config_aneg(phydev);
1352 static int ksz9x31_cable_test_start(struct phy_device *phydev)
1354 struct kszphy_priv *priv = phydev->priv;
1357 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1358 * Prior to running the cable diagnostics, Auto-negotiation should
1359 * be disabled, full duplex set and the link speed set to 1000Mbps
1360 * via the Basic Control Register.
1362 ret = phy_modify(phydev, MII_BMCR,
1363 BMCR_SPEED1000 | BMCR_FULLDPLX |
1364 BMCR_ANENABLE | BMCR_SPEED100,
1365 BMCR_SPEED1000 | BMCR_FULLDPLX);
1369 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1370 * The Master-Slave configuration should be set to Slave by writing
1371 * a value of 0x1000 to the Auto-Negotiation Master Slave Control
1374 ret = phy_read(phydev, MII_CTRL1000);
1378 /* Cache these bits, they need to be restored once LinkMD finishes. */
1379 priv->vct_ctrl1000 = ret & (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1380 ret &= ~(CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1381 ret |= CTL1000_ENABLE_MASTER;
1383 return phy_write(phydev, MII_CTRL1000, ret);
1386 static int ksz9x31_cable_test_result_trans(u16 status)
1388 switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1389 case KSZ9x31_LMD_VCT_ST_NORMAL:
1390 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1391 case KSZ9x31_LMD_VCT_ST_OPEN:
1392 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1393 case KSZ9x31_LMD_VCT_ST_SHORT:
1394 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1395 case KSZ9x31_LMD_VCT_ST_FAIL:
1398 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1402 static bool ksz9x31_cable_test_failed(u16 status)
1404 int stat = FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status);
1406 return stat == KSZ9x31_LMD_VCT_ST_FAIL;
1409 static bool ksz9x31_cable_test_fault_length_valid(u16 status)
1411 switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1412 case KSZ9x31_LMD_VCT_ST_OPEN:
1414 case KSZ9x31_LMD_VCT_ST_SHORT:
1420 static int ksz9x31_cable_test_fault_length(struct phy_device *phydev, u16 stat)
1422 int dt = FIELD_GET(KSZ9x31_LMD_VCT_DATA_MASK, stat);
1424 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1426 * distance to fault = (VCT_DATA - 22) * 4 / cable propagation velocity
1428 if ((phydev->phy_id & MICREL_PHY_ID_MASK) == PHY_ID_KSZ9131)
1429 dt = clamp(dt - 22, 0, 255);
1431 return (dt * 400) / 10;
1434 static int ksz9x31_cable_test_wait_for_completion(struct phy_device *phydev)
1438 ret = phy_read_poll_timeout(phydev, KSZ9x31_LMD, val,
1439 !(val & KSZ9x31_LMD_VCT_EN),
1440 30000, 100000, true);
1442 return ret < 0 ? ret : 0;
1445 static int ksz9x31_cable_test_get_pair(int pair)
1447 static const int ethtool_pair[] = {
1448 ETHTOOL_A_CABLE_PAIR_A,
1449 ETHTOOL_A_CABLE_PAIR_B,
1450 ETHTOOL_A_CABLE_PAIR_C,
1451 ETHTOOL_A_CABLE_PAIR_D,
1454 return ethtool_pair[pair];
1457 static int ksz9x31_cable_test_one_pair(struct phy_device *phydev, int pair)
1461 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1462 * To test each individual cable pair, set the cable pair in the Cable
1463 * Diagnostics Test Pair (VCT_PAIR[1:0]) field of the LinkMD Cable
1464 * Diagnostic Register, along with setting the Cable Diagnostics Test
1465 * Enable (VCT_EN) bit. The Cable Diagnostics Test Enable (VCT_EN) bit
1466 * will self clear when the test is concluded.
1468 ret = phy_write(phydev, KSZ9x31_LMD,
1469 KSZ9x31_LMD_VCT_EN | KSZ9x31_LMD_VCT_PAIR(pair));
1473 ret = ksz9x31_cable_test_wait_for_completion(phydev);
1477 val = phy_read(phydev, KSZ9x31_LMD);
1481 if (ksz9x31_cable_test_failed(val))
1484 ret = ethnl_cable_test_result(phydev,
1485 ksz9x31_cable_test_get_pair(pair),
1486 ksz9x31_cable_test_result_trans(val));
1490 if (!ksz9x31_cable_test_fault_length_valid(val))
1493 return ethnl_cable_test_fault_length(phydev,
1494 ksz9x31_cable_test_get_pair(pair),
1495 ksz9x31_cable_test_fault_length(phydev, val));
1498 static int ksz9x31_cable_test_get_status(struct phy_device *phydev,
1501 struct kszphy_priv *priv = phydev->priv;
1502 unsigned long pair_mask = 0xf;
1508 /* Try harder if link partner is active */
1509 while (pair_mask && retries--) {
1510 for_each_set_bit(pair, &pair_mask, 4) {
1511 ret = ksz9x31_cable_test_one_pair(phydev, pair);
1516 clear_bit(pair, &pair_mask);
1518 /* If link partner is in autonegotiation mode it will send 2ms
1519 * of FLPs with at least 6ms of silence.
1520 * Add 2ms sleep to have better chances to hit this silence.
1523 usleep_range(2000, 3000);
1526 /* Report remaining unfinished pair result as unknown. */
1527 for_each_set_bit(pair, &pair_mask, 4) {
1528 ret = ethnl_cable_test_result(phydev,
1529 ksz9x31_cable_test_get_pair(pair),
1530 ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC);
1535 /* Restore cached bits from before LinkMD got started. */
1536 rv = phy_modify(phydev, MII_CTRL1000,
1537 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER,
1538 priv->vct_ctrl1000);
1545 static int ksz8873mll_config_aneg(struct phy_device *phydev)
1550 static int ksz886x_config_mdix(struct phy_device *phydev, u8 ctrl)
1556 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX;
1559 /* Note: The naming of the bit KSZ886X_BMCR_FORCE_MDI is bit
1560 * counter intuitive, the "-X" in "1 = Force MDI" in the data
1561 * sheet seems to be missing:
1562 * 1 = Force MDI (sic!) (transmit on RX+/RX- pins)
1563 * 0 = Normal operation (transmit on TX+/TX- pins)
1565 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX | KSZ886X_BMCR_FORCE_MDI;
1567 case ETH_TP_MDI_AUTO:
1574 return phy_modify(phydev, MII_BMCR,
1575 KSZ886X_BMCR_HP_MDIX | KSZ886X_BMCR_FORCE_MDI |
1576 KSZ886X_BMCR_DISABLE_AUTO_MDIX,
1577 KSZ886X_BMCR_HP_MDIX | val);
1580 static int ksz886x_config_aneg(struct phy_device *phydev)
1584 ret = genphy_config_aneg(phydev);
1588 /* The MDI-X configuration is automatically changed by the PHY after
1589 * switching from autoneg off to on. So, take MDI-X configuration under
1590 * own control and set it after autoneg configuration was done.
1592 return ksz886x_config_mdix(phydev, phydev->mdix_ctrl);
1595 static int ksz886x_mdix_update(struct phy_device *phydev)
1599 ret = phy_read(phydev, MII_BMCR);
1603 if (ret & KSZ886X_BMCR_DISABLE_AUTO_MDIX) {
1604 if (ret & KSZ886X_BMCR_FORCE_MDI)
1605 phydev->mdix_ctrl = ETH_TP_MDI_X;
1607 phydev->mdix_ctrl = ETH_TP_MDI;
1609 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1612 ret = phy_read(phydev, MII_KSZPHY_CTRL);
1616 /* Same reverse logic as KSZ886X_BMCR_FORCE_MDI */
1617 if (ret & KSZ886X_CTRL_MDIX_STAT)
1618 phydev->mdix = ETH_TP_MDI_X;
1620 phydev->mdix = ETH_TP_MDI;
1625 static int ksz886x_read_status(struct phy_device *phydev)
1629 ret = ksz886x_mdix_update(phydev);
1633 return genphy_read_status(phydev);
1636 static int kszphy_get_sset_count(struct phy_device *phydev)
1638 return ARRAY_SIZE(kszphy_hw_stats);
1641 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
1645 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
1646 strlcpy(data + i * ETH_GSTRING_LEN,
1647 kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
1651 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
1653 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
1654 struct kszphy_priv *priv = phydev->priv;
1658 val = phy_read(phydev, stat.reg);
1662 val = val & ((1 << stat.bits) - 1);
1663 priv->stats[i] += val;
1664 ret = priv->stats[i];
1670 static void kszphy_get_stats(struct phy_device *phydev,
1671 struct ethtool_stats *stats, u64 *data)
1675 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
1676 data[i] = kszphy_get_stat(phydev, i);
1679 static int kszphy_suspend(struct phy_device *phydev)
1681 /* Disable PHY Interrupts */
1682 if (phy_interrupt_is_valid(phydev)) {
1683 phydev->interrupts = PHY_INTERRUPT_DISABLED;
1684 if (phydev->drv->config_intr)
1685 phydev->drv->config_intr(phydev);
1688 return genphy_suspend(phydev);
1691 static int kszphy_resume(struct phy_device *phydev)
1695 genphy_resume(phydev);
1697 /* After switching from power-down to normal mode, an internal global
1698 * reset is automatically generated. Wait a minimum of 1 ms before
1699 * read/write access to the PHY registers.
1701 usleep_range(1000, 2000);
1703 ret = kszphy_config_reset(phydev);
1707 /* Enable PHY Interrupts */
1708 if (phy_interrupt_is_valid(phydev)) {
1709 phydev->interrupts = PHY_INTERRUPT_ENABLED;
1710 if (phydev->drv->config_intr)
1711 phydev->drv->config_intr(phydev);
1717 static int kszphy_probe(struct phy_device *phydev)
1719 const struct kszphy_type *type = phydev->drv->driver_data;
1720 const struct device_node *np = phydev->mdio.dev.of_node;
1721 struct kszphy_priv *priv;
1725 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1729 phydev->priv = priv;
1733 if (type && type->led_mode_reg) {
1734 ret = of_property_read_u32(np, "micrel,led-mode",
1737 priv->led_mode = -1;
1739 if (priv->led_mode > 3) {
1740 phydev_err(phydev, "invalid led mode: 0x%02x\n",
1742 priv->led_mode = -1;
1745 priv->led_mode = -1;
1748 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
1749 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
1750 if (!IS_ERR_OR_NULL(clk)) {
1751 unsigned long rate = clk_get_rate(clk);
1752 bool rmii_ref_clk_sel_25_mhz;
1755 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
1756 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
1757 "micrel,rmii-reference-clock-select-25-mhz");
1759 if (rate > 24500000 && rate < 25500000) {
1760 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
1761 } else if (rate > 49500000 && rate < 50500000) {
1762 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
1764 phydev_err(phydev, "Clock rate out of range: %ld\n",
1770 if (ksz8041_fiber_mode(phydev))
1771 phydev->port = PORT_FIBRE;
1773 /* Support legacy board-file configuration */
1774 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
1775 priv->rmii_ref_clk_sel = true;
1776 priv->rmii_ref_clk_sel_val = true;
1782 static int ksz886x_cable_test_start(struct phy_device *phydev)
1784 if (phydev->dev_flags & MICREL_KSZ8_P1_ERRATA)
1787 /* If autoneg is enabled, we won't be able to test cross pair
1788 * short. In this case, the PHY will "detect" a link and
1789 * confuse the internal state machine - disable auto neg here.
1790 * If autoneg is disabled, we should set the speed to 10mbit.
1792 return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100);
1795 static int ksz886x_cable_test_result_trans(u16 status)
1797 switch (FIELD_GET(KSZ8081_LMD_STAT_MASK, status)) {
1798 case KSZ8081_LMD_STAT_NORMAL:
1799 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1800 case KSZ8081_LMD_STAT_SHORT:
1801 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1802 case KSZ8081_LMD_STAT_OPEN:
1803 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1804 case KSZ8081_LMD_STAT_FAIL:
1807 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1811 static bool ksz886x_cable_test_failed(u16 status)
1813 return FIELD_GET(KSZ8081_LMD_STAT_MASK, status) ==
1814 KSZ8081_LMD_STAT_FAIL;
1817 static bool ksz886x_cable_test_fault_length_valid(u16 status)
1819 switch (FIELD_GET(KSZ8081_LMD_STAT_MASK, status)) {
1820 case KSZ8081_LMD_STAT_OPEN:
1822 case KSZ8081_LMD_STAT_SHORT:
1828 static int ksz886x_cable_test_fault_length(u16 status)
1832 /* According to the data sheet the distance to the fault is
1833 * DELTA_TIME * 0.4 meters.
1835 dt = FIELD_GET(KSZ8081_LMD_DELTA_TIME_MASK, status);
1837 return (dt * 400) / 10;
1840 static int ksz886x_cable_test_wait_for_completion(struct phy_device *phydev)
1844 ret = phy_read_poll_timeout(phydev, KSZ8081_LMD, val,
1845 !(val & KSZ8081_LMD_ENABLE_TEST),
1846 30000, 100000, true);
1848 return ret < 0 ? ret : 0;
1851 static int ksz886x_cable_test_one_pair(struct phy_device *phydev, int pair)
1853 static const int ethtool_pair[] = {
1854 ETHTOOL_A_CABLE_PAIR_A,
1855 ETHTOOL_A_CABLE_PAIR_B,
1859 /* There is no way to choice the pair, like we do one ksz9031.
1860 * We can workaround this limitation by using the MDI-X functionality.
1865 mdix = ETH_TP_MDI_X;
1867 switch (phydev->phy_id & MICREL_PHY_ID_MASK) {
1868 case PHY_ID_KSZ8081:
1869 ret = ksz8081_config_mdix(phydev, mdix);
1871 case PHY_ID_KSZ886X:
1872 ret = ksz886x_config_mdix(phydev, mdix);
1881 /* Now we are ready to fire. This command will send a 100ns pulse
1884 ret = phy_write(phydev, KSZ8081_LMD, KSZ8081_LMD_ENABLE_TEST);
1888 ret = ksz886x_cable_test_wait_for_completion(phydev);
1892 val = phy_read(phydev, KSZ8081_LMD);
1896 if (ksz886x_cable_test_failed(val))
1899 ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
1900 ksz886x_cable_test_result_trans(val));
1904 if (!ksz886x_cable_test_fault_length_valid(val))
1907 return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
1908 ksz886x_cable_test_fault_length(val));
1911 static int ksz886x_cable_test_get_status(struct phy_device *phydev,
1914 unsigned long pair_mask = 0x3;
1920 /* Try harder if link partner is active */
1921 while (pair_mask && retries--) {
1922 for_each_set_bit(pair, &pair_mask, 4) {
1923 ret = ksz886x_cable_test_one_pair(phydev, pair);
1928 clear_bit(pair, &pair_mask);
1930 /* If link partner is in autonegotiation mode it will send 2ms
1931 * of FLPs with at least 6ms of silence.
1932 * Add 2ms sleep to have better chances to hit this silence.
1943 #define LAN_EXT_PAGE_ACCESS_CONTROL 0x16
1944 #define LAN_EXT_PAGE_ACCESS_ADDRESS_DATA 0x17
1945 #define LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC 0x4000
1947 #define LAN8814_QSGMII_SOFT_RESET 0x43
1948 #define LAN8814_QSGMII_SOFT_RESET_BIT BIT(0)
1949 #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG 0x13
1950 #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA BIT(3)
1951 #define LAN8814_ALIGN_SWAP 0x4a
1952 #define LAN8814_ALIGN_TX_A_B_SWAP 0x1
1953 #define LAN8814_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0)
1955 #define LAN8804_ALIGN_SWAP 0x4a
1956 #define LAN8804_ALIGN_TX_A_B_SWAP 0x1
1957 #define LAN8804_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0)
1958 #define LAN8814_CLOCK_MANAGEMENT 0xd
1959 #define LAN8814_LINK_QUALITY 0x8e
1961 static int lanphy_read_page_reg(struct phy_device *phydev, int page, u32 addr)
1965 phy_lock_mdio_bus(phydev);
1966 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
1967 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
1968 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
1969 (page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC));
1970 data = __phy_read(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA);
1971 phy_unlock_mdio_bus(phydev);
1976 static int lanphy_write_page_reg(struct phy_device *phydev, int page, u16 addr,
1979 phy_lock_mdio_bus(phydev);
1980 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
1981 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
1982 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
1983 page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC);
1985 val = __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val);
1987 phydev_err(phydev, "Error: phy_write has returned error %d\n",
1989 phy_unlock_mdio_bus(phydev);
1993 static int lan8814_config_ts_intr(struct phy_device *phydev, bool enable)
1998 val = PTP_TSU_INT_EN_PTP_TX_TS_EN_ |
1999 PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ |
2000 PTP_TSU_INT_EN_PTP_RX_TS_EN_ |
2001 PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_;
2003 return lanphy_write_page_reg(phydev, 5, PTP_TSU_INT_EN, val);
2006 static void lan8814_ptp_rx_ts_get(struct phy_device *phydev,
2007 u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2009 *seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_HI);
2010 *seconds = (*seconds << 16) |
2011 lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_LO);
2013 *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_HI);
2014 *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2015 lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_LO);
2017 *seq_id = lanphy_read_page_reg(phydev, 5, PTP_RX_MSG_HEADER2);
2020 static void lan8814_ptp_tx_ts_get(struct phy_device *phydev,
2021 u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2023 *seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_HI);
2024 *seconds = *seconds << 16 |
2025 lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_LO);
2027 *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_HI);
2028 *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2029 lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_LO);
2031 *seq_id = lanphy_read_page_reg(phydev, 5, PTP_TX_MSG_HEADER2);
2034 static int lan8814_ts_info(struct mii_timestamper *mii_ts, struct ethtool_ts_info *info)
2036 struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2037 struct phy_device *phydev = ptp_priv->phydev;
2038 struct lan8814_shared_priv *shared = phydev->shared->priv;
2040 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
2041 SOF_TIMESTAMPING_RX_HARDWARE |
2042 SOF_TIMESTAMPING_RAW_HARDWARE;
2044 info->phc_index = ptp_clock_index(shared->ptp_clock);
2047 (1 << HWTSTAMP_TX_OFF) |
2048 (1 << HWTSTAMP_TX_ON) |
2049 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
2052 (1 << HWTSTAMP_FILTER_NONE) |
2053 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2054 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2055 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2056 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2061 static void lan8814_flush_fifo(struct phy_device *phydev, bool egress)
2065 for (i = 0; i < FIFO_SIZE; ++i)
2066 lanphy_read_page_reg(phydev, 5,
2067 egress ? PTP_TX_MSG_HEADER2 : PTP_RX_MSG_HEADER2);
2069 /* Read to clear overflow status bit */
2070 lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
2073 static int lan8814_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)
2075 struct kszphy_ptp_priv *ptp_priv =
2076 container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2077 struct phy_device *phydev = ptp_priv->phydev;
2078 struct lan8814_shared_priv *shared = phydev->shared->priv;
2079 struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2080 struct hwtstamp_config config;
2081 int txcfg = 0, rxcfg = 0;
2084 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2087 ptp_priv->hwts_tx_type = config.tx_type;
2088 ptp_priv->rx_filter = config.rx_filter;
2090 switch (config.rx_filter) {
2091 case HWTSTAMP_FILTER_NONE:
2092 ptp_priv->layer = 0;
2093 ptp_priv->version = 0;
2095 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2096 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2097 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2098 ptp_priv->layer = PTP_CLASS_L4;
2099 ptp_priv->version = PTP_CLASS_V2;
2101 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2102 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2103 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2104 ptp_priv->layer = PTP_CLASS_L2;
2105 ptp_priv->version = PTP_CLASS_V2;
2107 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2108 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2109 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2110 ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
2111 ptp_priv->version = PTP_CLASS_V2;
2117 if (ptp_priv->layer & PTP_CLASS_L2) {
2118 rxcfg = PTP_RX_PARSE_CONFIG_LAYER2_EN_;
2119 txcfg = PTP_TX_PARSE_CONFIG_LAYER2_EN_;
2120 } else if (ptp_priv->layer & PTP_CLASS_L4) {
2121 rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
2122 txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
2124 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_PARSE_CONFIG, rxcfg);
2125 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_PARSE_CONFIG, txcfg);
2127 pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
2128 PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
2129 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
2130 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
2132 if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC)
2133 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
2134 PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
2136 if (config.rx_filter != HWTSTAMP_FILTER_NONE)
2137 lan8814_config_ts_intr(ptp_priv->phydev, true);
2139 lan8814_config_ts_intr(ptp_priv->phydev, false);
2141 mutex_lock(&shared->shared_lock);
2142 if (config.rx_filter != HWTSTAMP_FILTER_NONE)
2148 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
2149 PTP_CMD_CTL_PTP_ENABLE_);
2151 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
2152 PTP_CMD_CTL_PTP_DISABLE_);
2153 mutex_unlock(&shared->shared_lock);
2155 /* In case of multiple starts and stops, these needs to be cleared */
2156 list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2157 list_del(&rx_ts->list);
2160 skb_queue_purge(&ptp_priv->rx_queue);
2161 skb_queue_purge(&ptp_priv->tx_queue);
2163 lan8814_flush_fifo(ptp_priv->phydev, false);
2164 lan8814_flush_fifo(ptp_priv->phydev, true);
2166 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? -EFAULT : 0;
2169 static void lan8814_txtstamp(struct mii_timestamper *mii_ts,
2170 struct sk_buff *skb, int type)
2172 struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2174 switch (ptp_priv->hwts_tx_type) {
2175 case HWTSTAMP_TX_ONESTEP_SYNC:
2176 if (ptp_msg_is_sync(skb, type)) {
2181 case HWTSTAMP_TX_ON:
2182 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2183 skb_queue_tail(&ptp_priv->tx_queue, skb);
2185 case HWTSTAMP_TX_OFF:
2192 static void lan8814_get_sig_rx(struct sk_buff *skb, u16 *sig)
2194 struct ptp_header *ptp_header;
2197 skb_push(skb, ETH_HLEN);
2198 type = ptp_classify_raw(skb);
2199 ptp_header = ptp_parse_header(skb, type);
2200 skb_pull_inline(skb, ETH_HLEN);
2202 *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2205 static bool lan8814_match_rx_ts(struct kszphy_ptp_priv *ptp_priv,
2206 struct sk_buff *skb)
2208 struct skb_shared_hwtstamps *shhwtstamps;
2209 struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2210 unsigned long flags;
2214 lan8814_get_sig_rx(skb, &skb_sig);
2216 /* Iterate over all RX timestamps and match it with the received skbs */
2217 spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2218 list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2219 /* Check if we found the signature we were looking for. */
2220 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2223 shhwtstamps = skb_hwtstamps(skb);
2224 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2225 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds,
2227 list_del(&rx_ts->list);
2233 spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2240 static bool lan8814_rxtstamp(struct mii_timestamper *mii_ts, struct sk_buff *skb, int type)
2242 struct kszphy_ptp_priv *ptp_priv =
2243 container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2245 if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
2246 type == PTP_CLASS_NONE)
2249 if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
2252 /* If we failed to match then add it to the queue for when the timestamp
2255 if (!lan8814_match_rx_ts(ptp_priv, skb))
2256 skb_queue_tail(&ptp_priv->rx_queue, skb);
2261 static void lan8814_ptp_clock_set(struct phy_device *phydev,
2262 u32 seconds, u32 nano_seconds)
2264 u32 sec_low, sec_high, nsec_low, nsec_high;
2266 sec_low = seconds & 0xffff;
2267 sec_high = (seconds >> 16) & 0xffff;
2268 nsec_low = nano_seconds & 0xffff;
2269 nsec_high = (nano_seconds >> 16) & 0x3fff;
2271 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_LO, sec_low);
2272 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_MID, sec_high);
2273 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_LO, nsec_low);
2274 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_HI, nsec_high);
2276 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_LOAD_);
2279 static void lan8814_ptp_clock_get(struct phy_device *phydev,
2280 u32 *seconds, u32 *nano_seconds)
2282 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_READ_);
2284 *seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_MID);
2285 *seconds = (*seconds << 16) |
2286 lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_LO);
2288 *nano_seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_HI);
2289 *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2290 lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_LO);
2293 static int lan8814_ptpci_gettime64(struct ptp_clock_info *ptpci,
2294 struct timespec64 *ts)
2296 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2298 struct phy_device *phydev = shared->phydev;
2302 mutex_lock(&shared->shared_lock);
2303 lan8814_ptp_clock_get(phydev, &seconds, &nano_seconds);
2304 mutex_unlock(&shared->shared_lock);
2305 ts->tv_sec = seconds;
2306 ts->tv_nsec = nano_seconds;
2311 static int lan8814_ptpci_settime64(struct ptp_clock_info *ptpci,
2312 const struct timespec64 *ts)
2314 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2316 struct phy_device *phydev = shared->phydev;
2318 mutex_lock(&shared->shared_lock);
2319 lan8814_ptp_clock_set(phydev, ts->tv_sec, ts->tv_nsec);
2320 mutex_unlock(&shared->shared_lock);
2325 static void lan8814_ptp_clock_step(struct phy_device *phydev,
2328 u32 nano_seconds_step;
2329 u64 abs_time_step_ns;
2330 u32 unsigned_seconds;
2335 if (time_step_ns > 15000000000LL) {
2336 /* convert to clock set */
2337 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2338 unsigned_seconds += div_u64_rem(time_step_ns, 1000000000LL,
2340 nano_seconds += remainder;
2341 if (nano_seconds >= 1000000000) {
2343 nano_seconds -= 1000000000;
2345 lan8814_ptp_clock_set(phydev, unsigned_seconds, nano_seconds);
2347 } else if (time_step_ns < -15000000000LL) {
2348 /* convert to clock set */
2349 time_step_ns = -time_step_ns;
2351 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2352 unsigned_seconds -= div_u64_rem(time_step_ns, 1000000000LL,
2354 nano_seconds_step = remainder;
2355 if (nano_seconds < nano_seconds_step) {
2357 nano_seconds += 1000000000;
2359 nano_seconds -= nano_seconds_step;
2360 lan8814_ptp_clock_set(phydev, unsigned_seconds,
2366 if (time_step_ns >= 0) {
2367 abs_time_step_ns = (u64)time_step_ns;
2368 seconds = (s32)div_u64_rem(abs_time_step_ns, 1000000000,
2370 nano_seconds = remainder;
2372 abs_time_step_ns = (u64)(-time_step_ns);
2373 seconds = -((s32)div_u64_rem(abs_time_step_ns, 1000000000,
2375 nano_seconds = remainder;
2376 if (nano_seconds > 0) {
2377 /* subtracting nano seconds is not allowed
2378 * convert to subtracting from seconds,
2379 * and adding to nanoseconds
2382 nano_seconds = (1000000000 - nano_seconds);
2386 if (nano_seconds > 0) {
2387 /* add 8 ns to cover the likely normal increment */
2391 if (nano_seconds >= 1000000000) {
2392 /* carry into seconds */
2394 nano_seconds -= 1000000000;
2399 u32 adjustment_value = (u32)seconds;
2400 u16 adjustment_value_lo, adjustment_value_hi;
2402 if (adjustment_value > 0xF)
2403 adjustment_value = 0xF;
2405 adjustment_value_lo = adjustment_value & 0xffff;
2406 adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2408 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2409 adjustment_value_lo);
2410 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2411 PTP_LTC_STEP_ADJ_DIR_ |
2412 adjustment_value_hi);
2413 seconds -= ((s32)adjustment_value);
2415 u32 adjustment_value = (u32)(-seconds);
2416 u16 adjustment_value_lo, adjustment_value_hi;
2418 if (adjustment_value > 0xF)
2419 adjustment_value = 0xF;
2421 adjustment_value_lo = adjustment_value & 0xffff;
2422 adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2424 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2425 adjustment_value_lo);
2426 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2427 adjustment_value_hi);
2428 seconds += ((s32)adjustment_value);
2430 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2431 PTP_CMD_CTL_PTP_LTC_STEP_SEC_);
2434 u16 nano_seconds_lo;
2435 u16 nano_seconds_hi;
2437 nano_seconds_lo = nano_seconds & 0xffff;
2438 nano_seconds_hi = (nano_seconds >> 16) & 0x3fff;
2440 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2442 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2443 PTP_LTC_STEP_ADJ_DIR_ |
2445 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2446 PTP_CMD_CTL_PTP_LTC_STEP_NSEC_);
2450 static int lan8814_ptpci_adjtime(struct ptp_clock_info *ptpci, s64 delta)
2452 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2454 struct phy_device *phydev = shared->phydev;
2456 mutex_lock(&shared->shared_lock);
2457 lan8814_ptp_clock_step(phydev, delta);
2458 mutex_unlock(&shared->shared_lock);
2463 static int lan8814_ptpci_adjfine(struct ptp_clock_info *ptpci, long scaled_ppm)
2465 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2467 struct phy_device *phydev = shared->phydev;
2468 u16 kszphy_rate_adj_lo, kszphy_rate_adj_hi;
2469 bool positive = true;
2470 u32 kszphy_rate_adj;
2472 if (scaled_ppm < 0) {
2473 scaled_ppm = -scaled_ppm;
2477 kszphy_rate_adj = LAN8814_1PPM_FORMAT * (scaled_ppm >> 16);
2478 kszphy_rate_adj += (LAN8814_1PPM_FORMAT * (0xffff & scaled_ppm)) >> 16;
2480 kszphy_rate_adj_lo = kszphy_rate_adj & 0xffff;
2481 kszphy_rate_adj_hi = (kszphy_rate_adj >> 16) & 0x3fff;
2484 kszphy_rate_adj_hi |= PTP_CLOCK_RATE_ADJ_DIR_;
2486 mutex_lock(&shared->shared_lock);
2487 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_HI, kszphy_rate_adj_hi);
2488 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_LO, kszphy_rate_adj_lo);
2489 mutex_unlock(&shared->shared_lock);
2494 static void lan8814_get_sig_tx(struct sk_buff *skb, u16 *sig)
2496 struct ptp_header *ptp_header;
2499 type = ptp_classify_raw(skb);
2500 ptp_header = ptp_parse_header(skb, type);
2502 *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2505 static void lan8814_dequeue_tx_skb(struct kszphy_ptp_priv *ptp_priv)
2507 struct phy_device *phydev = ptp_priv->phydev;
2508 struct skb_shared_hwtstamps shhwtstamps;
2509 struct sk_buff *skb, *skb_tmp;
2510 unsigned long flags;
2516 lan8814_ptp_tx_ts_get(phydev, &seconds, &nsec, &seq_id);
2518 spin_lock_irqsave(&ptp_priv->tx_queue.lock, flags);
2519 skb_queue_walk_safe(&ptp_priv->tx_queue, skb, skb_tmp) {
2520 lan8814_get_sig_tx(skb, &skb_sig);
2522 if (memcmp(&skb_sig, &seq_id, sizeof(seq_id)))
2525 __skb_unlink(skb, &ptp_priv->tx_queue);
2529 spin_unlock_irqrestore(&ptp_priv->tx_queue.lock, flags);
2532 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2533 shhwtstamps.hwtstamp = ktime_set(seconds, nsec);
2534 skb_complete_tx_timestamp(skb, &shhwtstamps);
2538 static void lan8814_get_tx_ts(struct kszphy_ptp_priv *ptp_priv)
2540 struct phy_device *phydev = ptp_priv->phydev;
2544 lan8814_dequeue_tx_skb(ptp_priv);
2546 /* If other timestamps are available in the FIFO,
2549 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2550 } while (PTP_CAP_INFO_TX_TS_CNT_GET_(reg) > 0);
2553 static bool lan8814_match_skb(struct kszphy_ptp_priv *ptp_priv,
2554 struct lan8814_ptp_rx_ts *rx_ts)
2556 struct skb_shared_hwtstamps *shhwtstamps;
2557 struct sk_buff *skb, *skb_tmp;
2558 unsigned long flags;
2562 spin_lock_irqsave(&ptp_priv->rx_queue.lock, flags);
2563 skb_queue_walk_safe(&ptp_priv->rx_queue, skb, skb_tmp) {
2564 lan8814_get_sig_rx(skb, &skb_sig);
2566 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2569 __skb_unlink(skb, &ptp_priv->rx_queue);
2574 spin_unlock_irqrestore(&ptp_priv->rx_queue.lock, flags);
2577 shhwtstamps = skb_hwtstamps(skb);
2578 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2579 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds, rx_ts->nsec);
2586 static void lan8814_get_rx_ts(struct kszphy_ptp_priv *ptp_priv)
2588 struct phy_device *phydev = ptp_priv->phydev;
2589 struct lan8814_ptp_rx_ts *rx_ts;
2590 unsigned long flags;
2594 rx_ts = kzalloc(sizeof(*rx_ts), GFP_KERNEL);
2598 lan8814_ptp_rx_ts_get(phydev, &rx_ts->seconds, &rx_ts->nsec,
2601 /* If we failed to match the skb add it to the queue for when
2602 * the frame will come
2604 if (!lan8814_match_skb(ptp_priv, rx_ts)) {
2605 spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2606 list_add(&rx_ts->list, &ptp_priv->rx_ts_list);
2607 spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2612 /* If other timestamps are available in the FIFO,
2615 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2616 } while (PTP_CAP_INFO_RX_TS_CNT_GET_(reg) > 0);
2619 static void lan8814_handle_ptp_interrupt(struct phy_device *phydev)
2621 struct kszphy_priv *priv = phydev->priv;
2622 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
2625 status = lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
2626 if (status & PTP_TSU_INT_STS_PTP_TX_TS_EN_)
2627 lan8814_get_tx_ts(ptp_priv);
2629 if (status & PTP_TSU_INT_STS_PTP_RX_TS_EN_)
2630 lan8814_get_rx_ts(ptp_priv);
2632 if (status & PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_) {
2633 lan8814_flush_fifo(phydev, true);
2634 skb_queue_purge(&ptp_priv->tx_queue);
2637 if (status & PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_) {
2638 lan8814_flush_fifo(phydev, false);
2639 skb_queue_purge(&ptp_priv->rx_queue);
2643 static int lan8804_config_init(struct phy_device *phydev)
2647 /* MDI-X setting for swap A,B transmit */
2648 val = lanphy_read_page_reg(phydev, 2, LAN8804_ALIGN_SWAP);
2649 val &= ~LAN8804_ALIGN_TX_A_B_SWAP_MASK;
2650 val |= LAN8804_ALIGN_TX_A_B_SWAP;
2651 lanphy_write_page_reg(phydev, 2, LAN8804_ALIGN_SWAP, val);
2653 /* Make sure that the PHY will not stop generating the clock when the
2654 * link partner goes down
2656 lanphy_write_page_reg(phydev, 31, LAN8814_CLOCK_MANAGEMENT, 0x27e);
2657 lanphy_read_page_reg(phydev, 1, LAN8814_LINK_QUALITY);
2662 static irqreturn_t lan8814_handle_interrupt(struct phy_device *phydev)
2664 int irq_status, tsu_irq_status;
2666 irq_status = phy_read(phydev, LAN8814_INTS);
2667 if (irq_status > 0 && (irq_status & LAN8814_INT_LINK))
2668 phy_trigger_machine(phydev);
2670 if (irq_status < 0) {
2676 tsu_irq_status = lanphy_read_page_reg(phydev, 4,
2677 LAN8814_INTR_STS_REG);
2679 if (tsu_irq_status > 0 &&
2680 (tsu_irq_status & (LAN8814_INTR_STS_REG_1588_TSU0_ |
2681 LAN8814_INTR_STS_REG_1588_TSU1_ |
2682 LAN8814_INTR_STS_REG_1588_TSU2_ |
2683 LAN8814_INTR_STS_REG_1588_TSU3_)))
2684 lan8814_handle_ptp_interrupt(phydev);
2691 static int lan8814_ack_interrupt(struct phy_device *phydev)
2693 /* bit[12..0] int status, which is a read and clear register. */
2696 rc = phy_read(phydev, LAN8814_INTS);
2698 return (rc < 0) ? rc : 0;
2701 static int lan8814_config_intr(struct phy_device *phydev)
2705 lanphy_write_page_reg(phydev, 4, LAN8814_INTR_CTRL_REG,
2706 LAN8814_INTR_CTRL_REG_POLARITY |
2707 LAN8814_INTR_CTRL_REG_INTR_ENABLE);
2709 /* enable / disable interrupts */
2710 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
2711 err = lan8814_ack_interrupt(phydev);
2715 err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
2717 err = phy_write(phydev, LAN8814_INTC, 0);
2721 err = lan8814_ack_interrupt(phydev);
2727 static void lan8814_ptp_init(struct phy_device *phydev)
2729 struct kszphy_priv *priv = phydev->priv;
2730 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
2733 if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) ||
2734 !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
2737 lanphy_write_page_reg(phydev, 5, TSU_HARD_RESET, TSU_HARD_RESET_);
2739 temp = lanphy_read_page_reg(phydev, 5, PTP_TX_MOD);
2740 temp |= PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
2741 lanphy_write_page_reg(phydev, 5, PTP_TX_MOD, temp);
2743 temp = lanphy_read_page_reg(phydev, 5, PTP_RX_MOD);
2744 temp |= PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
2745 lanphy_write_page_reg(phydev, 5, PTP_RX_MOD, temp);
2747 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_CONFIG, 0);
2748 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_CONFIG, 0);
2750 /* Removing default registers configs related to L2 and IP */
2751 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_L2_ADDR_EN, 0);
2752 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_L2_ADDR_EN, 0);
2753 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_IP_ADDR_EN, 0);
2754 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_IP_ADDR_EN, 0);
2756 skb_queue_head_init(&ptp_priv->tx_queue);
2757 skb_queue_head_init(&ptp_priv->rx_queue);
2758 INIT_LIST_HEAD(&ptp_priv->rx_ts_list);
2759 spin_lock_init(&ptp_priv->rx_ts_lock);
2761 ptp_priv->phydev = phydev;
2763 ptp_priv->mii_ts.rxtstamp = lan8814_rxtstamp;
2764 ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
2765 ptp_priv->mii_ts.hwtstamp = lan8814_hwtstamp;
2766 ptp_priv->mii_ts.ts_info = lan8814_ts_info;
2768 phydev->mii_ts = &ptp_priv->mii_ts;
2771 static int lan8814_ptp_probe_once(struct phy_device *phydev)
2773 struct lan8814_shared_priv *shared = phydev->shared->priv;
2775 if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) ||
2776 !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
2779 /* Initialise shared lock for clock*/
2780 mutex_init(&shared->shared_lock);
2782 shared->ptp_clock_info.owner = THIS_MODULE;
2783 snprintf(shared->ptp_clock_info.name, 30, "%s", phydev->drv->name);
2784 shared->ptp_clock_info.max_adj = 31249999;
2785 shared->ptp_clock_info.n_alarm = 0;
2786 shared->ptp_clock_info.n_ext_ts = 0;
2787 shared->ptp_clock_info.n_pins = 0;
2788 shared->ptp_clock_info.pps = 0;
2789 shared->ptp_clock_info.pin_config = NULL;
2790 shared->ptp_clock_info.adjfine = lan8814_ptpci_adjfine;
2791 shared->ptp_clock_info.adjtime = lan8814_ptpci_adjtime;
2792 shared->ptp_clock_info.gettime64 = lan8814_ptpci_gettime64;
2793 shared->ptp_clock_info.settime64 = lan8814_ptpci_settime64;
2794 shared->ptp_clock_info.getcrosststamp = NULL;
2796 shared->ptp_clock = ptp_clock_register(&shared->ptp_clock_info,
2798 if (IS_ERR_OR_NULL(shared->ptp_clock)) {
2799 phydev_err(phydev, "ptp_clock_register failed %lu\n",
2800 PTR_ERR(shared->ptp_clock));
2804 phydev_dbg(phydev, "successfully registered ptp clock\n");
2806 shared->phydev = phydev;
2808 /* The EP.4 is shared between all the PHYs in the package and also it
2809 * can be accessed by any of the PHYs
2811 lanphy_write_page_reg(phydev, 4, LTC_HARD_RESET, LTC_HARD_RESET_);
2812 lanphy_write_page_reg(phydev, 4, PTP_OPERATING_MODE,
2813 PTP_OPERATING_MODE_STANDALONE_);
2818 static int lan8814_config_init(struct phy_device *phydev)
2823 val = lanphy_read_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET);
2824 val |= LAN8814_QSGMII_SOFT_RESET_BIT;
2825 lanphy_write_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET, val);
2827 /* Disable ANEG with QSGMII PCS Host side */
2828 val = lanphy_read_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG);
2829 val &= ~LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA;
2830 lanphy_write_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, val);
2832 /* MDI-X setting for swap A,B transmit */
2833 val = lanphy_read_page_reg(phydev, 2, LAN8814_ALIGN_SWAP);
2834 val &= ~LAN8814_ALIGN_TX_A_B_SWAP_MASK;
2835 val |= LAN8814_ALIGN_TX_A_B_SWAP;
2836 lanphy_write_page_reg(phydev, 2, LAN8814_ALIGN_SWAP, val);
2841 /* It is expected that there will not be any 'lan8814_take_coma_mode'
2842 * function called in suspend. Because the GPIO line can be shared, so if one of
2843 * the phys goes back in coma mode, then all the other PHYs will go, which is
2846 static int lan8814_release_coma_mode(struct phy_device *phydev)
2848 struct gpio_desc *gpiod;
2850 gpiod = devm_gpiod_get_optional(&phydev->mdio.dev, "coma-mode",
2851 GPIOD_OUT_HIGH_OPEN_DRAIN |
2852 GPIOD_FLAGS_BIT_NONEXCLUSIVE);
2854 return PTR_ERR(gpiod);
2856 gpiod_set_consumer_name(gpiod, "LAN8814 coma mode");
2857 gpiod_set_value_cansleep(gpiod, 0);
2862 static int lan8814_probe(struct phy_device *phydev)
2864 struct kszphy_priv *priv;
2868 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
2872 priv->led_mode = -1;
2874 phydev->priv = priv;
2876 /* Strap-in value for PHY address, below register read gives starting
2879 addr = lanphy_read_page_reg(phydev, 4, 0) & 0x1F;
2880 devm_phy_package_join(&phydev->mdio.dev, phydev,
2881 addr, sizeof(struct lan8814_shared_priv));
2883 if (phy_package_init_once(phydev)) {
2884 err = lan8814_release_coma_mode(phydev);
2888 err = lan8814_ptp_probe_once(phydev);
2893 lan8814_ptp_init(phydev);
2898 static struct phy_driver ksphy_driver[] = {
2900 .phy_id = PHY_ID_KS8737,
2901 .phy_id_mask = MICREL_PHY_ID_MASK,
2902 .name = "Micrel KS8737",
2903 /* PHY_BASIC_FEATURES */
2904 .driver_data = &ks8737_type,
2905 .probe = kszphy_probe,
2906 .config_init = kszphy_config_init,
2907 .config_intr = kszphy_config_intr,
2908 .handle_interrupt = kszphy_handle_interrupt,
2909 .suspend = kszphy_suspend,
2910 .resume = kszphy_resume,
2912 .phy_id = PHY_ID_KSZ8021,
2913 .phy_id_mask = 0x00ffffff,
2914 .name = "Micrel KSZ8021 or KSZ8031",
2915 /* PHY_BASIC_FEATURES */
2916 .driver_data = &ksz8021_type,
2917 .probe = kszphy_probe,
2918 .config_init = kszphy_config_init,
2919 .config_intr = kszphy_config_intr,
2920 .handle_interrupt = kszphy_handle_interrupt,
2921 .get_sset_count = kszphy_get_sset_count,
2922 .get_strings = kszphy_get_strings,
2923 .get_stats = kszphy_get_stats,
2924 .suspend = kszphy_suspend,
2925 .resume = kszphy_resume,
2927 .phy_id = PHY_ID_KSZ8031,
2928 .phy_id_mask = 0x00ffffff,
2929 .name = "Micrel KSZ8031",
2930 /* PHY_BASIC_FEATURES */
2931 .driver_data = &ksz8021_type,
2932 .probe = kszphy_probe,
2933 .config_init = kszphy_config_init,
2934 .config_intr = kszphy_config_intr,
2935 .handle_interrupt = kszphy_handle_interrupt,
2936 .get_sset_count = kszphy_get_sset_count,
2937 .get_strings = kszphy_get_strings,
2938 .get_stats = kszphy_get_stats,
2939 .suspend = kszphy_suspend,
2940 .resume = kszphy_resume,
2942 .phy_id = PHY_ID_KSZ8041,
2943 .phy_id_mask = MICREL_PHY_ID_MASK,
2944 .name = "Micrel KSZ8041",
2945 /* PHY_BASIC_FEATURES */
2946 .driver_data = &ksz8041_type,
2947 .probe = kszphy_probe,
2948 .config_init = ksz8041_config_init,
2949 .config_aneg = ksz8041_config_aneg,
2950 .config_intr = kszphy_config_intr,
2951 .handle_interrupt = kszphy_handle_interrupt,
2952 .get_sset_count = kszphy_get_sset_count,
2953 .get_strings = kszphy_get_strings,
2954 .get_stats = kszphy_get_stats,
2955 /* No suspend/resume callbacks because of errata DS80000700A,
2956 * receiver error following software power down.
2959 .phy_id = PHY_ID_KSZ8041RNLI,
2960 .phy_id_mask = MICREL_PHY_ID_MASK,
2961 .name = "Micrel KSZ8041RNLI",
2962 /* PHY_BASIC_FEATURES */
2963 .driver_data = &ksz8041_type,
2964 .probe = kszphy_probe,
2965 .config_init = kszphy_config_init,
2966 .config_intr = kszphy_config_intr,
2967 .handle_interrupt = kszphy_handle_interrupt,
2968 .get_sset_count = kszphy_get_sset_count,
2969 .get_strings = kszphy_get_strings,
2970 .get_stats = kszphy_get_stats,
2971 .suspend = kszphy_suspend,
2972 .resume = kszphy_resume,
2974 .name = "Micrel KSZ8051",
2975 /* PHY_BASIC_FEATURES */
2976 .driver_data = &ksz8051_type,
2977 .probe = kszphy_probe,
2978 .config_init = kszphy_config_init,
2979 .config_intr = kszphy_config_intr,
2980 .handle_interrupt = kszphy_handle_interrupt,
2981 .get_sset_count = kszphy_get_sset_count,
2982 .get_strings = kszphy_get_strings,
2983 .get_stats = kszphy_get_stats,
2984 .match_phy_device = ksz8051_match_phy_device,
2985 .suspend = kszphy_suspend,
2986 .resume = kszphy_resume,
2988 .phy_id = PHY_ID_KSZ8001,
2989 .name = "Micrel KSZ8001 or KS8721",
2990 .phy_id_mask = 0x00fffffc,
2991 /* PHY_BASIC_FEATURES */
2992 .driver_data = &ksz8041_type,
2993 .probe = kszphy_probe,
2994 .config_init = kszphy_config_init,
2995 .config_intr = kszphy_config_intr,
2996 .handle_interrupt = kszphy_handle_interrupt,
2997 .get_sset_count = kszphy_get_sset_count,
2998 .get_strings = kszphy_get_strings,
2999 .get_stats = kszphy_get_stats,
3000 .suspend = kszphy_suspend,
3001 .resume = kszphy_resume,
3003 .phy_id = PHY_ID_KSZ8081,
3004 .name = "Micrel KSZ8081 or KSZ8091",
3005 .phy_id_mask = MICREL_PHY_ID_MASK,
3006 .flags = PHY_POLL_CABLE_TEST,
3007 /* PHY_BASIC_FEATURES */
3008 .driver_data = &ksz8081_type,
3009 .probe = kszphy_probe,
3010 .config_init = ksz8081_config_init,
3011 .soft_reset = genphy_soft_reset,
3012 .config_aneg = ksz8081_config_aneg,
3013 .read_status = ksz8081_read_status,
3014 .config_intr = kszphy_config_intr,
3015 .handle_interrupt = kszphy_handle_interrupt,
3016 .get_sset_count = kszphy_get_sset_count,
3017 .get_strings = kszphy_get_strings,
3018 .get_stats = kszphy_get_stats,
3019 .suspend = kszphy_suspend,
3020 .resume = kszphy_resume,
3021 .cable_test_start = ksz886x_cable_test_start,
3022 .cable_test_get_status = ksz886x_cable_test_get_status,
3024 .phy_id = PHY_ID_KSZ8061,
3025 .name = "Micrel KSZ8061",
3026 .phy_id_mask = MICREL_PHY_ID_MASK,
3027 /* PHY_BASIC_FEATURES */
3028 .probe = kszphy_probe,
3029 .config_init = ksz8061_config_init,
3030 .config_intr = kszphy_config_intr,
3031 .handle_interrupt = kszphy_handle_interrupt,
3032 .suspend = kszphy_suspend,
3033 .resume = kszphy_resume,
3035 .phy_id = PHY_ID_KSZ9021,
3036 .phy_id_mask = 0x000ffffe,
3037 .name = "Micrel KSZ9021 Gigabit PHY",
3038 /* PHY_GBIT_FEATURES */
3039 .driver_data = &ksz9021_type,
3040 .probe = kszphy_probe,
3041 .get_features = ksz9031_get_features,
3042 .config_init = ksz9021_config_init,
3043 .config_intr = kszphy_config_intr,
3044 .handle_interrupt = kszphy_handle_interrupt,
3045 .get_sset_count = kszphy_get_sset_count,
3046 .get_strings = kszphy_get_strings,
3047 .get_stats = kszphy_get_stats,
3048 .suspend = kszphy_suspend,
3049 .resume = kszphy_resume,
3050 .read_mmd = genphy_read_mmd_unsupported,
3051 .write_mmd = genphy_write_mmd_unsupported,
3053 .phy_id = PHY_ID_KSZ9031,
3054 .phy_id_mask = MICREL_PHY_ID_MASK,
3055 .name = "Micrel KSZ9031 Gigabit PHY",
3056 .flags = PHY_POLL_CABLE_TEST,
3057 .driver_data = &ksz9021_type,
3058 .probe = kszphy_probe,
3059 .get_features = ksz9031_get_features,
3060 .config_init = ksz9031_config_init,
3061 .soft_reset = genphy_soft_reset,
3062 .read_status = ksz9031_read_status,
3063 .config_intr = kszphy_config_intr,
3064 .handle_interrupt = kszphy_handle_interrupt,
3065 .get_sset_count = kszphy_get_sset_count,
3066 .get_strings = kszphy_get_strings,
3067 .get_stats = kszphy_get_stats,
3068 .suspend = kszphy_suspend,
3069 .resume = kszphy_resume,
3070 .cable_test_start = ksz9x31_cable_test_start,
3071 .cable_test_get_status = ksz9x31_cable_test_get_status,
3073 .phy_id = PHY_ID_LAN8814,
3074 .phy_id_mask = MICREL_PHY_ID_MASK,
3075 .name = "Microchip INDY Gigabit Quad PHY",
3076 .config_init = lan8814_config_init,
3077 .probe = lan8814_probe,
3078 .soft_reset = genphy_soft_reset,
3079 .read_status = ksz9031_read_status,
3080 .get_sset_count = kszphy_get_sset_count,
3081 .get_strings = kszphy_get_strings,
3082 .get_stats = kszphy_get_stats,
3083 .suspend = genphy_suspend,
3084 .resume = kszphy_resume,
3085 .config_intr = lan8814_config_intr,
3086 .handle_interrupt = lan8814_handle_interrupt,
3088 .phy_id = PHY_ID_LAN8804,
3089 .phy_id_mask = MICREL_PHY_ID_MASK,
3090 .name = "Microchip LAN966X Gigabit PHY",
3091 .config_init = lan8804_config_init,
3092 .driver_data = &ksz9021_type,
3093 .probe = kszphy_probe,
3094 .soft_reset = genphy_soft_reset,
3095 .read_status = ksz9031_read_status,
3096 .get_sset_count = kszphy_get_sset_count,
3097 .get_strings = kszphy_get_strings,
3098 .get_stats = kszphy_get_stats,
3099 .suspend = genphy_suspend,
3100 .resume = kszphy_resume,
3102 .phy_id = PHY_ID_KSZ9131,
3103 .phy_id_mask = MICREL_PHY_ID_MASK,
3104 .name = "Microchip KSZ9131 Gigabit PHY",
3105 /* PHY_GBIT_FEATURES */
3106 .flags = PHY_POLL_CABLE_TEST,
3107 .driver_data = &ksz9021_type,
3108 .probe = kszphy_probe,
3109 .config_init = ksz9131_config_init,
3110 .config_intr = kszphy_config_intr,
3111 .handle_interrupt = kszphy_handle_interrupt,
3112 .get_sset_count = kszphy_get_sset_count,
3113 .get_strings = kszphy_get_strings,
3114 .get_stats = kszphy_get_stats,
3115 .suspend = kszphy_suspend,
3116 .resume = kszphy_resume,
3117 .cable_test_start = ksz9x31_cable_test_start,
3118 .cable_test_get_status = ksz9x31_cable_test_get_status,
3120 .phy_id = PHY_ID_KSZ8873MLL,
3121 .phy_id_mask = MICREL_PHY_ID_MASK,
3122 .name = "Micrel KSZ8873MLL Switch",
3123 /* PHY_BASIC_FEATURES */
3124 .config_init = kszphy_config_init,
3125 .config_aneg = ksz8873mll_config_aneg,
3126 .read_status = ksz8873mll_read_status,
3127 .suspend = genphy_suspend,
3128 .resume = genphy_resume,
3130 .phy_id = PHY_ID_KSZ886X,
3131 .phy_id_mask = MICREL_PHY_ID_MASK,
3132 .name = "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch",
3133 /* PHY_BASIC_FEATURES */
3134 .flags = PHY_POLL_CABLE_TEST,
3135 .config_init = kszphy_config_init,
3136 .config_aneg = ksz886x_config_aneg,
3137 .read_status = ksz886x_read_status,
3138 .suspend = genphy_suspend,
3139 .resume = genphy_resume,
3140 .cable_test_start = ksz886x_cable_test_start,
3141 .cable_test_get_status = ksz886x_cable_test_get_status,
3143 .name = "Micrel KSZ87XX Switch",
3144 /* PHY_BASIC_FEATURES */
3145 .config_init = kszphy_config_init,
3146 .match_phy_device = ksz8795_match_phy_device,
3147 .suspend = genphy_suspend,
3148 .resume = genphy_resume,
3150 .phy_id = PHY_ID_KSZ9477,
3151 .phy_id_mask = MICREL_PHY_ID_MASK,
3152 .name = "Microchip KSZ9477",
3153 /* PHY_GBIT_FEATURES */
3154 .config_init = kszphy_config_init,
3155 .suspend = genphy_suspend,
3156 .resume = genphy_resume,
3159 module_phy_driver(ksphy_driver);
3161 MODULE_DESCRIPTION("Micrel PHY driver");
3162 MODULE_AUTHOR("David J. Choi");
3163 MODULE_LICENSE("GPL");
3165 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
3166 { PHY_ID_KSZ9021, 0x000ffffe },
3167 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
3168 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
3169 { PHY_ID_KSZ8001, 0x00fffffc },
3170 { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
3171 { PHY_ID_KSZ8021, 0x00ffffff },
3172 { PHY_ID_KSZ8031, 0x00ffffff },
3173 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
3174 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
3175 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
3176 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
3177 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
3178 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
3179 { PHY_ID_LAN8814, MICREL_PHY_ID_MASK },
3180 { PHY_ID_LAN8804, MICREL_PHY_ID_MASK },
3184 MODULE_DEVICE_TABLE(mdio, micrel_tbl);