git.itanic.dy.fi Git - linux-stable/blob - drivers/net/phy/micrel.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/net/phy/micrel.c
   4  *
   5  * Driver for Micrel PHYs
   6  *
   7  * Author: David J. Choi
   8  *
   9  * Copyright (c) 2010-2013 Micrel, Inc.
  10  * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
  11  *
  12  * Support : Micrel Phys:
  13  *              Giga phys: ksz9021, ksz9031, ksz9131
  14  *              100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
  15  *                         ksz8021, ksz8031, ksz8051,
  16  *                         ksz8081, ksz8091,
  17  *                         ksz8061,
  18  *              Switch : ksz8873, ksz886x
  19  *                       ksz9477
  20  */
  21
  22 #include <linux/bitfield.h>
  23 #include <linux/ethtool_netlink.h>
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/phy.h>
  27 #include <linux/micrel_phy.h>
  28 #include <linux/of.h>
  29 #include <linux/clk.h>
  30 #include <linux/delay.h>
  31 #include <linux/ptp_clock_kernel.h>
  32 #include <linux/ptp_clock.h>
  33 #include <linux/ptp_classify.h>
  34 #include <linux/net_tstamp.h>
  35 #include <linux/gpio/consumer.h>
  36
  37 /* Operation Mode Strap Override */
  38 #define MII_KSZPHY_OMSO                         0x16
  39 #define KSZPHY_OMSO_FACTORY_TEST                BIT(15)
  40 #define KSZPHY_OMSO_B_CAST_OFF                  BIT(9)
  41 #define KSZPHY_OMSO_NAND_TREE_ON                BIT(5)
  42 #define KSZPHY_OMSO_RMII_OVERRIDE               BIT(1)
  43 #define KSZPHY_OMSO_MII_OVERRIDE                BIT(0)
  44
  45 /* general Interrupt control/status reg in vendor specific block. */
  46 #define MII_KSZPHY_INTCS                        0x1B
  47 #define KSZPHY_INTCS_JABBER                     BIT(15)
  48 #define KSZPHY_INTCS_RECEIVE_ERR                BIT(14)
  49 #define KSZPHY_INTCS_PAGE_RECEIVE               BIT(13)
  50 #define KSZPHY_INTCS_PARELLEL                   BIT(12)
  51 #define KSZPHY_INTCS_LINK_PARTNER_ACK           BIT(11)
  52 #define KSZPHY_INTCS_LINK_DOWN                  BIT(10)
  53 #define KSZPHY_INTCS_REMOTE_FAULT               BIT(9)
  54 #define KSZPHY_INTCS_LINK_UP                    BIT(8)
  55 #define KSZPHY_INTCS_ALL                        (KSZPHY_INTCS_LINK_UP |\
  56                                                 KSZPHY_INTCS_LINK_DOWN)
  57 #define KSZPHY_INTCS_LINK_DOWN_STATUS           BIT(2)
  58 #define KSZPHY_INTCS_LINK_UP_STATUS             BIT(0)
  59 #define KSZPHY_INTCS_STATUS                     (KSZPHY_INTCS_LINK_DOWN_STATUS |\
  60                                                  KSZPHY_INTCS_LINK_UP_STATUS)
  61
  62 /* LinkMD Control/Status */
  63 #define KSZ8081_LMD                             0x1d
  64 #define KSZ8081_LMD_ENABLE_TEST                 BIT(15)
  65 #define KSZ8081_LMD_STAT_NORMAL                 0
  66 #define KSZ8081_LMD_STAT_OPEN                   1
  67 #define KSZ8081_LMD_STAT_SHORT                  2
  68 #define KSZ8081_LMD_STAT_FAIL                   3
  69 #define KSZ8081_LMD_STAT_MASK                   GENMASK(14, 13)
  70 /* Short cable (<10 meter) has been detected by LinkMD */
  71 #define KSZ8081_LMD_SHORT_INDICATOR             BIT(12)
  72 #define KSZ8081_LMD_DELTA_TIME_MASK             GENMASK(8, 0)
  73
  74 #define KSZ9x31_LMD                             0x12
  75 #define KSZ9x31_LMD_VCT_EN                      BIT(15)
  76 #define KSZ9x31_LMD_VCT_DIS_TX                  BIT(14)
  77 #define KSZ9x31_LMD_VCT_PAIR(n)                 (((n) & 0x3) << 12)
  78 #define KSZ9x31_LMD_VCT_SEL_RESULT              0
  79 #define KSZ9x31_LMD_VCT_SEL_THRES_HI            BIT(10)
  80 #define KSZ9x31_LMD_VCT_SEL_THRES_LO            BIT(11)
  81 #define KSZ9x31_LMD_VCT_SEL_MASK                GENMASK(11, 10)
  82 #define KSZ9x31_LMD_VCT_ST_NORMAL               0
  83 #define KSZ9x31_LMD_VCT_ST_OPEN                 1
  84 #define KSZ9x31_LMD_VCT_ST_SHORT                2
  85 #define KSZ9x31_LMD_VCT_ST_FAIL                 3
  86 #define KSZ9x31_LMD_VCT_ST_MASK                 GENMASK(9, 8)
  87 #define KSZ9x31_LMD_VCT_DATA_REFLECTED_INVALID  BIT(7)
  88 #define KSZ9x31_LMD_VCT_DATA_SIG_WAIT_TOO_LONG  BIT(6)
  89 #define KSZ9x31_LMD_VCT_DATA_MASK100            BIT(5)
  90 #define KSZ9x31_LMD_VCT_DATA_NLP_FLP            BIT(4)
  91 #define KSZ9x31_LMD_VCT_DATA_LO_PULSE_MASK      GENMASK(3, 2)
  92 #define KSZ9x31_LMD_VCT_DATA_HI_PULSE_MASK      GENMASK(1, 0)
  93 #define KSZ9x31_LMD_VCT_DATA_MASK               GENMASK(7, 0)
  94
  95 /* Lan8814 general Interrupt control/status reg in GPHY specific block. */
  96 #define LAN8814_INTC                            0x18
  97 #define LAN8814_INTS                            0x1B
  98
  99 #define LAN8814_INT_LINK_DOWN                   BIT(2)
 100 #define LAN8814_INT_LINK_UP                     BIT(0)
 101 #define LAN8814_INT_LINK                        (LAN8814_INT_LINK_UP |\
 102                                                  LAN8814_INT_LINK_DOWN)
 103
 104 #define LAN8814_INTR_CTRL_REG                   0x34
 105 #define LAN8814_INTR_CTRL_REG_POLARITY          BIT(1)
 106 #define LAN8814_INTR_CTRL_REG_INTR_ENABLE       BIT(0)
 107
 108 /* Represents 1ppm adjustment in 2^32 format with
 109  * each nsec contains 4 clock cycles.
 110  * The value is calculated as following: (1/1000000)/((2^-32)/4)
 111  */
 112 #define LAN8814_1PPM_FORMAT                     17179
 113
 114 #define PTP_RX_MOD                              0x024F
 115 #define PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
 116 #define PTP_RX_TIMESTAMP_EN                     0x024D
 117 #define PTP_TX_TIMESTAMP_EN                     0x028D
 118
 119 #define PTP_TIMESTAMP_EN_SYNC_                  BIT(0)
 120 #define PTP_TIMESTAMP_EN_DREQ_                  BIT(1)
 121 #define PTP_TIMESTAMP_EN_PDREQ_                 BIT(2)
 122 #define PTP_TIMESTAMP_EN_PDRES_                 BIT(3)
 123
 124 #define PTP_TX_PARSE_L2_ADDR_EN                 0x0284
 125 #define PTP_RX_PARSE_L2_ADDR_EN                 0x0244
 126
 127 #define PTP_TX_PARSE_IP_ADDR_EN                 0x0285
 128 #define PTP_RX_PARSE_IP_ADDR_EN                 0x0245
 129 #define LTC_HARD_RESET                          0x023F
 130 #define LTC_HARD_RESET_                         BIT(0)
 131
 132 #define TSU_HARD_RESET                          0x02C1
 133 #define TSU_HARD_RESET_                         BIT(0)
 134
 135 #define PTP_CMD_CTL                             0x0200
 136 #define PTP_CMD_CTL_PTP_DISABLE_                BIT(0)
 137 #define PTP_CMD_CTL_PTP_ENABLE_                 BIT(1)
 138 #define PTP_CMD_CTL_PTP_CLOCK_READ_             BIT(3)
 139 #define PTP_CMD_CTL_PTP_CLOCK_LOAD_             BIT(4)
 140 #define PTP_CMD_CTL_PTP_LTC_STEP_SEC_           BIT(5)
 141 #define PTP_CMD_CTL_PTP_LTC_STEP_NSEC_          BIT(6)
 142
 143 #define PTP_CLOCK_SET_SEC_MID                   0x0206
 144 #define PTP_CLOCK_SET_SEC_LO                    0x0207
 145 #define PTP_CLOCK_SET_NS_HI                     0x0208
 146 #define PTP_CLOCK_SET_NS_LO                     0x0209
 147
 148 #define PTP_CLOCK_READ_SEC_MID                  0x022A
 149 #define PTP_CLOCK_READ_SEC_LO                   0x022B
 150 #define PTP_CLOCK_READ_NS_HI                    0x022C
 151 #define PTP_CLOCK_READ_NS_LO                    0x022D
 152
 153 #define PTP_OPERATING_MODE                      0x0241
 154 #define PTP_OPERATING_MODE_STANDALONE_          BIT(0)
 155
 156 #define PTP_TX_MOD                              0x028F
 157 #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_       BIT(12)
 158 #define PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
 159
 160 #define PTP_RX_PARSE_CONFIG                     0x0242
 161 #define PTP_RX_PARSE_CONFIG_LAYER2_EN_          BIT(0)
 162 #define PTP_RX_PARSE_CONFIG_IPV4_EN_            BIT(1)
 163 #define PTP_RX_PARSE_CONFIG_IPV6_EN_            BIT(2)
 164
 165 #define PTP_TX_PARSE_CONFIG                     0x0282
 166 #define PTP_TX_PARSE_CONFIG_LAYER2_EN_          BIT(0)
 167 #define PTP_TX_PARSE_CONFIG_IPV4_EN_            BIT(1)
 168 #define PTP_TX_PARSE_CONFIG_IPV6_EN_            BIT(2)
 169
 170 #define PTP_CLOCK_RATE_ADJ_HI                   0x020C
 171 #define PTP_CLOCK_RATE_ADJ_LO                   0x020D
 172 #define PTP_CLOCK_RATE_ADJ_DIR_                 BIT(15)
 173
 174 #define PTP_LTC_STEP_ADJ_HI                     0x0212
 175 #define PTP_LTC_STEP_ADJ_LO                     0x0213
 176 #define PTP_LTC_STEP_ADJ_DIR_                   BIT(15)
 177
 178 #define LAN8814_INTR_STS_REG                    0x0033
 179 #define LAN8814_INTR_STS_REG_1588_TSU0_         BIT(0)
 180 #define LAN8814_INTR_STS_REG_1588_TSU1_         BIT(1)
 181 #define LAN8814_INTR_STS_REG_1588_TSU2_         BIT(2)
 182 #define LAN8814_INTR_STS_REG_1588_TSU3_         BIT(3)
 183
 184 #define PTP_CAP_INFO                            0x022A
 185 #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val)    (((reg_val) & 0x0f00) >> 8)
 186 #define PTP_CAP_INFO_RX_TS_CNT_GET_(reg_val)    ((reg_val) & 0x000f)
 187
 188 #define PTP_TX_EGRESS_SEC_HI                    0x0296
 189 #define PTP_TX_EGRESS_SEC_LO                    0x0297
 190 #define PTP_TX_EGRESS_NS_HI                     0x0294
 191 #define PTP_TX_EGRESS_NS_LO                     0x0295
 192 #define PTP_TX_MSG_HEADER2                      0x0299
 193
 194 #define PTP_RX_INGRESS_SEC_HI                   0x0256
 195 #define PTP_RX_INGRESS_SEC_LO                   0x0257
 196 #define PTP_RX_INGRESS_NS_HI                    0x0254
 197 #define PTP_RX_INGRESS_NS_LO                    0x0255
 198 #define PTP_RX_MSG_HEADER2                      0x0259
 199
 200 #define PTP_TSU_INT_EN                          0x0200
 201 #define PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_      BIT(3)
 202 #define PTP_TSU_INT_EN_PTP_TX_TS_EN_            BIT(2)
 203 #define PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_      BIT(1)
 204 #define PTP_TSU_INT_EN_PTP_RX_TS_EN_            BIT(0)
 205
 206 #define PTP_TSU_INT_STS                         0x0201
 207 #define PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_    BIT(3)
 208 #define PTP_TSU_INT_STS_PTP_TX_TS_EN_           BIT(2)
 209 #define PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_    BIT(1)
 210 #define PTP_TSU_INT_STS_PTP_RX_TS_EN_           BIT(0)
 211
 212 /* PHY Control 1 */
 213 #define MII_KSZPHY_CTRL_1                       0x1e
 214 #define KSZ8081_CTRL1_MDIX_STAT                 BIT(4)
 215
 216 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
 217 #define MII_KSZPHY_CTRL_2                       0x1f
 218 #define MII_KSZPHY_CTRL                         MII_KSZPHY_CTRL_2
 219 /* bitmap of PHY register to set interrupt mode */
 220 #define KSZ8081_CTRL2_HP_MDIX                   BIT(15)
 221 #define KSZ8081_CTRL2_MDI_MDI_X_SELECT          BIT(14)
 222 #define KSZ8081_CTRL2_DISABLE_AUTO_MDIX         BIT(13)
 223 #define KSZ8081_CTRL2_FORCE_LINK                BIT(11)
 224 #define KSZ8081_CTRL2_POWER_SAVING              BIT(10)
 225 #define KSZPHY_CTRL_INT_ACTIVE_HIGH             BIT(9)
 226 #define KSZPHY_RMII_REF_CLK_SEL                 BIT(7)
 227
 228 /* Write/read to/from extended registers */
 229 #define MII_KSZPHY_EXTREG                       0x0b
 230 #define KSZPHY_EXTREG_WRITE                     0x8000
 231
 232 #define MII_KSZPHY_EXTREG_WRITE                 0x0c
 233 #define MII_KSZPHY_EXTREG_READ                  0x0d
 234
 235 /* Extended registers */
 236 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW         0x104
 237 #define MII_KSZPHY_RX_DATA_PAD_SKEW             0x105
 238 #define MII_KSZPHY_TX_DATA_PAD_SKEW             0x106
 239
 240 #define PS_TO_REG                               200
 241 #define FIFO_SIZE                               8
 242
 243 struct kszphy_hw_stat {
 244         const char *string;
 245         u8 reg;
 246         u8 bits;
 247 };
 248
 249 static struct kszphy_hw_stat kszphy_hw_stats[] = {
 250         { "phy_receive_errors", 21, 16},
 251         { "phy_idle_errors", 10, 8 },
 252 };
 253
 254 struct kszphy_type {
 255         u32 led_mode_reg;
 256         u16 interrupt_level_mask;
 257         bool has_broadcast_disable;
 258         bool has_nand_tree_disable;
 259         bool has_rmii_ref_clk_sel;
 260 };
 261
 262 /* Shared structure between the PHYs of the same package. */
 263 struct lan8814_shared_priv {
 264         struct phy_device *phydev;
 265         struct ptp_clock *ptp_clock;
 266         struct ptp_clock_info ptp_clock_info;
 267
 268         /* Reference counter to how many ports in the package are enabling the
 269          * timestamping
 270          */
 271         u8 ref;
 272
 273         /* Lock for ptp_clock and ref */
 274         struct mutex shared_lock;
 275 };
 276
 277 struct lan8814_ptp_rx_ts {
 278         struct list_head list;
 279         u32 seconds;
 280         u32 nsec;
 281         u16 seq_id;
 282 };
 283
 284 struct kszphy_ptp_priv {
 285         struct mii_timestamper mii_ts;
 286         struct phy_device *phydev;
 287
 288         struct sk_buff_head tx_queue;
 289         struct sk_buff_head rx_queue;
 290
 291         struct list_head rx_ts_list;
 292         /* Lock for Rx ts fifo */
 293         spinlock_t rx_ts_lock;
 294
 295         int hwts_tx_type;
 296         enum hwtstamp_rx_filters rx_filter;
 297         int layer;
 298         int version;
 299 };
 300
 301 struct kszphy_priv {
 302         struct kszphy_ptp_priv ptp_priv;
 303         const struct kszphy_type *type;
 304         int led_mode;
 305         u16 vct_ctrl1000;
 306         bool rmii_ref_clk_sel;
 307         bool rmii_ref_clk_sel_val;
 308         u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
 309 };
 310
 311 static const struct kszphy_type ksz8021_type = {
 312         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 313         .has_broadcast_disable  = true,
 314         .has_nand_tree_disable  = true,
 315         .has_rmii_ref_clk_sel   = true,
 316 };
 317
 318 static const struct kszphy_type ksz8041_type = {
 319         .led_mode_reg           = MII_KSZPHY_CTRL_1,
 320 };
 321
 322 static const struct kszphy_type ksz8051_type = {
 323         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 324         .has_nand_tree_disable  = true,
 325 };
 326
 327 static const struct kszphy_type ksz8081_type = {
 328         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 329         .has_broadcast_disable  = true,
 330         .has_nand_tree_disable  = true,
 331         .has_rmii_ref_clk_sel   = true,
 332 };
 333
 334 static const struct kszphy_type ks8737_type = {
 335         .interrupt_level_mask   = BIT(14),
 336 };
 337
 338 static const struct kszphy_type ksz9021_type = {
 339         .interrupt_level_mask   = BIT(14),
 340 };
 341
 342 static int kszphy_extended_write(struct phy_device *phydev,
 343                                 u32 regnum, u16 val)
 344 {
 345         phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
 346         return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
 347 }
 348
 349 static int kszphy_extended_read(struct phy_device *phydev,
 350                                 u32 regnum)
 351 {
 352         phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
 353         return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
 354 }
 355
 356 static int kszphy_ack_interrupt(struct phy_device *phydev)
 357 {
 358         /* bit[7..0] int status, which is a read and clear register. */
 359         int rc;
 360
 361         rc = phy_read(phydev, MII_KSZPHY_INTCS);
 362
 363         return (rc < 0) ? rc : 0;
 364 }
 365
 366 static int kszphy_config_intr(struct phy_device *phydev)
 367 {
 368         const struct kszphy_type *type = phydev->drv->driver_data;
 369         int temp, err;
 370         u16 mask;
 371
 372         if (type && type->interrupt_level_mask)
 373                 mask = type->interrupt_level_mask;
 374         else
 375                 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
 376
 377         /* set the interrupt pin active low */
 378         temp = phy_read(phydev, MII_KSZPHY_CTRL);
 379         if (temp < 0)
 380                 return temp;
 381         temp &= ~mask;
 382         phy_write(phydev, MII_KSZPHY_CTRL, temp);
 383
 384         /* enable / disable interrupts */
 385         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 386                 err = kszphy_ack_interrupt(phydev);
 387                 if (err)
 388                         return err;
 389
 390                 temp = KSZPHY_INTCS_ALL;
 391                 err = phy_write(phydev, MII_KSZPHY_INTCS, temp);
 392         } else {
 393                 temp = 0;
 394                 err = phy_write(phydev, MII_KSZPHY_INTCS, temp);
 395                 if (err)
 396                         return err;
 397
 398                 err = kszphy_ack_interrupt(phydev);
 399         }
 400
 401         return err;
 402 }
 403
 404 static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev)
 405 {
 406         int irq_status;
 407
 408         irq_status = phy_read(phydev, MII_KSZPHY_INTCS);
 409         if (irq_status < 0) {
 410                 phy_error(phydev);
 411                 return IRQ_NONE;
 412         }
 413
 414         if (!(irq_status & KSZPHY_INTCS_STATUS))
 415                 return IRQ_NONE;
 416
 417         phy_trigger_machine(phydev);
 418
 419         return IRQ_HANDLED;
 420 }
 421
 422 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
 423 {
 424         int ctrl;
 425
 426         ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
 427         if (ctrl < 0)
 428                 return ctrl;
 429
 430         if (val)
 431                 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
 432         else
 433                 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
 434
 435         return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
 436 }
 437
 438 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
 439 {
 440         int rc, temp, shift;
 441
 442         switch (reg) {
 443         case MII_KSZPHY_CTRL_1:
 444                 shift = 14;
 445                 break;
 446         case MII_KSZPHY_CTRL_2:
 447                 shift = 4;
 448                 break;
 449         default:
 450                 return -EINVAL;
 451         }
 452
 453         temp = phy_read(phydev, reg);
 454         if (temp < 0) {
 455                 rc = temp;
 456                 goto out;
 457         }
 458
 459         temp &= ~(3 << shift);
 460         temp |= val << shift;
 461         rc = phy_write(phydev, reg, temp);
 462 out:
 463         if (rc < 0)
 464                 phydev_err(phydev, "failed to set led mode\n");
 465
 466         return rc;
 467 }
 468
 469 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
 470  * unique (non-broadcast) address on a shared bus.
 471  */
 472 static int kszphy_broadcast_disable(struct phy_device *phydev)
 473 {
 474         int ret;
 475
 476         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 477         if (ret < 0)
 478                 goto out;
 479
 480         ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
 481 out:
 482         if (ret)
 483                 phydev_err(phydev, "failed to disable broadcast address\n");
 484
 485         return ret;
 486 }
 487
 488 static int kszphy_nand_tree_disable(struct phy_device *phydev)
 489 {
 490         int ret;
 491
 492         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 493         if (ret < 0)
 494                 goto out;
 495
 496         if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
 497                 return 0;
 498
 499         ret = phy_write(phydev, MII_KSZPHY_OMSO,
 500                         ret & ~KSZPHY_OMSO_NAND_TREE_ON);
 501 out:
 502         if (ret)
 503                 phydev_err(phydev, "failed to disable NAND tree mode\n");
 504
 505         return ret;
 506 }
 507
 508 /* Some config bits need to be set again on resume, handle them here. */
 509 static int kszphy_config_reset(struct phy_device *phydev)
 510 {
 511         struct kszphy_priv *priv = phydev->priv;
 512         int ret;
 513
 514         if (priv->rmii_ref_clk_sel) {
 515                 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
 516                 if (ret) {
 517                         phydev_err(phydev,
 518                                    "failed to set rmii reference clock\n");
 519                         return ret;
 520                 }
 521         }
 522
 523         if (priv->type && priv->led_mode >= 0)
 524                 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
 525
 526         return 0;
 527 }
 528
 529 static int kszphy_config_init(struct phy_device *phydev)
 530 {
 531         struct kszphy_priv *priv = phydev->priv;
 532         const struct kszphy_type *type;
 533
 534         if (!priv)
 535                 return 0;
 536
 537         type = priv->type;
 538
 539         if (type && type->has_broadcast_disable)
 540                 kszphy_broadcast_disable(phydev);
 541
 542         if (type && type->has_nand_tree_disable)
 543                 kszphy_nand_tree_disable(phydev);
 544
 545         return kszphy_config_reset(phydev);
 546 }
 547
 548 static int ksz8041_fiber_mode(struct phy_device *phydev)
 549 {
 550         struct device_node *of_node = phydev->mdio.dev.of_node;
 551
 552         return of_property_read_bool(of_node, "micrel,fiber-mode");
 553 }
 554
 555 static int ksz8041_config_init(struct phy_device *phydev)
 556 {
 557         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 558
 559         /* Limit supported and advertised modes in fiber mode */
 560         if (ksz8041_fiber_mode(phydev)) {
 561                 phydev->dev_flags |= MICREL_PHY_FXEN;
 562                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
 563                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
 564
 565                 linkmode_and(phydev->supported, phydev->supported, mask);
 566                 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
 567                                  phydev->supported);
 568                 linkmode_and(phydev->advertising, phydev->advertising, mask);
 569                 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
 570                                  phydev->advertising);
 571                 phydev->autoneg = AUTONEG_DISABLE;
 572         }
 573
 574         return kszphy_config_init(phydev);
 575 }
 576
 577 static int ksz8041_config_aneg(struct phy_device *phydev)
 578 {
 579         /* Skip auto-negotiation in fiber mode */
 580         if (phydev->dev_flags & MICREL_PHY_FXEN) {
 581                 phydev->speed = SPEED_100;
 582                 return 0;
 583         }
 584
 585         return genphy_config_aneg(phydev);
 586 }
 587
 588 static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
 589                                             const bool ksz_8051)
 590 {
 591         int ret;
 592
 593         if ((phydev->phy_id & MICREL_PHY_ID_MASK) != PHY_ID_KSZ8051)
 594                 return 0;
 595
 596         ret = phy_read(phydev, MII_BMSR);
 597         if (ret < 0)
 598                 return ret;
 599
 600         /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
 601          * exact PHY ID. However, they can be told apart by the extended
 602          * capability registers presence. The KSZ8051 PHY has them while
 603          * the switch does not.
 604          */
 605         ret &= BMSR_ERCAP;
 606         if (ksz_8051)
 607                 return ret;
 608         else
 609                 return !ret;
 610 }
 611
 612 static int ksz8051_match_phy_device(struct phy_device *phydev)
 613 {
 614         return ksz8051_ksz8795_match_phy_device(phydev, true);
 615 }
 616
 617 static int ksz8081_config_init(struct phy_device *phydev)
 618 {
 619         /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
 620          * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
 621          * pull-down is missing, the factory test mode should be cleared by
 622          * manually writing a 0.
 623          */
 624         phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
 625
 626         return kszphy_config_init(phydev);
 627 }
 628
 629 static int ksz8081_config_mdix(struct phy_device *phydev, u8 ctrl)
 630 {
 631         u16 val;
 632
 633         switch (ctrl) {
 634         case ETH_TP_MDI:
 635                 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX;
 636                 break;
 637         case ETH_TP_MDI_X:
 638                 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX |
 639                         KSZ8081_CTRL2_MDI_MDI_X_SELECT;
 640                 break;
 641         case ETH_TP_MDI_AUTO:
 642                 val = 0;
 643                 break;
 644         default:
 645                 return 0;
 646         }
 647
 648         return phy_modify(phydev, MII_KSZPHY_CTRL_2,
 649                           KSZ8081_CTRL2_HP_MDIX |
 650                           KSZ8081_CTRL2_MDI_MDI_X_SELECT |
 651                           KSZ8081_CTRL2_DISABLE_AUTO_MDIX,
 652                           KSZ8081_CTRL2_HP_MDIX | val);
 653 }
 654
 655 static int ksz8081_config_aneg(struct phy_device *phydev)
 656 {
 657         int ret;
 658
 659         ret = genphy_config_aneg(phydev);
 660         if (ret)
 661                 return ret;
 662
 663         /* The MDI-X configuration is automatically changed by the PHY after
 664          * switching from autoneg off to on. So, take MDI-X configuration under
 665          * own control and set it after autoneg configuration was done.
 666          */
 667         return ksz8081_config_mdix(phydev, phydev->mdix_ctrl);
 668 }
 669
 670 static int ksz8081_mdix_update(struct phy_device *phydev)
 671 {
 672         int ret;
 673
 674         ret = phy_read(phydev, MII_KSZPHY_CTRL_2);
 675         if (ret < 0)
 676                 return ret;
 677
 678         if (ret & KSZ8081_CTRL2_DISABLE_AUTO_MDIX) {
 679                 if (ret & KSZ8081_CTRL2_MDI_MDI_X_SELECT)
 680                         phydev->mdix_ctrl = ETH_TP_MDI_X;
 681                 else
 682                         phydev->mdix_ctrl = ETH_TP_MDI;
 683         } else {
 684                 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
 685         }
 686
 687         ret = phy_read(phydev, MII_KSZPHY_CTRL_1);
 688         if (ret < 0)
 689                 return ret;
 690
 691         if (ret & KSZ8081_CTRL1_MDIX_STAT)
 692                 phydev->mdix = ETH_TP_MDI;
 693         else
 694                 phydev->mdix = ETH_TP_MDI_X;
 695
 696         return 0;
 697 }
 698
 699 static int ksz8081_read_status(struct phy_device *phydev)
 700 {
 701         int ret;
 702
 703         ret = ksz8081_mdix_update(phydev);
 704         if (ret < 0)
 705                 return ret;
 706
 707         return genphy_read_status(phydev);
 708 }
 709
 710 static int ksz8061_config_init(struct phy_device *phydev)
 711 {
 712         int ret;
 713
 714         ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
 715         if (ret)
 716                 return ret;
 717
 718         return kszphy_config_init(phydev);
 719 }
 720
 721 static int ksz8795_match_phy_device(struct phy_device *phydev)
 722 {
 723         return ksz8051_ksz8795_match_phy_device(phydev, false);
 724 }
 725
 726 static int ksz9021_load_values_from_of(struct phy_device *phydev,
 727                                        const struct device_node *of_node,
 728                                        u16 reg,
 729                                        const char *field1, const char *field2,
 730                                        const char *field3, const char *field4)
 731 {
 732         int val1 = -1;
 733         int val2 = -2;
 734         int val3 = -3;
 735         int val4 = -4;
 736         int newval;
 737         int matches = 0;
 738
 739         if (!of_property_read_u32(of_node, field1, &val1))
 740                 matches++;
 741
 742         if (!of_property_read_u32(of_node, field2, &val2))
 743                 matches++;
 744
 745         if (!of_property_read_u32(of_node, field3, &val3))
 746                 matches++;
 747
 748         if (!of_property_read_u32(of_node, field4, &val4))
 749                 matches++;
 750
 751         if (!matches)
 752                 return 0;
 753
 754         if (matches < 4)
 755                 newval = kszphy_extended_read(phydev, reg);
 756         else
 757                 newval = 0;
 758
 759         if (val1 != -1)
 760                 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
 761
 762         if (val2 != -2)
 763                 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
 764
 765         if (val3 != -3)
 766                 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
 767
 768         if (val4 != -4)
 769                 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
 770
 771         return kszphy_extended_write(phydev, reg, newval);
 772 }
 773
 774 static int ksz9021_config_init(struct phy_device *phydev)
 775 {
 776         const struct device_node *of_node;
 777         const struct device *dev_walker;
 778
 779         /* The Micrel driver has a deprecated option to place phy OF
 780          * properties in the MAC node. Walk up the tree of devices to
 781          * find a device with an OF node.
 782          */
 783         dev_walker = &phydev->mdio.dev;
 784         do {
 785                 of_node = dev_walker->of_node;
 786                 dev_walker = dev_walker->parent;
 787
 788         } while (!of_node && dev_walker);
 789
 790         if (of_node) {
 791                 ksz9021_load_values_from_of(phydev, of_node,
 792                                     MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
 793                                     "txen-skew-ps", "txc-skew-ps",
 794                                     "rxdv-skew-ps", "rxc-skew-ps");
 795                 ksz9021_load_values_from_of(phydev, of_node,
 796                                     MII_KSZPHY_RX_DATA_PAD_SKEW,
 797                                     "rxd0-skew-ps", "rxd1-skew-ps",
 798                                     "rxd2-skew-ps", "rxd3-skew-ps");
 799                 ksz9021_load_values_from_of(phydev, of_node,
 800                                     MII_KSZPHY_TX_DATA_PAD_SKEW,
 801                                     "txd0-skew-ps", "txd1-skew-ps",
 802                                     "txd2-skew-ps", "txd3-skew-ps");
 803         }
 804         return 0;
 805 }
 806
 807 #define KSZ9031_PS_TO_REG               60
 808
 809 /* Extended registers */
 810 /* MMD Address 0x0 */
 811 #define MII_KSZ9031RN_FLP_BURST_TX_LO   3
 812 #define MII_KSZ9031RN_FLP_BURST_TX_HI   4
 813
 814 /* MMD Address 0x2 */
 815 #define MII_KSZ9031RN_CONTROL_PAD_SKEW  4
 816 #define MII_KSZ9031RN_RX_CTL_M          GENMASK(7, 4)
 817 #define MII_KSZ9031RN_TX_CTL_M          GENMASK(3, 0)
 818
 819 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW  5
 820 #define MII_KSZ9031RN_RXD3              GENMASK(15, 12)
 821 #define MII_KSZ9031RN_RXD2              GENMASK(11, 8)
 822 #define MII_KSZ9031RN_RXD1              GENMASK(7, 4)
 823 #define MII_KSZ9031RN_RXD0              GENMASK(3, 0)
 824
 825 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW  6
 826 #define MII_KSZ9031RN_TXD3              GENMASK(15, 12)
 827 #define MII_KSZ9031RN_TXD2              GENMASK(11, 8)
 828 #define MII_KSZ9031RN_TXD1              GENMASK(7, 4)
 829 #define MII_KSZ9031RN_TXD0              GENMASK(3, 0)
 830
 831 #define MII_KSZ9031RN_CLK_PAD_SKEW      8
 832 #define MII_KSZ9031RN_GTX_CLK           GENMASK(9, 5)
 833 #define MII_KSZ9031RN_RX_CLK            GENMASK(4, 0)
 834
 835 /* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To
 836  * provide different RGMII options we need to configure delay offset
 837  * for each pad relative to build in delay.
 838  */
 839 /* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of
 840  * 1.80ns
 841  */
 842 #define RX_ID                           0x7
 843 #define RX_CLK_ID                       0x19
 844
 845 /* set rx to +0.30ns and rx_clk to -0.90ns to compensate the
 846  * internal 1.2ns delay.
 847  */
 848 #define RX_ND                           0xc
 849 #define RX_CLK_ND                       0x0
 850
 851 /* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
 852 #define TX_ID                           0x0
 853 #define TX_CLK_ID                       0x1f
 854
 855 /* set tx and tx_clk to "No delay adjustment" to keep 0ns
 856  * dealy
 857  */
 858 #define TX_ND                           0x7
 859 #define TX_CLK_ND                       0xf
 860
 861 /* MMD Address 0x1C */
 862 #define MII_KSZ9031RN_EDPD              0x23
 863 #define MII_KSZ9031RN_EDPD_ENABLE       BIT(0)
 864
 865 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
 866                                        const struct device_node *of_node,
 867                                        u16 reg, size_t field_sz,
 868                                        const char *field[], u8 numfields,
 869                                        bool *update)
 870 {
 871         int val[4] = {-1, -2, -3, -4};
 872         int matches = 0;
 873         u16 mask;
 874         u16 maxval;
 875         u16 newval;
 876         int i;
 877
 878         for (i = 0; i < numfields; i++)
 879                 if (!of_property_read_u32(of_node, field[i], val + i))
 880                         matches++;
 881
 882         if (!matches)
 883                 return 0;
 884
 885         *update |= true;
 886
 887         if (matches < numfields)
 888                 newval = phy_read_mmd(phydev, 2, reg);
 889         else
 890                 newval = 0;
 891
 892         maxval = (field_sz == 4) ? 0xf : 0x1f;
 893         for (i = 0; i < numfields; i++)
 894                 if (val[i] != -(i + 1)) {
 895                         mask = 0xffff;
 896                         mask ^= maxval << (field_sz * i);
 897                         newval = (newval & mask) |
 898                                 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
 899                                         << (field_sz * i));
 900                 }
 901
 902         return phy_write_mmd(phydev, 2, reg, newval);
 903 }
 904
 905 /* Center KSZ9031RNX FLP timing at 16ms. */
 906 static int ksz9031_center_flp_timing(struct phy_device *phydev)
 907 {
 908         int result;
 909
 910         result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
 911                                0x0006);
 912         if (result)
 913                 return result;
 914
 915         result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
 916                                0x1A80);
 917         if (result)
 918                 return result;
 919
 920         return genphy_restart_aneg(phydev);
 921 }
 922
 923 /* Enable energy-detect power-down mode */
 924 static int ksz9031_enable_edpd(struct phy_device *phydev)
 925 {
 926         int reg;
 927
 928         reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
 929         if (reg < 0)
 930                 return reg;
 931         return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
 932                              reg | MII_KSZ9031RN_EDPD_ENABLE);
 933 }
 934
 935 static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
 936 {
 937         u16 rx, tx, rx_clk, tx_clk;
 938         int ret;
 939
 940         switch (phydev->interface) {
 941         case PHY_INTERFACE_MODE_RGMII:
 942                 tx = TX_ND;
 943                 tx_clk = TX_CLK_ND;
 944                 rx = RX_ND;
 945                 rx_clk = RX_CLK_ND;
 946                 break;
 947         case PHY_INTERFACE_MODE_RGMII_ID:
 948                 tx = TX_ID;
 949                 tx_clk = TX_CLK_ID;
 950                 rx = RX_ID;
 951                 rx_clk = RX_CLK_ID;
 952                 break;
 953         case PHY_INTERFACE_MODE_RGMII_RXID:
 954                 tx = TX_ND;
 955                 tx_clk = TX_CLK_ND;
 956                 rx = RX_ID;
 957                 rx_clk = RX_CLK_ID;
 958                 break;
 959         case PHY_INTERFACE_MODE_RGMII_TXID:
 960                 tx = TX_ID;
 961                 tx_clk = TX_CLK_ID;
 962                 rx = RX_ND;
 963                 rx_clk = RX_CLK_ND;
 964                 break;
 965         default:
 966                 return 0;
 967         }
 968
 969         ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,
 970                             FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) |
 971                             FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));
 972         if (ret < 0)
 973                 return ret;
 974
 975         ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,
 976                             FIELD_PREP(MII_KSZ9031RN_RXD3, rx) |
 977                             FIELD_PREP(MII_KSZ9031RN_RXD2, rx) |
 978                             FIELD_PREP(MII_KSZ9031RN_RXD1, rx) |
 979                             FIELD_PREP(MII_KSZ9031RN_RXD0, rx));
 980         if (ret < 0)
 981                 return ret;
 982
 983         ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,
 984                             FIELD_PREP(MII_KSZ9031RN_TXD3, tx) |
 985                             FIELD_PREP(MII_KSZ9031RN_TXD2, tx) |
 986                             FIELD_PREP(MII_KSZ9031RN_TXD1, tx) |
 987                             FIELD_PREP(MII_KSZ9031RN_TXD0, tx));
 988         if (ret < 0)
 989                 return ret;
 990
 991         return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW,
 992                              FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) |
 993                              FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));
 994 }
 995
 996 static int ksz9031_config_init(struct phy_device *phydev)
 997 {
 998         const struct device_node *of_node;
 999         static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
1000         static const char *rx_data_skews[4] = {
1001                 "rxd0-skew-ps", "rxd1-skew-ps",
1002                 "rxd2-skew-ps", "rxd3-skew-ps"
1003         };
1004         static const char *tx_data_skews[4] = {
1005                 "txd0-skew-ps", "txd1-skew-ps",
1006                 "txd2-skew-ps", "txd3-skew-ps"
1007         };
1008         static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
1009         const struct device *dev_walker;
1010         int result;
1011
1012         result = ksz9031_enable_edpd(phydev);
1013         if (result < 0)
1014                 return result;
1015
1016         /* The Micrel driver has a deprecated option to place phy OF
1017          * properties in the MAC node. Walk up the tree of devices to
1018          * find a device with an OF node.
1019          */
1020         dev_walker = &phydev->mdio.dev;
1021         do {
1022                 of_node = dev_walker->of_node;
1023                 dev_walker = dev_walker->parent;
1024         } while (!of_node && dev_walker);
1025
1026         if (of_node) {
1027                 bool update = false;
1028
1029                 if (phy_interface_is_rgmii(phydev)) {
1030                         result = ksz9031_config_rgmii_delay(phydev);
1031                         if (result < 0)
1032                                 return result;
1033                 }
1034
1035                 ksz9031_of_load_skew_values(phydev, of_node,
1036                                 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1037                                 clk_skews, 2, &update);
1038
1039                 ksz9031_of_load_skew_values(phydev, of_node,
1040                                 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1041                                 control_skews, 2, &update);
1042
1043                 ksz9031_of_load_skew_values(phydev, of_node,
1044                                 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1045                                 rx_data_skews, 4, &update);
1046
1047                 ksz9031_of_load_skew_values(phydev, of_node,
1048                                 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1049                                 tx_data_skews, 4, &update);
1050
1051                 if (update && !phy_interface_is_rgmii(phydev))
1052                         phydev_warn(phydev,
1053                                     "*-skew-ps values should be used only with RGMII PHY modes\n");
1054
1055                 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1056                  * When the device links in the 1000BASE-T slave mode only,
1057                  * the optional 125MHz reference output clock (CLK125_NDO)
1058                  * has wide duty cycle variation.
1059                  *
1060                  * The optional CLK125_NDO clock does not meet the RGMII
1061                  * 45/55 percent (min/max) duty cycle requirement and therefore
1062                  * cannot be used directly by the MAC side for clocking
1063                  * applications that have setup/hold time requirements on
1064                  * rising and falling clock edges.
1065                  *
1066                  * Workaround:
1067                  * Force the phy to be the master to receive a stable clock
1068                  * which meets the duty cycle requirement.
1069                  */
1070                 if (of_property_read_bool(of_node, "micrel,force-master")) {
1071                         result = phy_read(phydev, MII_CTRL1000);
1072                         if (result < 0)
1073                                 goto err_force_master;
1074
1075                         /* enable master mode, config & prefer master */
1076                         result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
1077                         result = phy_write(phydev, MII_CTRL1000, result);
1078                         if (result < 0)
1079                                 goto err_force_master;
1080                 }
1081         }
1082
1083         return ksz9031_center_flp_timing(phydev);
1084
1085 err_force_master:
1086         phydev_err(phydev, "failed to force the phy to master mode\n");
1087         return result;
1088 }
1089
1090 #define KSZ9131_SKEW_5BIT_MAX   2400
1091 #define KSZ9131_SKEW_4BIT_MAX   800
1092 #define KSZ9131_OFFSET          700
1093 #define KSZ9131_STEP            100
1094
1095 static int ksz9131_of_load_skew_values(struct phy_device *phydev,
1096                                        struct device_node *of_node,
1097                                        u16 reg, size_t field_sz,
1098                                        char *field[], u8 numfields)
1099 {
1100         int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
1101                       -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
1102         int skewval, skewmax = 0;
1103         int matches = 0;
1104         u16 maxval;
1105         u16 newval;
1106         u16 mask;
1107         int i;
1108
1109         /* psec properties in dts should mean x pico seconds */
1110         if (field_sz == 5)
1111                 skewmax = KSZ9131_SKEW_5BIT_MAX;
1112         else
1113                 skewmax = KSZ9131_SKEW_4BIT_MAX;
1114
1115         for (i = 0; i < numfields; i++)
1116                 if (!of_property_read_s32(of_node, field[i], &skewval)) {
1117                         if (skewval < -KSZ9131_OFFSET)
1118                                 skewval = -KSZ9131_OFFSET;
1119                         else if (skewval > skewmax)
1120                                 skewval = skewmax;
1121
1122                         val[i] = skewval + KSZ9131_OFFSET;
1123                         matches++;
1124                 }
1125
1126         if (!matches)
1127                 return 0;
1128
1129         if (matches < numfields)
1130                 newval = phy_read_mmd(phydev, 2, reg);
1131         else
1132                 newval = 0;
1133
1134         maxval = (field_sz == 4) ? 0xf : 0x1f;
1135         for (i = 0; i < numfields; i++)
1136                 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
1137                         mask = 0xffff;
1138                         mask ^= maxval << (field_sz * i);
1139                         newval = (newval & mask) |
1140                                 (((val[i] / KSZ9131_STEP) & maxval)
1141                                         << (field_sz * i));
1142                 }
1143
1144         return phy_write_mmd(phydev, 2, reg, newval);
1145 }
1146
1147 #define KSZ9131RN_MMD_COMMON_CTRL_REG   2
1148 #define KSZ9131RN_RXC_DLL_CTRL          76
1149 #define KSZ9131RN_TXC_DLL_CTRL          77
1150 #define KSZ9131RN_DLL_CTRL_BYPASS       BIT_MASK(12)
1151 #define KSZ9131RN_DLL_ENABLE_DELAY      0
1152 #define KSZ9131RN_DLL_DISABLE_DELAY     BIT(12)
1153
1154 static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
1155 {
1156         u16 rxcdll_val, txcdll_val;
1157         int ret;
1158
1159         switch (phydev->interface) {
1160         case PHY_INTERFACE_MODE_RGMII:
1161                 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1162                 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1163                 break;
1164         case PHY_INTERFACE_MODE_RGMII_ID:
1165                 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1166                 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1167                 break;
1168         case PHY_INTERFACE_MODE_RGMII_RXID:
1169                 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1170                 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1171                 break;
1172         case PHY_INTERFACE_MODE_RGMII_TXID:
1173                 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1174                 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1175                 break;
1176         default:
1177                 return 0;
1178         }
1179
1180         ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1181                              KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
1182                              rxcdll_val);
1183         if (ret < 0)
1184                 return ret;
1185
1186         return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1187                               KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
1188                               txcdll_val);
1189 }
1190
1191 /* Silicon Errata DS80000693B
1192  *
1193  * When LEDs are configured in Individual Mode, LED1 is ON in a no-link
1194  * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
1195  * according to the datasheet (off if there is no link).
1196  */
1197 static int ksz9131_led_errata(struct phy_device *phydev)
1198 {
1199         int reg;
1200
1201         reg = phy_read_mmd(phydev, 2, 0);
1202         if (reg < 0)
1203                 return reg;
1204
1205         if (!(reg & BIT(4)))
1206                 return 0;
1207
1208         return phy_set_bits(phydev, 0x1e, BIT(9));
1209 }
1210
1211 static int ksz9131_config_init(struct phy_device *phydev)
1212 {
1213         struct device_node *of_node;
1214         char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
1215         char *rx_data_skews[4] = {
1216                 "rxd0-skew-psec", "rxd1-skew-psec",
1217                 "rxd2-skew-psec", "rxd3-skew-psec"
1218         };
1219         char *tx_data_skews[4] = {
1220                 "txd0-skew-psec", "txd1-skew-psec",
1221                 "txd2-skew-psec", "txd3-skew-psec"
1222         };
1223         char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
1224         const struct device *dev_walker;
1225         int ret;
1226
1227         dev_walker = &phydev->mdio.dev;
1228         do {
1229                 of_node = dev_walker->of_node;
1230                 dev_walker = dev_walker->parent;
1231         } while (!of_node && dev_walker);
1232
1233         if (!of_node)
1234                 return 0;
1235
1236         if (phy_interface_is_rgmii(phydev)) {
1237                 ret = ksz9131_config_rgmii_delay(phydev);
1238                 if (ret < 0)
1239                         return ret;
1240         }
1241
1242         ret = ksz9131_of_load_skew_values(phydev, of_node,
1243                                           MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1244                                           clk_skews, 2);
1245         if (ret < 0)
1246                 return ret;
1247
1248         ret = ksz9131_of_load_skew_values(phydev, of_node,
1249                                           MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1250                                           control_skews, 2);
1251         if (ret < 0)
1252                 return ret;
1253
1254         ret = ksz9131_of_load_skew_values(phydev, of_node,
1255                                           MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1256                                           rx_data_skews, 4);
1257         if (ret < 0)
1258                 return ret;
1259
1260         ret = ksz9131_of_load_skew_values(phydev, of_node,
1261                                           MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1262                                           tx_data_skews, 4);
1263         if (ret < 0)
1264                 return ret;
1265
1266         ret = ksz9131_led_errata(phydev);
1267         if (ret < 0)
1268                 return ret;
1269
1270         return 0;
1271 }
1272
1273 #define KSZ8873MLL_GLOBAL_CONTROL_4     0x06
1274 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX      BIT(6)
1275 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED       BIT(4)
1276 static int ksz8873mll_read_status(struct phy_device *phydev)
1277 {
1278         int regval;
1279
1280         /* dummy read */
1281         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1282
1283         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1284
1285         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
1286                 phydev->duplex = DUPLEX_HALF;
1287         else
1288                 phydev->duplex = DUPLEX_FULL;
1289
1290         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
1291                 phydev->speed = SPEED_10;
1292         else
1293                 phydev->speed = SPEED_100;
1294
1295         phydev->link = 1;
1296         phydev->pause = phydev->asym_pause = 0;
1297
1298         return 0;
1299 }
1300
1301 static int ksz9031_get_features(struct phy_device *phydev)
1302 {
1303         int ret;
1304
1305         ret = genphy_read_abilities(phydev);
1306         if (ret < 0)
1307                 return ret;
1308
1309         /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1310          * Whenever the device's Asymmetric Pause capability is set to 1,
1311          * link-up may fail after a link-up to link-down transition.
1312          *
1313          * The Errata Sheet is for ksz9031, but ksz9021 has the same issue
1314          *
1315          * Workaround:
1316          * Do not enable the Asymmetric Pause capability bit.
1317          */
1318         linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
1319
1320         /* We force setting the Pause capability as the core will force the
1321          * Asymmetric Pause capability to 1 otherwise.
1322          */
1323         linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
1324
1325         return 0;
1326 }
1327
1328 static int ksz9031_read_status(struct phy_device *phydev)
1329 {
1330         int err;
1331         int regval;
1332
1333         err = genphy_read_status(phydev);
1334         if (err)
1335                 return err;
1336
1337         /* Make sure the PHY is not broken. Read idle error count,
1338          * and reset the PHY if it is maxed out.
1339          */
1340         regval = phy_read(phydev, MII_STAT1000);
1341         if ((regval & 0xFF) == 0xFF) {
1342                 phy_init_hw(phydev);
1343                 phydev->link = 0;
1344                 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
1345                         phydev->drv->config_intr(phydev);
1346                 return genphy_config_aneg(phydev);
1347         }
1348
1349         return 0;
1350 }
1351
1352 static int ksz9x31_cable_test_start(struct phy_device *phydev)
1353 {
1354         struct kszphy_priv *priv = phydev->priv;
1355         int ret;
1356
1357         /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1358          * Prior to running the cable diagnostics, Auto-negotiation should
1359          * be disabled, full duplex set and the link speed set to 1000Mbps
1360          * via the Basic Control Register.
1361          */
1362         ret = phy_modify(phydev, MII_BMCR,
1363                          BMCR_SPEED1000 | BMCR_FULLDPLX |
1364                          BMCR_ANENABLE | BMCR_SPEED100,
1365                          BMCR_SPEED1000 | BMCR_FULLDPLX);
1366         if (ret)
1367                 return ret;
1368
1369         /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1370          * The Master-Slave configuration should be set to Slave by writing
1371          * a value of 0x1000 to the Auto-Negotiation Master Slave Control
1372          * Register.
1373          */
1374         ret = phy_read(phydev, MII_CTRL1000);
1375         if (ret < 0)
1376                 return ret;
1377
1378         /* Cache these bits, they need to be restored once LinkMD finishes. */
1379         priv->vct_ctrl1000 = ret & (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1380         ret &= ~(CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1381         ret |= CTL1000_ENABLE_MASTER;
1382
1383         return phy_write(phydev, MII_CTRL1000, ret);
1384 }
1385
1386 static int ksz9x31_cable_test_result_trans(u16 status)
1387 {
1388         switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1389         case KSZ9x31_LMD_VCT_ST_NORMAL:
1390                 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1391         case KSZ9x31_LMD_VCT_ST_OPEN:
1392                 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1393         case KSZ9x31_LMD_VCT_ST_SHORT:
1394                 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1395         case KSZ9x31_LMD_VCT_ST_FAIL:
1396                 fallthrough;
1397         default:
1398                 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1399         }
1400 }
1401
1402 static bool ksz9x31_cable_test_failed(u16 status)
1403 {
1404         int stat = FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status);
1405
1406         return stat == KSZ9x31_LMD_VCT_ST_FAIL;
1407 }
1408
1409 static bool ksz9x31_cable_test_fault_length_valid(u16 status)
1410 {
1411         switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1412         case KSZ9x31_LMD_VCT_ST_OPEN:
1413                 fallthrough;
1414         case KSZ9x31_LMD_VCT_ST_SHORT:
1415                 return true;
1416         }
1417         return false;
1418 }
1419
1420 static int ksz9x31_cable_test_fault_length(struct phy_device *phydev, u16 stat)
1421 {
1422         int dt = FIELD_GET(KSZ9x31_LMD_VCT_DATA_MASK, stat);
1423
1424         /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1425          *
1426          * distance to fault = (VCT_DATA - 22) * 4 / cable propagation velocity
1427          */
1428         if ((phydev->phy_id & MICREL_PHY_ID_MASK) == PHY_ID_KSZ9131)
1429                 dt = clamp(dt - 22, 0, 255);
1430
1431         return (dt * 400) / 10;
1432 }
1433
1434 static int ksz9x31_cable_test_wait_for_completion(struct phy_device *phydev)
1435 {
1436         int val, ret;
1437
1438         ret = phy_read_poll_timeout(phydev, KSZ9x31_LMD, val,
1439                                     !(val & KSZ9x31_LMD_VCT_EN),
1440                                     30000, 100000, true);
1441
1442         return ret < 0 ? ret : 0;
1443 }
1444
1445 static int ksz9x31_cable_test_get_pair(int pair)
1446 {
1447         static const int ethtool_pair[] = {
1448                 ETHTOOL_A_CABLE_PAIR_A,
1449                 ETHTOOL_A_CABLE_PAIR_B,
1450                 ETHTOOL_A_CABLE_PAIR_C,
1451                 ETHTOOL_A_CABLE_PAIR_D,
1452         };
1453
1454         return ethtool_pair[pair];
1455 }
1456
1457 static int ksz9x31_cable_test_one_pair(struct phy_device *phydev, int pair)
1458 {
1459         int ret, val;
1460
1461         /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1462          * To test each individual cable pair, set the cable pair in the Cable
1463          * Diagnostics Test Pair (VCT_PAIR[1:0]) field of the LinkMD Cable
1464          * Diagnostic Register, along with setting the Cable Diagnostics Test
1465          * Enable (VCT_EN) bit. The Cable Diagnostics Test Enable (VCT_EN) bit
1466          * will self clear when the test is concluded.
1467          */
1468         ret = phy_write(phydev, KSZ9x31_LMD,
1469                         KSZ9x31_LMD_VCT_EN | KSZ9x31_LMD_VCT_PAIR(pair));
1470         if (ret)
1471                 return ret;
1472
1473         ret = ksz9x31_cable_test_wait_for_completion(phydev);
1474         if (ret)
1475                 return ret;
1476
1477         val = phy_read(phydev, KSZ9x31_LMD);
1478         if (val < 0)
1479                 return val;
1480
1481         if (ksz9x31_cable_test_failed(val))
1482                 return -EAGAIN;
1483
1484         ret = ethnl_cable_test_result(phydev,
1485                                       ksz9x31_cable_test_get_pair(pair),
1486                                       ksz9x31_cable_test_result_trans(val));
1487         if (ret)
1488                 return ret;
1489
1490         if (!ksz9x31_cable_test_fault_length_valid(val))
1491                 return 0;
1492
1493         return ethnl_cable_test_fault_length(phydev,
1494                                              ksz9x31_cable_test_get_pair(pair),
1495                                              ksz9x31_cable_test_fault_length(phydev, val));
1496 }
1497
1498 static int ksz9x31_cable_test_get_status(struct phy_device *phydev,
1499                                          bool *finished)
1500 {
1501         struct kszphy_priv *priv = phydev->priv;
1502         unsigned long pair_mask = 0xf;
1503         int retries = 20;
1504         int pair, ret, rv;
1505
1506         *finished = false;
1507
1508         /* Try harder if link partner is active */
1509         while (pair_mask && retries--) {
1510                 for_each_set_bit(pair, &pair_mask, 4) {
1511                         ret = ksz9x31_cable_test_one_pair(phydev, pair);
1512                         if (ret == -EAGAIN)
1513                                 continue;
1514                         if (ret < 0)
1515                                 return ret;
1516                         clear_bit(pair, &pair_mask);
1517                 }
1518                 /* If link partner is in autonegotiation mode it will send 2ms
1519                  * of FLPs with at least 6ms of silence.
1520                  * Add 2ms sleep to have better chances to hit this silence.
1521                  */
1522                 if (pair_mask)
1523                         usleep_range(2000, 3000);
1524         }
1525
1526         /* Report remaining unfinished pair result as unknown. */
1527         for_each_set_bit(pair, &pair_mask, 4) {
1528                 ret = ethnl_cable_test_result(phydev,
1529                                               ksz9x31_cable_test_get_pair(pair),
1530                                               ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC);
1531         }
1532
1533         *finished = true;
1534
1535         /* Restore cached bits from before LinkMD got started. */
1536         rv = phy_modify(phydev, MII_CTRL1000,
1537                         CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER,
1538                         priv->vct_ctrl1000);
1539         if (rv)
1540                 return rv;
1541
1542         return ret;
1543 }
1544
1545 static int ksz8873mll_config_aneg(struct phy_device *phydev)
1546 {
1547         return 0;
1548 }
1549
1550 static int ksz886x_config_mdix(struct phy_device *phydev, u8 ctrl)
1551 {
1552         u16 val;
1553
1554         switch (ctrl) {
1555         case ETH_TP_MDI:
1556                 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX;
1557                 break;
1558         case ETH_TP_MDI_X:
1559                 /* Note: The naming of the bit KSZ886X_BMCR_FORCE_MDI is bit
1560                  * counter intuitive, the "-X" in "1 = Force MDI" in the data
1561                  * sheet seems to be missing:
1562                  * 1 = Force MDI (sic!) (transmit on RX+/RX- pins)
1563                  * 0 = Normal operation (transmit on TX+/TX- pins)
1564                  */
1565                 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX | KSZ886X_BMCR_FORCE_MDI;
1566                 break;
1567         case ETH_TP_MDI_AUTO:
1568                 val = 0;
1569                 break;
1570         default:
1571                 return 0;
1572         }
1573
1574         return phy_modify(phydev, MII_BMCR,
1575                           KSZ886X_BMCR_HP_MDIX | KSZ886X_BMCR_FORCE_MDI |
1576                           KSZ886X_BMCR_DISABLE_AUTO_MDIX,
1577                           KSZ886X_BMCR_HP_MDIX | val);
1578 }
1579
1580 static int ksz886x_config_aneg(struct phy_device *phydev)
1581 {
1582         int ret;
1583
1584         ret = genphy_config_aneg(phydev);
1585         if (ret)
1586                 return ret;
1587
1588         /* The MDI-X configuration is automatically changed by the PHY after
1589          * switching from autoneg off to on. So, take MDI-X configuration under
1590          * own control and set it after autoneg configuration was done.
1591          */
1592         return ksz886x_config_mdix(phydev, phydev->mdix_ctrl);
1593 }
1594
1595 static int ksz886x_mdix_update(struct phy_device *phydev)
1596 {
1597         int ret;
1598
1599         ret = phy_read(phydev, MII_BMCR);
1600         if (ret < 0)
1601                 return ret;
1602
1603         if (ret & KSZ886X_BMCR_DISABLE_AUTO_MDIX) {
1604                 if (ret & KSZ886X_BMCR_FORCE_MDI)
1605                         phydev->mdix_ctrl = ETH_TP_MDI_X;
1606                 else
1607                         phydev->mdix_ctrl = ETH_TP_MDI;
1608         } else {
1609                 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1610         }
1611
1612         ret = phy_read(phydev, MII_KSZPHY_CTRL);
1613         if (ret < 0)
1614                 return ret;
1615
1616         /* Same reverse logic as KSZ886X_BMCR_FORCE_MDI */
1617         if (ret & KSZ886X_CTRL_MDIX_STAT)
1618                 phydev->mdix = ETH_TP_MDI_X;
1619         else
1620                 phydev->mdix = ETH_TP_MDI;
1621
1622         return 0;
1623 }
1624
1625 static int ksz886x_read_status(struct phy_device *phydev)
1626 {
1627         int ret;
1628
1629         ret = ksz886x_mdix_update(phydev);
1630         if (ret < 0)
1631                 return ret;
1632
1633         return genphy_read_status(phydev);
1634 }
1635
1636 static int kszphy_get_sset_count(struct phy_device *phydev)
1637 {
1638         return ARRAY_SIZE(kszphy_hw_stats);
1639 }
1640
1641 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
1642 {
1643         int i;
1644
1645         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
1646                 strlcpy(data + i * ETH_GSTRING_LEN,
1647                         kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
1648         }
1649 }
1650
1651 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
1652 {
1653         struct kszphy_hw_stat stat = kszphy_hw_stats[i];
1654         struct kszphy_priv *priv = phydev->priv;
1655         int val;
1656         u64 ret;
1657
1658         val = phy_read(phydev, stat.reg);
1659         if (val < 0) {
1660                 ret = U64_MAX;
1661         } else {
1662                 val = val & ((1 << stat.bits) - 1);
1663                 priv->stats[i] += val;
1664                 ret = priv->stats[i];
1665         }
1666
1667         return ret;
1668 }
1669
1670 static void kszphy_get_stats(struct phy_device *phydev,
1671                              struct ethtool_stats *stats, u64 *data)
1672 {
1673         int i;
1674
1675         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
1676                 data[i] = kszphy_get_stat(phydev, i);
1677 }
1678
1679 static int kszphy_suspend(struct phy_device *phydev)
1680 {
1681         /* Disable PHY Interrupts */
1682         if (phy_interrupt_is_valid(phydev)) {
1683                 phydev->interrupts = PHY_INTERRUPT_DISABLED;
1684                 if (phydev->drv->config_intr)
1685                         phydev->drv->config_intr(phydev);
1686         }
1687
1688         return genphy_suspend(phydev);
1689 }
1690
1691 static int kszphy_resume(struct phy_device *phydev)
1692 {
1693         int ret;
1694
1695         genphy_resume(phydev);
1696
1697         /* After switching from power-down to normal mode, an internal global
1698          * reset is automatically generated. Wait a minimum of 1 ms before
1699          * read/write access to the PHY registers.
1700          */
1701         usleep_range(1000, 2000);
1702
1703         ret = kszphy_config_reset(phydev);
1704         if (ret)
1705                 return ret;
1706
1707         /* Enable PHY Interrupts */
1708         if (phy_interrupt_is_valid(phydev)) {
1709                 phydev->interrupts = PHY_INTERRUPT_ENABLED;
1710                 if (phydev->drv->config_intr)
1711                         phydev->drv->config_intr(phydev);
1712         }
1713
1714         return 0;
1715 }
1716
1717 static int kszphy_probe(struct phy_device *phydev)
1718 {
1719         const struct kszphy_type *type = phydev->drv->driver_data;
1720         const struct device_node *np = phydev->mdio.dev.of_node;
1721         struct kszphy_priv *priv;
1722         struct clk *clk;
1723         int ret;
1724
1725         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1726         if (!priv)
1727                 return -ENOMEM;
1728
1729         phydev->priv = priv;
1730
1731         priv->type = type;
1732
1733         if (type && type->led_mode_reg) {
1734                 ret = of_property_read_u32(np, "micrel,led-mode",
1735                                 &priv->led_mode);
1736                 if (ret)
1737                         priv->led_mode = -1;
1738
1739                 if (priv->led_mode > 3) {
1740                         phydev_err(phydev, "invalid led mode: 0x%02x\n",
1741                                    priv->led_mode);
1742                         priv->led_mode = -1;
1743                 }
1744         } else {
1745                 priv->led_mode = -1;
1746         }
1747
1748         clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
1749         /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
1750         if (!IS_ERR_OR_NULL(clk)) {
1751                 unsigned long rate = clk_get_rate(clk);
1752                 bool rmii_ref_clk_sel_25_mhz;
1753
1754                 if (type)
1755                         priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
1756                 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
1757                                 "micrel,rmii-reference-clock-select-25-mhz");
1758
1759                 if (rate > 24500000 && rate < 25500000) {
1760                         priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
1761                 } else if (rate > 49500000 && rate < 50500000) {
1762                         priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
1763                 } else {
1764                         phydev_err(phydev, "Clock rate out of range: %ld\n",
1765                                    rate);
1766                         return -EINVAL;
1767                 }
1768         }
1769
1770         if (ksz8041_fiber_mode(phydev))
1771                 phydev->port = PORT_FIBRE;
1772
1773         /* Support legacy board-file configuration */
1774         if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
1775                 priv->rmii_ref_clk_sel = true;
1776                 priv->rmii_ref_clk_sel_val = true;
1777         }
1778
1779         return 0;
1780 }
1781
1782 static int ksz886x_cable_test_start(struct phy_device *phydev)
1783 {
1784         if (phydev->dev_flags & MICREL_KSZ8_P1_ERRATA)
1785                 return -EOPNOTSUPP;
1786
1787         /* If autoneg is enabled, we won't be able to test cross pair
1788          * short. In this case, the PHY will "detect" a link and
1789          * confuse the internal state machine - disable auto neg here.
1790          * If autoneg is disabled, we should set the speed to 10mbit.
1791          */
1792         return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100);
1793 }
1794
1795 static int ksz886x_cable_test_result_trans(u16 status)
1796 {
1797         switch (FIELD_GET(KSZ8081_LMD_STAT_MASK, status)) {
1798         case KSZ8081_LMD_STAT_NORMAL:
1799                 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1800         case KSZ8081_LMD_STAT_SHORT:
1801                 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1802         case KSZ8081_LMD_STAT_OPEN:
1803                 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1804         case KSZ8081_LMD_STAT_FAIL:
1805                 fallthrough;
1806         default:
1807                 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1808         }
1809 }
1810
1811 static bool ksz886x_cable_test_failed(u16 status)
1812 {
1813         return FIELD_GET(KSZ8081_LMD_STAT_MASK, status) ==
1814                 KSZ8081_LMD_STAT_FAIL;
1815 }
1816
1817 static bool ksz886x_cable_test_fault_length_valid(u16 status)
1818 {
1819         switch (FIELD_GET(KSZ8081_LMD_STAT_MASK, status)) {
1820         case KSZ8081_LMD_STAT_OPEN:
1821                 fallthrough;
1822         case KSZ8081_LMD_STAT_SHORT:
1823                 return true;
1824         }
1825         return false;
1826 }
1827
1828 static int ksz886x_cable_test_fault_length(u16 status)
1829 {
1830         int dt;
1831
1832         /* According to the data sheet the distance to the fault is
1833          * DELTA_TIME * 0.4 meters.
1834          */
1835         dt = FIELD_GET(KSZ8081_LMD_DELTA_TIME_MASK, status);
1836
1837         return (dt * 400) / 10;
1838 }
1839
1840 static int ksz886x_cable_test_wait_for_completion(struct phy_device *phydev)
1841 {
1842         int val, ret;
1843
1844         ret = phy_read_poll_timeout(phydev, KSZ8081_LMD, val,
1845                                     !(val & KSZ8081_LMD_ENABLE_TEST),
1846                                     30000, 100000, true);
1847
1848         return ret < 0 ? ret : 0;
1849 }
1850
1851 static int ksz886x_cable_test_one_pair(struct phy_device *phydev, int pair)
1852 {
1853         static const int ethtool_pair[] = {
1854                 ETHTOOL_A_CABLE_PAIR_A,
1855                 ETHTOOL_A_CABLE_PAIR_B,
1856         };
1857         int ret, val, mdix;
1858
1859         /* There is no way to choice the pair, like we do one ksz9031.
1860          * We can workaround this limitation by using the MDI-X functionality.
1861          */
1862         if (pair == 0)
1863                 mdix = ETH_TP_MDI;
1864         else
1865                 mdix = ETH_TP_MDI_X;
1866
1867         switch (phydev->phy_id & MICREL_PHY_ID_MASK) {
1868         case PHY_ID_KSZ8081:
1869                 ret = ksz8081_config_mdix(phydev, mdix);
1870                 break;
1871         case PHY_ID_KSZ886X:
1872                 ret = ksz886x_config_mdix(phydev, mdix);
1873                 break;
1874         default:
1875                 ret = -ENODEV;
1876         }
1877
1878         if (ret)
1879                 return ret;
1880
1881         /* Now we are ready to fire. This command will send a 100ns pulse
1882          * to the pair.
1883          */
1884         ret = phy_write(phydev, KSZ8081_LMD, KSZ8081_LMD_ENABLE_TEST);
1885         if (ret)
1886                 return ret;
1887
1888         ret = ksz886x_cable_test_wait_for_completion(phydev);
1889         if (ret)
1890                 return ret;
1891
1892         val = phy_read(phydev, KSZ8081_LMD);
1893         if (val < 0)
1894                 return val;
1895
1896         if (ksz886x_cable_test_failed(val))
1897                 return -EAGAIN;
1898
1899         ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
1900                                       ksz886x_cable_test_result_trans(val));
1901         if (ret)
1902                 return ret;
1903
1904         if (!ksz886x_cable_test_fault_length_valid(val))
1905                 return 0;
1906
1907         return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
1908                                              ksz886x_cable_test_fault_length(val));
1909 }
1910
1911 static int ksz886x_cable_test_get_status(struct phy_device *phydev,
1912                                          bool *finished)
1913 {
1914         unsigned long pair_mask = 0x3;
1915         int retries = 20;
1916         int pair, ret;
1917
1918         *finished = false;
1919
1920         /* Try harder if link partner is active */
1921         while (pair_mask && retries--) {
1922                 for_each_set_bit(pair, &pair_mask, 4) {
1923                         ret = ksz886x_cable_test_one_pair(phydev, pair);
1924                         if (ret == -EAGAIN)
1925                                 continue;
1926                         if (ret < 0)
1927                                 return ret;
1928                         clear_bit(pair, &pair_mask);
1929                 }
1930                 /* If link partner is in autonegotiation mode it will send 2ms
1931                  * of FLPs with at least 6ms of silence.
1932                  * Add 2ms sleep to have better chances to hit this silence.
1933                  */
1934                 if (pair_mask)
1935                         msleep(2);
1936         }
1937
1938         *finished = true;
1939
1940         return ret;
1941 }
1942
1943 #define LAN_EXT_PAGE_ACCESS_CONTROL                     0x16
1944 #define LAN_EXT_PAGE_ACCESS_ADDRESS_DATA                0x17
1945 #define LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC                0x4000
1946
1947 #define LAN8814_QSGMII_SOFT_RESET                       0x43
1948 #define LAN8814_QSGMII_SOFT_RESET_BIT                   BIT(0)
1949 #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG                0x13
1950 #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA       BIT(3)
1951 #define LAN8814_ALIGN_SWAP                              0x4a
1952 #define LAN8814_ALIGN_TX_A_B_SWAP                       0x1
1953 #define LAN8814_ALIGN_TX_A_B_SWAP_MASK                  GENMASK(2, 0)
1954
1955 #define LAN8804_ALIGN_SWAP                              0x4a
1956 #define LAN8804_ALIGN_TX_A_B_SWAP                       0x1
1957 #define LAN8804_ALIGN_TX_A_B_SWAP_MASK                  GENMASK(2, 0)
1958 #define LAN8814_CLOCK_MANAGEMENT                        0xd
1959 #define LAN8814_LINK_QUALITY                            0x8e
1960
1961 static int lanphy_read_page_reg(struct phy_device *phydev, int page, u32 addr)
1962 {
1963         int data;
1964
1965         phy_lock_mdio_bus(phydev);
1966         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
1967         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
1968         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
1969                     (page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC));
1970         data = __phy_read(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA);
1971         phy_unlock_mdio_bus(phydev);
1972
1973         return data;
1974 }
1975
1976 static int lanphy_write_page_reg(struct phy_device *phydev, int page, u16 addr,
1977                                  u16 val)
1978 {
1979         phy_lock_mdio_bus(phydev);
1980         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
1981         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
1982         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
1983                     page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC);
1984
1985         val = __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val);
1986         if (val != 0)
1987                 phydev_err(phydev, "Error: phy_write has returned error %d\n",
1988                            val);
1989         phy_unlock_mdio_bus(phydev);
1990         return val;
1991 }
1992
1993 static int lan8814_config_ts_intr(struct phy_device *phydev, bool enable)
1994 {
1995         u16 val = 0;
1996
1997         if (enable)
1998                 val = PTP_TSU_INT_EN_PTP_TX_TS_EN_ |
1999                       PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ |
2000                       PTP_TSU_INT_EN_PTP_RX_TS_EN_ |
2001                       PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_;
2002
2003         return lanphy_write_page_reg(phydev, 5, PTP_TSU_INT_EN, val);
2004 }
2005
2006 static void lan8814_ptp_rx_ts_get(struct phy_device *phydev,
2007                                   u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2008 {
2009         *seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_HI);
2010         *seconds = (*seconds << 16) |
2011                    lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_LO);
2012
2013         *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_HI);
2014         *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2015                         lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_LO);
2016
2017         *seq_id = lanphy_read_page_reg(phydev, 5, PTP_RX_MSG_HEADER2);
2018 }
2019
2020 static void lan8814_ptp_tx_ts_get(struct phy_device *phydev,
2021                                   u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2022 {
2023         *seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_HI);
2024         *seconds = *seconds << 16 |
2025                    lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_LO);
2026
2027         *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_HI);
2028         *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2029                         lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_LO);
2030
2031         *seq_id = lanphy_read_page_reg(phydev, 5, PTP_TX_MSG_HEADER2);
2032 }
2033
2034 static int lan8814_ts_info(struct mii_timestamper *mii_ts, struct ethtool_ts_info *info)
2035 {
2036         struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2037         struct phy_device *phydev = ptp_priv->phydev;
2038         struct lan8814_shared_priv *shared = phydev->shared->priv;
2039
2040         info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
2041                                 SOF_TIMESTAMPING_RX_HARDWARE |
2042                                 SOF_TIMESTAMPING_RAW_HARDWARE;
2043
2044         info->phc_index = ptp_clock_index(shared->ptp_clock);
2045
2046         info->tx_types =
2047                 (1 << HWTSTAMP_TX_OFF) |
2048                 (1 << HWTSTAMP_TX_ON) |
2049                 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
2050
2051         info->rx_filters =
2052                 (1 << HWTSTAMP_FILTER_NONE) |
2053                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2054                 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2055                 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2056                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2057
2058         return 0;
2059 }
2060
2061 static void lan8814_flush_fifo(struct phy_device *phydev, bool egress)
2062 {
2063         int i;
2064
2065         for (i = 0; i < FIFO_SIZE; ++i)
2066                 lanphy_read_page_reg(phydev, 5,
2067                                      egress ? PTP_TX_MSG_HEADER2 : PTP_RX_MSG_HEADER2);
2068
2069         /* Read to clear overflow status bit */
2070         lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
2071 }
2072
2073 static int lan8814_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)
2074 {
2075         struct kszphy_ptp_priv *ptp_priv =
2076                           container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2077         struct phy_device *phydev = ptp_priv->phydev;
2078         struct lan8814_shared_priv *shared = phydev->shared->priv;
2079         struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2080         struct hwtstamp_config config;
2081         int txcfg = 0, rxcfg = 0;
2082         int pkt_ts_enable;
2083
2084         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2085                 return -EFAULT;
2086
2087         ptp_priv->hwts_tx_type = config.tx_type;
2088         ptp_priv->rx_filter = config.rx_filter;
2089
2090         switch (config.rx_filter) {
2091         case HWTSTAMP_FILTER_NONE:
2092                 ptp_priv->layer = 0;
2093                 ptp_priv->version = 0;
2094                 break;
2095         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2096         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2097         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2098                 ptp_priv->layer = PTP_CLASS_L4;
2099                 ptp_priv->version = PTP_CLASS_V2;
2100                 break;
2101         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2102         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2103         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2104                 ptp_priv->layer = PTP_CLASS_L2;
2105                 ptp_priv->version = PTP_CLASS_V2;
2106                 break;
2107         case HWTSTAMP_FILTER_PTP_V2_EVENT:
2108         case HWTSTAMP_FILTER_PTP_V2_SYNC:
2109         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2110                 ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
2111                 ptp_priv->version = PTP_CLASS_V2;
2112                 break;
2113         default:
2114                 return -ERANGE;
2115         }
2116
2117         if (ptp_priv->layer & PTP_CLASS_L2) {
2118                 rxcfg = PTP_RX_PARSE_CONFIG_LAYER2_EN_;
2119                 txcfg = PTP_TX_PARSE_CONFIG_LAYER2_EN_;
2120         } else if (ptp_priv->layer & PTP_CLASS_L4) {
2121                 rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
2122                 txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
2123         }
2124         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_PARSE_CONFIG, rxcfg);
2125         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_PARSE_CONFIG, txcfg);
2126
2127         pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
2128                         PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
2129         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
2130         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
2131
2132         if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC)
2133                 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
2134                                       PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
2135
2136         if (config.rx_filter != HWTSTAMP_FILTER_NONE)
2137                 lan8814_config_ts_intr(ptp_priv->phydev, true);
2138         else
2139                 lan8814_config_ts_intr(ptp_priv->phydev, false);
2140
2141         mutex_lock(&shared->shared_lock);
2142         if (config.rx_filter != HWTSTAMP_FILTER_NONE)
2143                 shared->ref++;
2144         else
2145                 shared->ref--;
2146
2147         if (shared->ref)
2148                 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
2149                                       PTP_CMD_CTL_PTP_ENABLE_);
2150         else
2151                 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
2152                                       PTP_CMD_CTL_PTP_DISABLE_);
2153         mutex_unlock(&shared->shared_lock);
2154
2155         /* In case of multiple starts and stops, these needs to be cleared */
2156         list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2157                 list_del(&rx_ts->list);
2158                 kfree(rx_ts);
2159         }
2160         skb_queue_purge(&ptp_priv->rx_queue);
2161         skb_queue_purge(&ptp_priv->tx_queue);
2162
2163         lan8814_flush_fifo(ptp_priv->phydev, false);
2164         lan8814_flush_fifo(ptp_priv->phydev, true);
2165
2166         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? -EFAULT : 0;
2167 }
2168
2169 static void lan8814_txtstamp(struct mii_timestamper *mii_ts,
2170                              struct sk_buff *skb, int type)
2171 {
2172         struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2173
2174         switch (ptp_priv->hwts_tx_type) {
2175         case HWTSTAMP_TX_ONESTEP_SYNC:
2176                 if (ptp_msg_is_sync(skb, type)) {
2177                         kfree_skb(skb);
2178                         return;
2179                 }
2180                 fallthrough;
2181         case HWTSTAMP_TX_ON:
2182                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2183                 skb_queue_tail(&ptp_priv->tx_queue, skb);
2184                 break;
2185         case HWTSTAMP_TX_OFF:
2186         default:
2187                 kfree_skb(skb);
2188                 break;
2189         }
2190 }
2191
2192 static void lan8814_get_sig_rx(struct sk_buff *skb, u16 *sig)
2193 {
2194         struct ptp_header *ptp_header;
2195         u32 type;
2196
2197         skb_push(skb, ETH_HLEN);
2198         type = ptp_classify_raw(skb);
2199         ptp_header = ptp_parse_header(skb, type);
2200         skb_pull_inline(skb, ETH_HLEN);
2201
2202         *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2203 }
2204
2205 static bool lan8814_match_rx_ts(struct kszphy_ptp_priv *ptp_priv,
2206                                 struct sk_buff *skb)
2207 {
2208         struct skb_shared_hwtstamps *shhwtstamps;
2209         struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2210         unsigned long flags;
2211         bool ret = false;
2212         u16 skb_sig;
2213
2214         lan8814_get_sig_rx(skb, &skb_sig);
2215
2216         /* Iterate over all RX timestamps and match it with the received skbs */
2217         spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2218         list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2219                 /* Check if we found the signature we were looking for. */
2220                 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2221                         continue;
2222
2223                 shhwtstamps = skb_hwtstamps(skb);
2224                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2225                 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds,
2226                                                   rx_ts->nsec);
2227                 list_del(&rx_ts->list);
2228                 kfree(rx_ts);
2229
2230                 ret = true;
2231                 break;
2232         }
2233         spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2234
2235         if (ret)
2236                 netif_rx(skb);
2237         return ret;
2238 }
2239
2240 static bool lan8814_rxtstamp(struct mii_timestamper *mii_ts, struct sk_buff *skb, int type)
2241 {
2242         struct kszphy_ptp_priv *ptp_priv =
2243                         container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2244
2245         if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
2246             type == PTP_CLASS_NONE)
2247                 return false;
2248
2249         if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
2250                 return false;
2251
2252         /* If we failed to match then add it to the queue for when the timestamp
2253          * will come
2254          */
2255         if (!lan8814_match_rx_ts(ptp_priv, skb))
2256                 skb_queue_tail(&ptp_priv->rx_queue, skb);
2257
2258         return true;
2259 }
2260
2261 static void lan8814_ptp_clock_set(struct phy_device *phydev,
2262                                   u32 seconds, u32 nano_seconds)
2263 {
2264         u32 sec_low, sec_high, nsec_low, nsec_high;
2265
2266         sec_low = seconds & 0xffff;
2267         sec_high = (seconds >> 16) & 0xffff;
2268         nsec_low = nano_seconds & 0xffff;
2269         nsec_high = (nano_seconds >> 16) & 0x3fff;
2270
2271         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_LO, sec_low);
2272         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_MID, sec_high);
2273         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_LO, nsec_low);
2274         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_HI, nsec_high);
2275
2276         lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_LOAD_);
2277 }
2278
2279 static void lan8814_ptp_clock_get(struct phy_device *phydev,
2280                                   u32 *seconds, u32 *nano_seconds)
2281 {
2282         lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_READ_);
2283
2284         *seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_MID);
2285         *seconds = (*seconds << 16) |
2286                    lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_LO);
2287
2288         *nano_seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_HI);
2289         *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2290                         lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_LO);
2291 }
2292
2293 static int lan8814_ptpci_gettime64(struct ptp_clock_info *ptpci,
2294                                    struct timespec64 *ts)
2295 {
2296         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2297                                                           ptp_clock_info);
2298         struct phy_device *phydev = shared->phydev;
2299         u32 nano_seconds;
2300         u32 seconds;
2301
2302         mutex_lock(&shared->shared_lock);
2303         lan8814_ptp_clock_get(phydev, &seconds, &nano_seconds);
2304         mutex_unlock(&shared->shared_lock);
2305         ts->tv_sec = seconds;
2306         ts->tv_nsec = nano_seconds;
2307
2308         return 0;
2309 }
2310
2311 static int lan8814_ptpci_settime64(struct ptp_clock_info *ptpci,
2312                                    const struct timespec64 *ts)
2313 {
2314         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2315                                                           ptp_clock_info);
2316         struct phy_device *phydev = shared->phydev;
2317
2318         mutex_lock(&shared->shared_lock);
2319         lan8814_ptp_clock_set(phydev, ts->tv_sec, ts->tv_nsec);
2320         mutex_unlock(&shared->shared_lock);
2321
2322         return 0;
2323 }
2324
2325 static void lan8814_ptp_clock_step(struct phy_device *phydev,
2326                                    s64 time_step_ns)
2327 {
2328         u32 nano_seconds_step;
2329         u64 abs_time_step_ns;
2330         u32 unsigned_seconds;
2331         u32 nano_seconds;
2332         u32 remainder;
2333         s32 seconds;
2334
2335         if (time_step_ns >  15000000000LL) {
2336                 /* convert to clock set */
2337                 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2338                 unsigned_seconds += div_u64_rem(time_step_ns, 1000000000LL,
2339                                                 &remainder);
2340                 nano_seconds += remainder;
2341                 if (nano_seconds >= 1000000000) {
2342                         unsigned_seconds++;
2343                         nano_seconds -= 1000000000;
2344                 }
2345                 lan8814_ptp_clock_set(phydev, unsigned_seconds, nano_seconds);
2346                 return;
2347         } else if (time_step_ns < -15000000000LL) {
2348                 /* convert to clock set */
2349                 time_step_ns = -time_step_ns;
2350
2351                 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2352                 unsigned_seconds -= div_u64_rem(time_step_ns, 1000000000LL,
2353                                                 &remainder);
2354                 nano_seconds_step = remainder;
2355                 if (nano_seconds < nano_seconds_step) {
2356                         unsigned_seconds--;
2357                         nano_seconds += 1000000000;
2358                 }
2359                 nano_seconds -= nano_seconds_step;
2360                 lan8814_ptp_clock_set(phydev, unsigned_seconds,
2361                                       nano_seconds);
2362                 return;
2363         }
2364
2365         /* do clock step */
2366         if (time_step_ns >= 0) {
2367                 abs_time_step_ns = (u64)time_step_ns;
2368                 seconds = (s32)div_u64_rem(abs_time_step_ns, 1000000000,
2369                                            &remainder);
2370                 nano_seconds = remainder;
2371         } else {
2372                 abs_time_step_ns = (u64)(-time_step_ns);
2373                 seconds = -((s32)div_u64_rem(abs_time_step_ns, 1000000000,
2374                             &remainder));
2375                 nano_seconds = remainder;
2376                 if (nano_seconds > 0) {
2377                         /* subtracting nano seconds is not allowed
2378                          * convert to subtracting from seconds,
2379                          * and adding to nanoseconds
2380                          */
2381                         seconds--;
2382                         nano_seconds = (1000000000 - nano_seconds);
2383                 }
2384         }
2385
2386         if (nano_seconds > 0) {
2387                 /* add 8 ns to cover the likely normal increment */
2388                 nano_seconds += 8;
2389         }
2390
2391         if (nano_seconds >= 1000000000) {
2392                 /* carry into seconds */
2393                 seconds++;
2394                 nano_seconds -= 1000000000;
2395         }
2396
2397         while (seconds) {
2398                 if (seconds > 0) {
2399                         u32 adjustment_value = (u32)seconds;
2400                         u16 adjustment_value_lo, adjustment_value_hi;
2401
2402                         if (adjustment_value > 0xF)
2403                                 adjustment_value = 0xF;
2404
2405                         adjustment_value_lo = adjustment_value & 0xffff;
2406                         adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2407
2408                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2409                                               adjustment_value_lo);
2410                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2411                                               PTP_LTC_STEP_ADJ_DIR_ |
2412                                               adjustment_value_hi);
2413                         seconds -= ((s32)adjustment_value);
2414                 } else {
2415                         u32 adjustment_value = (u32)(-seconds);
2416                         u16 adjustment_value_lo, adjustment_value_hi;
2417
2418                         if (adjustment_value > 0xF)
2419                                 adjustment_value = 0xF;
2420
2421                         adjustment_value_lo = adjustment_value & 0xffff;
2422                         adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2423
2424                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2425                                               adjustment_value_lo);
2426                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2427                                               adjustment_value_hi);
2428                         seconds += ((s32)adjustment_value);
2429                 }
2430                 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2431                                       PTP_CMD_CTL_PTP_LTC_STEP_SEC_);
2432         }
2433         if (nano_seconds) {
2434                 u16 nano_seconds_lo;
2435                 u16 nano_seconds_hi;
2436
2437                 nano_seconds_lo = nano_seconds & 0xffff;
2438                 nano_seconds_hi = (nano_seconds >> 16) & 0x3fff;
2439
2440                 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2441                                       nano_seconds_lo);
2442                 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2443                                       PTP_LTC_STEP_ADJ_DIR_ |
2444                                       nano_seconds_hi);
2445                 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2446                                       PTP_CMD_CTL_PTP_LTC_STEP_NSEC_);
2447         }
2448 }
2449
2450 static int lan8814_ptpci_adjtime(struct ptp_clock_info *ptpci, s64 delta)
2451 {
2452         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2453                                                           ptp_clock_info);
2454         struct phy_device *phydev = shared->phydev;
2455
2456         mutex_lock(&shared->shared_lock);
2457         lan8814_ptp_clock_step(phydev, delta);
2458         mutex_unlock(&shared->shared_lock);
2459
2460         return 0;
2461 }
2462
2463 static int lan8814_ptpci_adjfine(struct ptp_clock_info *ptpci, long scaled_ppm)
2464 {
2465         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2466                                                           ptp_clock_info);
2467         struct phy_device *phydev = shared->phydev;
2468         u16 kszphy_rate_adj_lo, kszphy_rate_adj_hi;
2469         bool positive = true;
2470         u32 kszphy_rate_adj;
2471
2472         if (scaled_ppm < 0) {
2473                 scaled_ppm = -scaled_ppm;
2474                 positive = false;
2475         }
2476
2477         kszphy_rate_adj = LAN8814_1PPM_FORMAT * (scaled_ppm >> 16);
2478         kszphy_rate_adj += (LAN8814_1PPM_FORMAT * (0xffff & scaled_ppm)) >> 16;
2479
2480         kszphy_rate_adj_lo = kszphy_rate_adj & 0xffff;
2481         kszphy_rate_adj_hi = (kszphy_rate_adj >> 16) & 0x3fff;
2482
2483         if (positive)
2484                 kszphy_rate_adj_hi |= PTP_CLOCK_RATE_ADJ_DIR_;
2485
2486         mutex_lock(&shared->shared_lock);
2487         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_HI, kszphy_rate_adj_hi);
2488         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_LO, kszphy_rate_adj_lo);
2489         mutex_unlock(&shared->shared_lock);
2490
2491         return 0;
2492 }
2493
2494 static void lan8814_get_sig_tx(struct sk_buff *skb, u16 *sig)
2495 {
2496         struct ptp_header *ptp_header;
2497         u32 type;
2498
2499         type = ptp_classify_raw(skb);
2500         ptp_header = ptp_parse_header(skb, type);
2501
2502         *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2503 }
2504
2505 static void lan8814_dequeue_tx_skb(struct kszphy_ptp_priv *ptp_priv)
2506 {
2507         struct phy_device *phydev = ptp_priv->phydev;
2508         struct skb_shared_hwtstamps shhwtstamps;
2509         struct sk_buff *skb, *skb_tmp;
2510         unsigned long flags;
2511         u32 seconds, nsec;
2512         bool ret = false;
2513         u16 skb_sig;
2514         u16 seq_id;
2515
2516         lan8814_ptp_tx_ts_get(phydev, &seconds, &nsec, &seq_id);
2517
2518         spin_lock_irqsave(&ptp_priv->tx_queue.lock, flags);
2519         skb_queue_walk_safe(&ptp_priv->tx_queue, skb, skb_tmp) {
2520                 lan8814_get_sig_tx(skb, &skb_sig);
2521
2522                 if (memcmp(&skb_sig, &seq_id, sizeof(seq_id)))
2523                         continue;
2524
2525                 __skb_unlink(skb, &ptp_priv->tx_queue);
2526                 ret = true;
2527                 break;
2528         }
2529         spin_unlock_irqrestore(&ptp_priv->tx_queue.lock, flags);
2530
2531         if (ret) {
2532                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2533                 shhwtstamps.hwtstamp = ktime_set(seconds, nsec);
2534                 skb_complete_tx_timestamp(skb, &shhwtstamps);
2535         }
2536 }
2537
2538 static void lan8814_get_tx_ts(struct kszphy_ptp_priv *ptp_priv)
2539 {
2540         struct phy_device *phydev = ptp_priv->phydev;
2541         u32 reg;
2542
2543         do {
2544                 lan8814_dequeue_tx_skb(ptp_priv);
2545
2546                 /* If other timestamps are available in the FIFO,
2547                  * process them.
2548                  */
2549                 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2550         } while (PTP_CAP_INFO_TX_TS_CNT_GET_(reg) > 0);
2551 }
2552
2553 static bool lan8814_match_skb(struct kszphy_ptp_priv *ptp_priv,
2554                               struct lan8814_ptp_rx_ts *rx_ts)
2555 {
2556         struct skb_shared_hwtstamps *shhwtstamps;
2557         struct sk_buff *skb, *skb_tmp;
2558         unsigned long flags;
2559         bool ret = false;
2560         u16 skb_sig;
2561
2562         spin_lock_irqsave(&ptp_priv->rx_queue.lock, flags);
2563         skb_queue_walk_safe(&ptp_priv->rx_queue, skb, skb_tmp) {
2564                 lan8814_get_sig_rx(skb, &skb_sig);
2565
2566                 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2567                         continue;
2568
2569                 __skb_unlink(skb, &ptp_priv->rx_queue);
2570
2571                 ret = true;
2572                 break;
2573         }
2574         spin_unlock_irqrestore(&ptp_priv->rx_queue.lock, flags);
2575
2576         if (ret) {
2577                 shhwtstamps = skb_hwtstamps(skb);
2578                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2579                 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds, rx_ts->nsec);
2580                 netif_rx(skb);
2581         }
2582
2583         return ret;
2584 }
2585
2586 static void lan8814_get_rx_ts(struct kszphy_ptp_priv *ptp_priv)
2587 {
2588         struct phy_device *phydev = ptp_priv->phydev;
2589         struct lan8814_ptp_rx_ts *rx_ts;
2590         unsigned long flags;
2591         u32 reg;
2592
2593         do {
2594                 rx_ts = kzalloc(sizeof(*rx_ts), GFP_KERNEL);
2595                 if (!rx_ts)
2596                         return;
2597
2598                 lan8814_ptp_rx_ts_get(phydev, &rx_ts->seconds, &rx_ts->nsec,
2599                                       &rx_ts->seq_id);
2600
2601                 /* If we failed to match the skb add it to the queue for when
2602                  * the frame will come
2603                  */
2604                 if (!lan8814_match_skb(ptp_priv, rx_ts)) {
2605                         spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2606                         list_add(&rx_ts->list, &ptp_priv->rx_ts_list);
2607                         spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2608                 } else {
2609                         kfree(rx_ts);
2610                 }
2611
2612                 /* If other timestamps are available in the FIFO,
2613                  * process them.
2614                  */
2615                 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2616         } while (PTP_CAP_INFO_RX_TS_CNT_GET_(reg) > 0);
2617 }
2618
2619 static void lan8814_handle_ptp_interrupt(struct phy_device *phydev)
2620 {
2621         struct kszphy_priv *priv = phydev->priv;
2622         struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
2623         u16 status;
2624
2625         status = lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
2626         if (status & PTP_TSU_INT_STS_PTP_TX_TS_EN_)
2627                 lan8814_get_tx_ts(ptp_priv);
2628
2629         if (status & PTP_TSU_INT_STS_PTP_RX_TS_EN_)
2630                 lan8814_get_rx_ts(ptp_priv);
2631
2632         if (status & PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_) {
2633                 lan8814_flush_fifo(phydev, true);
2634                 skb_queue_purge(&ptp_priv->tx_queue);
2635         }
2636
2637         if (status & PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_) {
2638                 lan8814_flush_fifo(phydev, false);
2639                 skb_queue_purge(&ptp_priv->rx_queue);
2640         }
2641 }
2642
2643 static int lan8804_config_init(struct phy_device *phydev)
2644 {
2645         int val;
2646
2647         /* MDI-X setting for swap A,B transmit */
2648         val = lanphy_read_page_reg(phydev, 2, LAN8804_ALIGN_SWAP);
2649         val &= ~LAN8804_ALIGN_TX_A_B_SWAP_MASK;
2650         val |= LAN8804_ALIGN_TX_A_B_SWAP;
2651         lanphy_write_page_reg(phydev, 2, LAN8804_ALIGN_SWAP, val);
2652
2653         /* Make sure that the PHY will not stop generating the clock when the
2654          * link partner goes down
2655          */
2656         lanphy_write_page_reg(phydev, 31, LAN8814_CLOCK_MANAGEMENT, 0x27e);
2657         lanphy_read_page_reg(phydev, 1, LAN8814_LINK_QUALITY);
2658
2659         return 0;
2660 }
2661
2662 static irqreturn_t lan8814_handle_interrupt(struct phy_device *phydev)
2663 {
2664         int irq_status, tsu_irq_status;
2665         int ret = IRQ_NONE;
2666
2667         irq_status = phy_read(phydev, LAN8814_INTS);
2668         if (irq_status < 0) {
2669                 phy_error(phydev);
2670                 return IRQ_NONE;
2671         }
2672
2673         if (irq_status & LAN8814_INT_LINK) {
2674                 phy_trigger_machine(phydev);
2675                 ret = IRQ_HANDLED;
2676         }
2677
2678         while (1) {
2679                 tsu_irq_status = lanphy_read_page_reg(phydev, 4,
2680                                                       LAN8814_INTR_STS_REG);
2681
2682                 if (tsu_irq_status > 0 &&
2683                     (tsu_irq_status & (LAN8814_INTR_STS_REG_1588_TSU0_ |
2684                                        LAN8814_INTR_STS_REG_1588_TSU1_ |
2685                                        LAN8814_INTR_STS_REG_1588_TSU2_ |
2686                                        LAN8814_INTR_STS_REG_1588_TSU3_))) {
2687                         lan8814_handle_ptp_interrupt(phydev);
2688                         ret = IRQ_HANDLED;
2689                 } else {
2690                         break;
2691                 }
2692         }
2693
2694         return ret;
2695 }
2696
2697 static int lan8814_ack_interrupt(struct phy_device *phydev)
2698 {
2699         /* bit[12..0] int status, which is a read and clear register. */
2700         int rc;
2701
2702         rc = phy_read(phydev, LAN8814_INTS);
2703
2704         return (rc < 0) ? rc : 0;
2705 }
2706
2707 static int lan8814_config_intr(struct phy_device *phydev)
2708 {
2709         int err;
2710
2711         lanphy_write_page_reg(phydev, 4, LAN8814_INTR_CTRL_REG,
2712                               LAN8814_INTR_CTRL_REG_POLARITY |
2713                               LAN8814_INTR_CTRL_REG_INTR_ENABLE);
2714
2715         /* enable / disable interrupts */
2716         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
2717                 err = lan8814_ack_interrupt(phydev);
2718                 if (err)
2719                         return err;
2720
2721                 err =  phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
2722         } else {
2723                 err =  phy_write(phydev, LAN8814_INTC, 0);
2724                 if (err)
2725                         return err;
2726
2727                 err = lan8814_ack_interrupt(phydev);
2728         }
2729
2730         return err;
2731 }
2732
2733 static void lan8814_ptp_init(struct phy_device *phydev)
2734 {
2735         struct kszphy_priv *priv = phydev->priv;
2736         struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
2737         u32 temp;
2738
2739         if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) ||
2740             !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
2741                 return;
2742
2743         lanphy_write_page_reg(phydev, 5, TSU_HARD_RESET, TSU_HARD_RESET_);
2744
2745         temp = lanphy_read_page_reg(phydev, 5, PTP_TX_MOD);
2746         temp |= PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
2747         lanphy_write_page_reg(phydev, 5, PTP_TX_MOD, temp);
2748
2749         temp = lanphy_read_page_reg(phydev, 5, PTP_RX_MOD);
2750         temp |= PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
2751         lanphy_write_page_reg(phydev, 5, PTP_RX_MOD, temp);
2752
2753         lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_CONFIG, 0);
2754         lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_CONFIG, 0);
2755
2756         /* Removing default registers configs related to L2 and IP */
2757         lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_L2_ADDR_EN, 0);
2758         lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_L2_ADDR_EN, 0);
2759         lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_IP_ADDR_EN, 0);
2760         lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_IP_ADDR_EN, 0);
2761
2762         skb_queue_head_init(&ptp_priv->tx_queue);
2763         skb_queue_head_init(&ptp_priv->rx_queue);
2764         INIT_LIST_HEAD(&ptp_priv->rx_ts_list);
2765         spin_lock_init(&ptp_priv->rx_ts_lock);
2766
2767         ptp_priv->phydev = phydev;
2768
2769         ptp_priv->mii_ts.rxtstamp = lan8814_rxtstamp;
2770         ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
2771         ptp_priv->mii_ts.hwtstamp = lan8814_hwtstamp;
2772         ptp_priv->mii_ts.ts_info  = lan8814_ts_info;
2773
2774         phydev->mii_ts = &ptp_priv->mii_ts;
2775 }
2776
2777 static int lan8814_ptp_probe_once(struct phy_device *phydev)
2778 {
2779         struct lan8814_shared_priv *shared = phydev->shared->priv;
2780
2781         if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) ||
2782             !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
2783                 return 0;
2784
2785         /* Initialise shared lock for clock*/
2786         mutex_init(&shared->shared_lock);
2787
2788         shared->ptp_clock_info.owner = THIS_MODULE;
2789         snprintf(shared->ptp_clock_info.name, 30, "%s", phydev->drv->name);
2790         shared->ptp_clock_info.max_adj = 31249999;
2791         shared->ptp_clock_info.n_alarm = 0;
2792         shared->ptp_clock_info.n_ext_ts = 0;
2793         shared->ptp_clock_info.n_pins = 0;
2794         shared->ptp_clock_info.pps = 0;
2795         shared->ptp_clock_info.pin_config = NULL;
2796         shared->ptp_clock_info.adjfine = lan8814_ptpci_adjfine;
2797         shared->ptp_clock_info.adjtime = lan8814_ptpci_adjtime;
2798         shared->ptp_clock_info.gettime64 = lan8814_ptpci_gettime64;
2799         shared->ptp_clock_info.settime64 = lan8814_ptpci_settime64;
2800         shared->ptp_clock_info.getcrosststamp = NULL;
2801
2802         shared->ptp_clock = ptp_clock_register(&shared->ptp_clock_info,
2803                                                &phydev->mdio.dev);
2804         if (IS_ERR_OR_NULL(shared->ptp_clock)) {
2805                 phydev_err(phydev, "ptp_clock_register failed %lu\n",
2806                            PTR_ERR(shared->ptp_clock));
2807                 return -EINVAL;
2808         }
2809
2810         phydev_dbg(phydev, "successfully registered ptp clock\n");
2811
2812         shared->phydev = phydev;
2813
2814         /* The EP.4 is shared between all the PHYs in the package and also it
2815          * can be accessed by any of the PHYs
2816          */
2817         lanphy_write_page_reg(phydev, 4, LTC_HARD_RESET, LTC_HARD_RESET_);
2818         lanphy_write_page_reg(phydev, 4, PTP_OPERATING_MODE,
2819                               PTP_OPERATING_MODE_STANDALONE_);
2820
2821         return 0;
2822 }
2823
2824 static int lan8814_config_init(struct phy_device *phydev)
2825 {
2826         int val;
2827
2828         /* Reset the PHY */
2829         val = lanphy_read_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET);
2830         val |= LAN8814_QSGMII_SOFT_RESET_BIT;
2831         lanphy_write_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET, val);
2832
2833         /* Disable ANEG with QSGMII PCS Host side */
2834         val = lanphy_read_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG);
2835         val &= ~LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA;
2836         lanphy_write_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, val);
2837
2838         /* MDI-X setting for swap A,B transmit */
2839         val = lanphy_read_page_reg(phydev, 2, LAN8814_ALIGN_SWAP);
2840         val &= ~LAN8814_ALIGN_TX_A_B_SWAP_MASK;
2841         val |= LAN8814_ALIGN_TX_A_B_SWAP;
2842         lanphy_write_page_reg(phydev, 2, LAN8814_ALIGN_SWAP, val);
2843
2844         return 0;
2845 }
2846
2847 /* It is expected that there will not be any 'lan8814_take_coma_mode'
2848  * function called in suspend. Because the GPIO line can be shared, so if one of
2849  * the phys goes back in coma mode, then all the other PHYs will go, which is
2850  * wrong.
2851  */
2852 static int lan8814_release_coma_mode(struct phy_device *phydev)
2853 {
2854         struct gpio_desc *gpiod;
2855
2856         gpiod = devm_gpiod_get_optional(&phydev->mdio.dev, "coma-mode",
2857                                         GPIOD_OUT_HIGH_OPEN_DRAIN |
2858                                         GPIOD_FLAGS_BIT_NONEXCLUSIVE);
2859         if (IS_ERR(gpiod))
2860                 return PTR_ERR(gpiod);
2861
2862         gpiod_set_consumer_name(gpiod, "LAN8814 coma mode");
2863         gpiod_set_value_cansleep(gpiod, 0);
2864
2865         return 0;
2866 }
2867
2868 static int lan8814_probe(struct phy_device *phydev)
2869 {
2870         struct kszphy_priv *priv;
2871         u16 addr;
2872         int err;
2873
2874         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
2875         if (!priv)
2876                 return -ENOMEM;
2877
2878         priv->led_mode = -1;
2879
2880         phydev->priv = priv;
2881
2882         /* Strap-in value for PHY address, below register read gives starting
2883          * phy address value
2884          */
2885         addr = lanphy_read_page_reg(phydev, 4, 0) & 0x1F;
2886         devm_phy_package_join(&phydev->mdio.dev, phydev,
2887                               addr, sizeof(struct lan8814_shared_priv));
2888
2889         if (phy_package_init_once(phydev)) {
2890                 err = lan8814_release_coma_mode(phydev);
2891                 if (err)
2892                         return err;
2893
2894                 err = lan8814_ptp_probe_once(phydev);
2895                 if (err)
2896                         return err;
2897         }
2898
2899         lan8814_ptp_init(phydev);
2900
2901         return 0;
2902 }
2903
2904 static struct phy_driver ksphy_driver[] = {
2905 {
2906         .phy_id         = PHY_ID_KS8737,
2907         .phy_id_mask    = MICREL_PHY_ID_MASK,
2908         .name           = "Micrel KS8737",
2909         /* PHY_BASIC_FEATURES */
2910         .driver_data    = &ks8737_type,
2911         .probe          = kszphy_probe,
2912         .config_init    = kszphy_config_init,
2913         .config_intr    = kszphy_config_intr,
2914         .handle_interrupt = kszphy_handle_interrupt,
2915         .suspend        = kszphy_suspend,
2916         .resume         = kszphy_resume,
2917 }, {
2918         .phy_id         = PHY_ID_KSZ8021,
2919         .phy_id_mask    = 0x00ffffff,
2920         .name           = "Micrel KSZ8021 or KSZ8031",
2921         /* PHY_BASIC_FEATURES */
2922         .driver_data    = &ksz8021_type,
2923         .probe          = kszphy_probe,
2924         .config_init    = kszphy_config_init,
2925         .config_intr    = kszphy_config_intr,
2926         .handle_interrupt = kszphy_handle_interrupt,
2927         .get_sset_count = kszphy_get_sset_count,
2928         .get_strings    = kszphy_get_strings,
2929         .get_stats      = kszphy_get_stats,
2930         .suspend        = kszphy_suspend,
2931         .resume         = kszphy_resume,
2932 }, {
2933         .phy_id         = PHY_ID_KSZ8031,
2934         .phy_id_mask    = 0x00ffffff,
2935         .name           = "Micrel KSZ8031",
2936         /* PHY_BASIC_FEATURES */
2937         .driver_data    = &ksz8021_type,
2938         .probe          = kszphy_probe,
2939         .config_init    = kszphy_config_init,
2940         .config_intr    = kszphy_config_intr,
2941         .handle_interrupt = kszphy_handle_interrupt,
2942         .get_sset_count = kszphy_get_sset_count,
2943         .get_strings    = kszphy_get_strings,
2944         .get_stats      = kszphy_get_stats,
2945         .suspend        = kszphy_suspend,
2946         .resume         = kszphy_resume,
2947 }, {
2948         .phy_id         = PHY_ID_KSZ8041,
2949         .phy_id_mask    = MICREL_PHY_ID_MASK,
2950         .name           = "Micrel KSZ8041",
2951         /* PHY_BASIC_FEATURES */
2952         .driver_data    = &ksz8041_type,
2953         .probe          = kszphy_probe,
2954         .config_init    = ksz8041_config_init,
2955         .config_aneg    = ksz8041_config_aneg,
2956         .config_intr    = kszphy_config_intr,
2957         .handle_interrupt = kszphy_handle_interrupt,
2958         .get_sset_count = kszphy_get_sset_count,
2959         .get_strings    = kszphy_get_strings,
2960         .get_stats      = kszphy_get_stats,
2961         /* No suspend/resume callbacks because of errata DS80000700A,
2962          * receiver error following software power down.
2963          */
2964 }, {
2965         .phy_id         = PHY_ID_KSZ8041RNLI,
2966         .phy_id_mask    = MICREL_PHY_ID_MASK,
2967         .name           = "Micrel KSZ8041RNLI",
2968         /* PHY_BASIC_FEATURES */
2969         .driver_data    = &ksz8041_type,
2970         .probe          = kszphy_probe,
2971         .config_init    = kszphy_config_init,
2972         .config_intr    = kszphy_config_intr,
2973         .handle_interrupt = kszphy_handle_interrupt,
2974         .get_sset_count = kszphy_get_sset_count,
2975         .get_strings    = kszphy_get_strings,
2976         .get_stats      = kszphy_get_stats,
2977         .suspend        = kszphy_suspend,
2978         .resume         = kszphy_resume,
2979 }, {
2980         .name           = "Micrel KSZ8051",
2981         /* PHY_BASIC_FEATURES */
2982         .driver_data    = &ksz8051_type,
2983         .probe          = kszphy_probe,
2984         .config_init    = kszphy_config_init,
2985         .config_intr    = kszphy_config_intr,
2986         .handle_interrupt = kszphy_handle_interrupt,
2987         .get_sset_count = kszphy_get_sset_count,
2988         .get_strings    = kszphy_get_strings,
2989         .get_stats      = kszphy_get_stats,
2990         .match_phy_device = ksz8051_match_phy_device,
2991         .suspend        = kszphy_suspend,
2992         .resume         = kszphy_resume,
2993 }, {
2994         .phy_id         = PHY_ID_KSZ8001,
2995         .name           = "Micrel KSZ8001 or KS8721",
2996         .phy_id_mask    = 0x00fffffc,
2997         /* PHY_BASIC_FEATURES */
2998         .driver_data    = &ksz8041_type,
2999         .probe          = kszphy_probe,
3000         .config_init    = kszphy_config_init,
3001         .config_intr    = kszphy_config_intr,
3002         .handle_interrupt = kszphy_handle_interrupt,
3003         .get_sset_count = kszphy_get_sset_count,
3004         .get_strings    = kszphy_get_strings,
3005         .get_stats      = kszphy_get_stats,
3006         .suspend        = kszphy_suspend,
3007         .resume         = kszphy_resume,
3008 }, {
3009         .phy_id         = PHY_ID_KSZ8081,
3010         .name           = "Micrel KSZ8081 or KSZ8091",
3011         .phy_id_mask    = MICREL_PHY_ID_MASK,
3012         .flags          = PHY_POLL_CABLE_TEST,
3013         /* PHY_BASIC_FEATURES */
3014         .driver_data    = &ksz8081_type,
3015         .probe          = kszphy_probe,
3016         .config_init    = ksz8081_config_init,
3017         .soft_reset     = genphy_soft_reset,
3018         .config_aneg    = ksz8081_config_aneg,
3019         .read_status    = ksz8081_read_status,
3020         .config_intr    = kszphy_config_intr,
3021         .handle_interrupt = kszphy_handle_interrupt,
3022         .get_sset_count = kszphy_get_sset_count,
3023         .get_strings    = kszphy_get_strings,
3024         .get_stats      = kszphy_get_stats,
3025         .suspend        = kszphy_suspend,
3026         .resume         = kszphy_resume,
3027         .cable_test_start       = ksz886x_cable_test_start,
3028         .cable_test_get_status  = ksz886x_cable_test_get_status,
3029 }, {
3030         .phy_id         = PHY_ID_KSZ8061,
3031         .name           = "Micrel KSZ8061",
3032         .phy_id_mask    = MICREL_PHY_ID_MASK,
3033         /* PHY_BASIC_FEATURES */
3034         .probe          = kszphy_probe,
3035         .config_init    = ksz8061_config_init,
3036         .config_intr    = kszphy_config_intr,
3037         .handle_interrupt = kszphy_handle_interrupt,
3038         .suspend        = kszphy_suspend,
3039         .resume         = kszphy_resume,
3040 }, {
3041         .phy_id         = PHY_ID_KSZ9021,
3042         .phy_id_mask    = 0x000ffffe,
3043         .name           = "Micrel KSZ9021 Gigabit PHY",
3044         /* PHY_GBIT_FEATURES */
3045         .driver_data    = &ksz9021_type,
3046         .probe          = kszphy_probe,
3047         .get_features   = ksz9031_get_features,
3048         .config_init    = ksz9021_config_init,
3049         .config_intr    = kszphy_config_intr,
3050         .handle_interrupt = kszphy_handle_interrupt,
3051         .get_sset_count = kszphy_get_sset_count,
3052         .get_strings    = kszphy_get_strings,
3053         .get_stats      = kszphy_get_stats,
3054         .suspend        = kszphy_suspend,
3055         .resume         = kszphy_resume,
3056         .read_mmd       = genphy_read_mmd_unsupported,
3057         .write_mmd      = genphy_write_mmd_unsupported,
3058 }, {
3059         .phy_id         = PHY_ID_KSZ9031,
3060         .phy_id_mask    = MICREL_PHY_ID_MASK,
3061         .name           = "Micrel KSZ9031 Gigabit PHY",
3062         .flags          = PHY_POLL_CABLE_TEST,
3063         .driver_data    = &ksz9021_type,
3064         .probe          = kszphy_probe,
3065         .get_features   = ksz9031_get_features,
3066         .config_init    = ksz9031_config_init,
3067         .soft_reset     = genphy_soft_reset,
3068         .read_status    = ksz9031_read_status,
3069         .config_intr    = kszphy_config_intr,
3070         .handle_interrupt = kszphy_handle_interrupt,
3071         .get_sset_count = kszphy_get_sset_count,
3072         .get_strings    = kszphy_get_strings,
3073         .get_stats      = kszphy_get_stats,
3074         .suspend        = kszphy_suspend,
3075         .resume         = kszphy_resume,
3076         .cable_test_start       = ksz9x31_cable_test_start,
3077         .cable_test_get_status  = ksz9x31_cable_test_get_status,
3078 }, {
3079         .phy_id         = PHY_ID_LAN8814,
3080         .phy_id_mask    = MICREL_PHY_ID_MASK,
3081         .name           = "Microchip INDY Gigabit Quad PHY",
3082         .config_init    = lan8814_config_init,
3083         .probe          = lan8814_probe,
3084         .soft_reset     = genphy_soft_reset,
3085         .read_status    = ksz9031_read_status,
3086         .get_sset_count = kszphy_get_sset_count,
3087         .get_strings    = kszphy_get_strings,
3088         .get_stats      = kszphy_get_stats,
3089         .suspend        = genphy_suspend,
3090         .resume         = kszphy_resume,
3091         .config_intr    = lan8814_config_intr,
3092         .handle_interrupt = lan8814_handle_interrupt,
3093 }, {
3094         .phy_id         = PHY_ID_LAN8804,
3095         .phy_id_mask    = MICREL_PHY_ID_MASK,
3096         .name           = "Microchip LAN966X Gigabit PHY",
3097         .config_init    = lan8804_config_init,
3098         .driver_data    = &ksz9021_type,
3099         .probe          = kszphy_probe,
3100         .soft_reset     = genphy_soft_reset,
3101         .read_status    = ksz9031_read_status,
3102         .get_sset_count = kszphy_get_sset_count,
3103         .get_strings    = kszphy_get_strings,
3104         .get_stats      = kszphy_get_stats,
3105         .suspend        = genphy_suspend,
3106         .resume         = kszphy_resume,
3107 }, {
3108         .phy_id         = PHY_ID_KSZ9131,
3109         .phy_id_mask    = MICREL_PHY_ID_MASK,
3110         .name           = "Microchip KSZ9131 Gigabit PHY",
3111         /* PHY_GBIT_FEATURES */
3112         .flags          = PHY_POLL_CABLE_TEST,
3113         .driver_data    = &ksz9021_type,
3114         .probe          = kszphy_probe,
3115         .config_init    = ksz9131_config_init,
3116         .config_intr    = kszphy_config_intr,
3117         .handle_interrupt = kszphy_handle_interrupt,
3118         .get_sset_count = kszphy_get_sset_count,
3119         .get_strings    = kszphy_get_strings,
3120         .get_stats      = kszphy_get_stats,
3121         .suspend        = kszphy_suspend,
3122         .resume         = kszphy_resume,
3123         .cable_test_start       = ksz9x31_cable_test_start,
3124         .cable_test_get_status  = ksz9x31_cable_test_get_status,
3125 }, {
3126         .phy_id         = PHY_ID_KSZ8873MLL,
3127         .phy_id_mask    = MICREL_PHY_ID_MASK,
3128         .name           = "Micrel KSZ8873MLL Switch",
3129         /* PHY_BASIC_FEATURES */
3130         .config_init    = kszphy_config_init,
3131         .config_aneg    = ksz8873mll_config_aneg,
3132         .read_status    = ksz8873mll_read_status,
3133         .suspend        = genphy_suspend,
3134         .resume         = genphy_resume,
3135 }, {
3136         .phy_id         = PHY_ID_KSZ886X,
3137         .phy_id_mask    = MICREL_PHY_ID_MASK,
3138         .name           = "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch",
3139         /* PHY_BASIC_FEATURES */
3140         .flags          = PHY_POLL_CABLE_TEST,
3141         .config_init    = kszphy_config_init,
3142         .config_aneg    = ksz886x_config_aneg,
3143         .read_status    = ksz886x_read_status,
3144         .suspend        = genphy_suspend,
3145         .resume         = genphy_resume,
3146         .cable_test_start       = ksz886x_cable_test_start,
3147         .cable_test_get_status  = ksz886x_cable_test_get_status,
3148 }, {
3149         .name           = "Micrel KSZ87XX Switch",
3150         /* PHY_BASIC_FEATURES */
3151         .config_init    = kszphy_config_init,
3152         .match_phy_device = ksz8795_match_phy_device,
3153         .suspend        = genphy_suspend,
3154         .resume         = genphy_resume,
3155 }, {
3156         .phy_id         = PHY_ID_KSZ9477,
3157         .phy_id_mask    = MICREL_PHY_ID_MASK,
3158         .name           = "Microchip KSZ9477",
3159         /* PHY_GBIT_FEATURES */
3160         .config_init    = kszphy_config_init,
3161         .suspend        = genphy_suspend,
3162         .resume         = genphy_resume,
3163 } };
3164
3165 module_phy_driver(ksphy_driver);
3166
3167 MODULE_DESCRIPTION("Micrel PHY driver");
3168 MODULE_AUTHOR("David J. Choi");
3169 MODULE_LICENSE("GPL");
3170
3171 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
3172         { PHY_ID_KSZ9021, 0x000ffffe },
3173         { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
3174         { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
3175         { PHY_ID_KSZ8001, 0x00fffffc },
3176         { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
3177         { PHY_ID_KSZ8021, 0x00ffffff },
3178         { PHY_ID_KSZ8031, 0x00ffffff },
3179         { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
3180         { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
3181         { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
3182         { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
3183         { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
3184         { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
3185         { PHY_ID_LAN8814, MICREL_PHY_ID_MASK },
3186         { PHY_ID_LAN8804, MICREL_PHY_ID_MASK },
3187         { }
3188 };
3189
3190 MODULE_DEVICE_TABLE(mdio, micrel_tbl);