git.itanic.dy.fi Git - linux-stable/blob - drivers/tty/serial/fsl_lpuart.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Freescale lpuart serial port driver
   4  *
   5  *  Copyright 2012-2014 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/console.h>
  10 #include <linux/delay.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/dmapool.h>
  14 #include <linux/io.h>
  15 #include <linux/irq.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/of_device.h>
  19 #include <linux/of_dma.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/slab.h>
  22 #include <linux/tty_flip.h>
  23
  24 /* All registers are 8-bit width */
  25 #define UARTBDH                 0x00
  26 #define UARTBDL                 0x01
  27 #define UARTCR1                 0x02
  28 #define UARTCR2                 0x03
  29 #define UARTSR1                 0x04
  30 #define UARTCR3                 0x06
  31 #define UARTDR                  0x07
  32 #define UARTCR4                 0x0a
  33 #define UARTCR5                 0x0b
  34 #define UARTMODEM               0x0d
  35 #define UARTPFIFO               0x10
  36 #define UARTCFIFO               0x11
  37 #define UARTSFIFO               0x12
  38 #define UARTTWFIFO              0x13
  39 #define UARTTCFIFO              0x14
  40 #define UARTRWFIFO              0x15
  41
  42 #define UARTBDH_LBKDIE          0x80
  43 #define UARTBDH_RXEDGIE         0x40
  44 #define UARTBDH_SBR_MASK        0x1f
  45
  46 #define UARTCR1_LOOPS           0x80
  47 #define UARTCR1_RSRC            0x20
  48 #define UARTCR1_M               0x10
  49 #define UARTCR1_WAKE            0x08
  50 #define UARTCR1_ILT             0x04
  51 #define UARTCR1_PE              0x02
  52 #define UARTCR1_PT              0x01
  53
  54 #define UARTCR2_TIE             0x80
  55 #define UARTCR2_TCIE            0x40
  56 #define UARTCR2_RIE             0x20
  57 #define UARTCR2_ILIE            0x10
  58 #define UARTCR2_TE              0x08
  59 #define UARTCR2_RE              0x04
  60 #define UARTCR2_RWU             0x02
  61 #define UARTCR2_SBK             0x01
  62
  63 #define UARTSR1_TDRE            0x80
  64 #define UARTSR1_TC              0x40
  65 #define UARTSR1_RDRF            0x20
  66 #define UARTSR1_IDLE            0x10
  67 #define UARTSR1_OR              0x08
  68 #define UARTSR1_NF              0x04
  69 #define UARTSR1_FE              0x02
  70 #define UARTSR1_PE              0x01
  71
  72 #define UARTCR3_R8              0x80
  73 #define UARTCR3_T8              0x40
  74 #define UARTCR3_TXDIR           0x20
  75 #define UARTCR3_TXINV           0x10
  76 #define UARTCR3_ORIE            0x08
  77 #define UARTCR3_NEIE            0x04
  78 #define UARTCR3_FEIE            0x02
  79 #define UARTCR3_PEIE            0x01
  80
  81 #define UARTCR4_MAEN1           0x80
  82 #define UARTCR4_MAEN2           0x40
  83 #define UARTCR4_M10             0x20
  84 #define UARTCR4_BRFA_MASK       0x1f
  85 #define UARTCR4_BRFA_OFF        0
  86
  87 #define UARTCR5_TDMAS           0x80
  88 #define UARTCR5_RDMAS           0x20
  89
  90 #define UARTMODEM_RXRTSE        0x08
  91 #define UARTMODEM_TXRTSPOL      0x04
  92 #define UARTMODEM_TXRTSE        0x02
  93 #define UARTMODEM_TXCTSE        0x01
  94
  95 #define UARTPFIFO_TXFE          0x80
  96 #define UARTPFIFO_FIFOSIZE_MASK 0x7
  97 #define UARTPFIFO_TXSIZE_OFF    4
  98 #define UARTPFIFO_RXFE          0x08
  99 #define UARTPFIFO_RXSIZE_OFF    0
 100
 101 #define UARTCFIFO_TXFLUSH       0x80
 102 #define UARTCFIFO_RXFLUSH       0x40
 103 #define UARTCFIFO_RXOFE         0x04
 104 #define UARTCFIFO_TXOFE         0x02
 105 #define UARTCFIFO_RXUFE         0x01
 106
 107 #define UARTSFIFO_TXEMPT        0x80
 108 #define UARTSFIFO_RXEMPT        0x40
 109 #define UARTSFIFO_RXOF          0x04
 110 #define UARTSFIFO_TXOF          0x02
 111 #define UARTSFIFO_RXUF          0x01
 112
 113 /* 32-bit global registers only for i.MX7ULP/i.MX8x
 114  * Used to reset all internal logic and registers, except the Global Register.
 115  */
 116 #define UART_GLOBAL             0x8
 117
 118 /* 32-bit register definition */
 119 #define UARTBAUD                0x00
 120 #define UARTSTAT                0x04
 121 #define UARTCTRL                0x08
 122 #define UARTDATA                0x0C
 123 #define UARTMATCH               0x10
 124 #define UARTMODIR               0x14
 125 #define UARTFIFO                0x18
 126 #define UARTWATER               0x1c
 127
 128 #define UARTBAUD_MAEN1          0x80000000
 129 #define UARTBAUD_MAEN2          0x40000000
 130 #define UARTBAUD_M10            0x20000000
 131 #define UARTBAUD_TDMAE          0x00800000
 132 #define UARTBAUD_RDMAE          0x00200000
 133 #define UARTBAUD_MATCFG         0x00400000
 134 #define UARTBAUD_BOTHEDGE       0x00020000
 135 #define UARTBAUD_RESYNCDIS      0x00010000
 136 #define UARTBAUD_LBKDIE         0x00008000
 137 #define UARTBAUD_RXEDGIE        0x00004000
 138 #define UARTBAUD_SBNS           0x00002000
 139 #define UARTBAUD_SBR            0x00000000
 140 #define UARTBAUD_SBR_MASK       0x1fff
 141 #define UARTBAUD_OSR_MASK       0x1f
 142 #define UARTBAUD_OSR_SHIFT      24
 143
 144 #define UARTSTAT_LBKDIF         0x80000000
 145 #define UARTSTAT_RXEDGIF        0x40000000
 146 #define UARTSTAT_MSBF           0x20000000
 147 #define UARTSTAT_RXINV          0x10000000
 148 #define UARTSTAT_RWUID          0x08000000
 149 #define UARTSTAT_BRK13          0x04000000
 150 #define UARTSTAT_LBKDE          0x02000000
 151 #define UARTSTAT_RAF            0x01000000
 152 #define UARTSTAT_TDRE           0x00800000
 153 #define UARTSTAT_TC             0x00400000
 154 #define UARTSTAT_RDRF           0x00200000
 155 #define UARTSTAT_IDLE           0x00100000
 156 #define UARTSTAT_OR             0x00080000
 157 #define UARTSTAT_NF             0x00040000
 158 #define UARTSTAT_FE             0x00020000
 159 #define UARTSTAT_PE             0x00010000
 160 #define UARTSTAT_MA1F           0x00008000
 161 #define UARTSTAT_M21F           0x00004000
 162
 163 #define UARTCTRL_R8T9           0x80000000
 164 #define UARTCTRL_R9T8           0x40000000
 165 #define UARTCTRL_TXDIR          0x20000000
 166 #define UARTCTRL_TXINV          0x10000000
 167 #define UARTCTRL_ORIE           0x08000000
 168 #define UARTCTRL_NEIE           0x04000000
 169 #define UARTCTRL_FEIE           0x02000000
 170 #define UARTCTRL_PEIE           0x01000000
 171 #define UARTCTRL_TIE            0x00800000
 172 #define UARTCTRL_TCIE           0x00400000
 173 #define UARTCTRL_RIE            0x00200000
 174 #define UARTCTRL_ILIE           0x00100000
 175 #define UARTCTRL_TE             0x00080000
 176 #define UARTCTRL_RE             0x00040000
 177 #define UARTCTRL_RWU            0x00020000
 178 #define UARTCTRL_SBK            0x00010000
 179 #define UARTCTRL_MA1IE          0x00008000
 180 #define UARTCTRL_MA2IE          0x00004000
 181 #define UARTCTRL_IDLECFG        0x00000100
 182 #define UARTCTRL_LOOPS          0x00000080
 183 #define UARTCTRL_DOZEEN         0x00000040
 184 #define UARTCTRL_RSRC           0x00000020
 185 #define UARTCTRL_M              0x00000010
 186 #define UARTCTRL_WAKE           0x00000008
 187 #define UARTCTRL_ILT            0x00000004
 188 #define UARTCTRL_PE             0x00000002
 189 #define UARTCTRL_PT             0x00000001
 190
 191 #define UARTDATA_NOISY          0x00008000
 192 #define UARTDATA_PARITYE        0x00004000
 193 #define UARTDATA_FRETSC         0x00002000
 194 #define UARTDATA_RXEMPT         0x00001000
 195 #define UARTDATA_IDLINE         0x00000800
 196 #define UARTDATA_MASK           0x3ff
 197
 198 #define UARTMODIR_IREN          0x00020000
 199 #define UARTMODIR_TXCTSSRC      0x00000020
 200 #define UARTMODIR_TXCTSC        0x00000010
 201 #define UARTMODIR_RXRTSE        0x00000008
 202 #define UARTMODIR_TXRTSPOL      0x00000004
 203 #define UARTMODIR_TXRTSE        0x00000002
 204 #define UARTMODIR_TXCTSE        0x00000001
 205
 206 #define UARTFIFO_TXEMPT         0x00800000
 207 #define UARTFIFO_RXEMPT         0x00400000
 208 #define UARTFIFO_TXOF           0x00020000
 209 #define UARTFIFO_RXUF           0x00010000
 210 #define UARTFIFO_TXFLUSH        0x00008000
 211 #define UARTFIFO_RXFLUSH        0x00004000
 212 #define UARTFIFO_TXOFE          0x00000200
 213 #define UARTFIFO_RXUFE          0x00000100
 214 #define UARTFIFO_TXFE           0x00000080
 215 #define UARTFIFO_FIFOSIZE_MASK  0x7
 216 #define UARTFIFO_TXSIZE_OFF     4
 217 #define UARTFIFO_RXFE           0x00000008
 218 #define UARTFIFO_RXSIZE_OFF     0
 219 #define UARTFIFO_DEPTH(x)       (0x1 << ((x) ? ((x) + 1) : 0))
 220
 221 #define UARTWATER_COUNT_MASK    0xff
 222 #define UARTWATER_TXCNT_OFF     8
 223 #define UARTWATER_RXCNT_OFF     24
 224 #define UARTWATER_WATER_MASK    0xff
 225 #define UARTWATER_TXWATER_OFF   0
 226 #define UARTWATER_RXWATER_OFF   16
 227
 228 #define UART_GLOBAL_RST 0x2
 229 #define GLOBAL_RST_MIN_US       20
 230 #define GLOBAL_RST_MAX_US       40
 231
 232 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
 233 #define DMA_RX_TIMEOUT          (10)
 234
 235 #define DRIVER_NAME     "fsl-lpuart"
 236 #define DEV_NAME        "ttyLP"
 237 #define UART_NR         6
 238
 239 /* IMX lpuart has four extra unused regs located at the beginning */
 240 #define IMX_REG_OFF     0x10
 241
 242 enum lpuart_type {
 243         VF610_LPUART,
 244         LS1021A_LPUART,
 245         LS1028A_LPUART,
 246         IMX7ULP_LPUART,
 247         IMX8QXP_LPUART,
 248         IMXRT1050_LPUART,
 249 };
 250
 251 struct lpuart_port {
 252         struct uart_port        port;
 253         enum lpuart_type        devtype;
 254         struct clk              *ipg_clk;
 255         struct clk              *baud_clk;
 256         unsigned int            txfifo_size;
 257         unsigned int            rxfifo_size;
 258
 259         bool                    lpuart_dma_tx_use;
 260         bool                    lpuart_dma_rx_use;
 261         struct dma_chan         *dma_tx_chan;
 262         struct dma_chan         *dma_rx_chan;
 263         struct dma_async_tx_descriptor  *dma_tx_desc;
 264         struct dma_async_tx_descriptor  *dma_rx_desc;
 265         dma_cookie_t            dma_tx_cookie;
 266         dma_cookie_t            dma_rx_cookie;
 267         unsigned int            dma_tx_bytes;
 268         unsigned int            dma_rx_bytes;
 269         bool                    dma_tx_in_progress;
 270         unsigned int            dma_rx_timeout;
 271         struct timer_list       lpuart_timer;
 272         struct scatterlist      rx_sgl, tx_sgl[2];
 273         struct circ_buf         rx_ring;
 274         int                     rx_dma_rng_buf_len;
 275         unsigned int            dma_tx_nents;
 276         wait_queue_head_t       dma_wait;
 277 };
 278
 279 struct lpuart_soc_data {
 280         enum lpuart_type devtype;
 281         char iotype;
 282         u8 reg_off;
 283 };
 284
 285 static const struct lpuart_soc_data vf_data = {
 286         .devtype = VF610_LPUART,
 287         .iotype = UPIO_MEM,
 288 };
 289
 290 static const struct lpuart_soc_data ls1021a_data = {
 291         .devtype = LS1021A_LPUART,
 292         .iotype = UPIO_MEM32BE,
 293 };
 294
 295 static const struct lpuart_soc_data ls1028a_data = {
 296         .devtype = LS1028A_LPUART,
 297         .iotype = UPIO_MEM32,
 298 };
 299
 300 static struct lpuart_soc_data imx7ulp_data = {
 301         .devtype = IMX7ULP_LPUART,
 302         .iotype = UPIO_MEM32,
 303         .reg_off = IMX_REG_OFF,
 304 };
 305
 306 static struct lpuart_soc_data imx8qxp_data = {
 307         .devtype = IMX8QXP_LPUART,
 308         .iotype = UPIO_MEM32,
 309         .reg_off = IMX_REG_OFF,
 310 };
 311 static struct lpuart_soc_data imxrt1050_data = {
 312         .devtype = IMXRT1050_LPUART,
 313         .iotype = UPIO_MEM32,
 314         .reg_off = IMX_REG_OFF,
 315 };
 316
 317 static const struct of_device_id lpuart_dt_ids[] = {
 318         { .compatible = "fsl,vf610-lpuart",     .data = &vf_data, },
 319         { .compatible = "fsl,ls1021a-lpuart",   .data = &ls1021a_data, },
 320         { .compatible = "fsl,ls1028a-lpuart",   .data = &ls1028a_data, },
 321         { .compatible = "fsl,imx7ulp-lpuart",   .data = &imx7ulp_data, },
 322         { .compatible = "fsl,imx8qxp-lpuart",   .data = &imx8qxp_data, },
 323         { .compatible = "fsl,imxrt1050-lpuart", .data = &imxrt1050_data},
 324         { /* sentinel */ }
 325 };
 326 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
 327
 328 /* Forward declare this for the dma callbacks*/
 329 static void lpuart_dma_tx_complete(void *arg);
 330
 331 static inline bool is_layerscape_lpuart(struct lpuart_port *sport)
 332 {
 333         return (sport->devtype == LS1021A_LPUART ||
 334                 sport->devtype == LS1028A_LPUART);
 335 }
 336
 337 static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport)
 338 {
 339         return sport->devtype == IMX7ULP_LPUART;
 340 }
 341
 342 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
 343 {
 344         return sport->devtype == IMX8QXP_LPUART;
 345 }
 346
 347 static inline u32 lpuart32_read(struct uart_port *port, u32 off)
 348 {
 349         switch (port->iotype) {
 350         case UPIO_MEM32:
 351                 return readl(port->membase + off);
 352         case UPIO_MEM32BE:
 353                 return ioread32be(port->membase + off);
 354         default:
 355                 return 0;
 356         }
 357 }
 358
 359 static inline void lpuart32_write(struct uart_port *port, u32 val,
 360                                   u32 off)
 361 {
 362         switch (port->iotype) {
 363         case UPIO_MEM32:
 364                 writel(val, port->membase + off);
 365                 break;
 366         case UPIO_MEM32BE:
 367                 iowrite32be(val, port->membase + off);
 368                 break;
 369         }
 370 }
 371
 372 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en)
 373 {
 374         int ret = 0;
 375
 376         if (is_en) {
 377                 ret = clk_prepare_enable(sport->ipg_clk);
 378                 if (ret)
 379                         return ret;
 380
 381                 ret = clk_prepare_enable(sport->baud_clk);
 382                 if (ret) {
 383                         clk_disable_unprepare(sport->ipg_clk);
 384                         return ret;
 385                 }
 386         } else {
 387                 clk_disable_unprepare(sport->baud_clk);
 388                 clk_disable_unprepare(sport->ipg_clk);
 389         }
 390
 391         return 0;
 392 }
 393
 394 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
 395 {
 396         if (is_imx8qxp_lpuart(sport))
 397                 return clk_get_rate(sport->baud_clk);
 398
 399         return clk_get_rate(sport->ipg_clk);
 400 }
 401
 402 #define lpuart_enable_clks(x)   __lpuart_enable_clks(x, true)
 403 #define lpuart_disable_clks(x)  __lpuart_enable_clks(x, false)
 404
 405 static int lpuart_global_reset(struct lpuart_port *sport)
 406 {
 407         struct uart_port *port = &sport->port;
 408         void __iomem *global_addr;
 409         int ret;
 410
 411         if (uart_console(port))
 412                 return 0;
 413
 414         ret = clk_prepare_enable(sport->ipg_clk);
 415         if (ret) {
 416                 dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret);
 417                 return ret;
 418         }
 419
 420         if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
 421                 global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF;
 422                 writel(UART_GLOBAL_RST, global_addr);
 423                 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
 424                 writel(0, global_addr);
 425                 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
 426         }
 427
 428         clk_disable_unprepare(sport->ipg_clk);
 429         return 0;
 430 }
 431
 432 static void lpuart_stop_tx(struct uart_port *port)
 433 {
 434         unsigned char temp;
 435
 436         temp = readb(port->membase + UARTCR2);
 437         temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
 438         writeb(temp, port->membase + UARTCR2);
 439 }
 440
 441 static void lpuart32_stop_tx(struct uart_port *port)
 442 {
 443         unsigned long temp;
 444
 445         temp = lpuart32_read(port, UARTCTRL);
 446         temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
 447         lpuart32_write(port, temp, UARTCTRL);
 448 }
 449
 450 static void lpuart_stop_rx(struct uart_port *port)
 451 {
 452         unsigned char temp;
 453
 454         temp = readb(port->membase + UARTCR2);
 455         writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
 456 }
 457
 458 static void lpuart32_stop_rx(struct uart_port *port)
 459 {
 460         unsigned long temp;
 461
 462         temp = lpuart32_read(port, UARTCTRL);
 463         lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
 464 }
 465
 466 static void lpuart_dma_tx(struct lpuart_port *sport)
 467 {
 468         struct circ_buf *xmit = &sport->port.state->xmit;
 469         struct scatterlist *sgl = sport->tx_sgl;
 470         struct device *dev = sport->port.dev;
 471         struct dma_chan *chan = sport->dma_tx_chan;
 472         int ret;
 473
 474         if (sport->dma_tx_in_progress)
 475                 return;
 476
 477         sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
 478
 479         if (xmit->tail < xmit->head || xmit->head == 0) {
 480                 sport->dma_tx_nents = 1;
 481                 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
 482         } else {
 483                 sport->dma_tx_nents = 2;
 484                 sg_init_table(sgl, 2);
 485                 sg_set_buf(sgl, xmit->buf + xmit->tail,
 486                                 UART_XMIT_SIZE - xmit->tail);
 487                 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
 488         }
 489
 490         ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents,
 491                          DMA_TO_DEVICE);
 492         if (!ret) {
 493                 dev_err(dev, "DMA mapping error for TX.\n");
 494                 return;
 495         }
 496
 497         sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl,
 498                                         ret, DMA_MEM_TO_DEV,
 499                                         DMA_PREP_INTERRUPT);
 500         if (!sport->dma_tx_desc) {
 501                 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
 502                               DMA_TO_DEVICE);
 503                 dev_err(dev, "Cannot prepare TX slave DMA!\n");
 504                 return;
 505         }
 506
 507         sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
 508         sport->dma_tx_desc->callback_param = sport;
 509         sport->dma_tx_in_progress = true;
 510         sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
 511         dma_async_issue_pending(chan);
 512 }
 513
 514 static bool lpuart_stopped_or_empty(struct uart_port *port)
 515 {
 516         return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port);
 517 }
 518
 519 static void lpuart_dma_tx_complete(void *arg)
 520 {
 521         struct lpuart_port *sport = arg;
 522         struct scatterlist *sgl = &sport->tx_sgl[0];
 523         struct circ_buf *xmit = &sport->port.state->xmit;
 524         struct dma_chan *chan = sport->dma_tx_chan;
 525         unsigned long flags;
 526
 527         spin_lock_irqsave(&sport->port.lock, flags);
 528         if (!sport->dma_tx_in_progress) {
 529                 spin_unlock_irqrestore(&sport->port.lock, flags);
 530                 return;
 531         }
 532
 533         dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
 534                      DMA_TO_DEVICE);
 535
 536         xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
 537
 538         sport->port.icount.tx += sport->dma_tx_bytes;
 539         sport->dma_tx_in_progress = false;
 540         spin_unlock_irqrestore(&sport->port.lock, flags);
 541
 542         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 543                 uart_write_wakeup(&sport->port);
 544
 545         if (waitqueue_active(&sport->dma_wait)) {
 546                 wake_up(&sport->dma_wait);
 547                 return;
 548         }
 549
 550         spin_lock_irqsave(&sport->port.lock, flags);
 551
 552         if (!lpuart_stopped_or_empty(&sport->port))
 553                 lpuart_dma_tx(sport);
 554
 555         spin_unlock_irqrestore(&sport->port.lock, flags);
 556 }
 557
 558 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
 559 {
 560         switch (sport->port.iotype) {
 561         case UPIO_MEM32:
 562                 return sport->port.mapbase + UARTDATA;
 563         case UPIO_MEM32BE:
 564                 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
 565         }
 566         return sport->port.mapbase + UARTDR;
 567 }
 568
 569 static int lpuart_dma_tx_request(struct uart_port *port)
 570 {
 571         struct lpuart_port *sport = container_of(port,
 572                                         struct lpuart_port, port);
 573         struct dma_slave_config dma_tx_sconfig = {};
 574         int ret;
 575
 576         dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);
 577         dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 578         dma_tx_sconfig.dst_maxburst = 1;
 579         dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
 580         ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
 581
 582         if (ret) {
 583                 dev_err(sport->port.dev,
 584                                 "DMA slave config failed, err = %d\n", ret);
 585                 return ret;
 586         }
 587
 588         return 0;
 589 }
 590
 591 static bool lpuart_is_32(struct lpuart_port *sport)
 592 {
 593         return sport->port.iotype == UPIO_MEM32 ||
 594                sport->port.iotype ==  UPIO_MEM32BE;
 595 }
 596
 597 static void lpuart_flush_buffer(struct uart_port *port)
 598 {
 599         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 600         struct dma_chan *chan = sport->dma_tx_chan;
 601         u32 val;
 602
 603         if (sport->lpuart_dma_tx_use) {
 604                 if (sport->dma_tx_in_progress) {
 605                         dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0],
 606                                 sport->dma_tx_nents, DMA_TO_DEVICE);
 607                         sport->dma_tx_in_progress = false;
 608                 }
 609                 dmaengine_terminate_all(chan);
 610         }
 611
 612         if (lpuart_is_32(sport)) {
 613                 val = lpuart32_read(&sport->port, UARTFIFO);
 614                 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
 615                 lpuart32_write(&sport->port, val, UARTFIFO);
 616         } else {
 617                 val = readb(sport->port.membase + UARTCFIFO);
 618                 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
 619                 writeb(val, sport->port.membase + UARTCFIFO);
 620         }
 621 }
 622
 623 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset,
 624                                 u8 bit)
 625 {
 626         while (!(readb(port->membase + offset) & bit))
 627                 cpu_relax();
 628 }
 629
 630 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset,
 631                                   u32 bit)
 632 {
 633         while (!(lpuart32_read(port, offset) & bit))
 634                 cpu_relax();
 635 }
 636
 637 #if defined(CONFIG_CONSOLE_POLL)
 638
 639 static int lpuart_poll_init(struct uart_port *port)
 640 {
 641         struct lpuart_port *sport = container_of(port,
 642                                         struct lpuart_port, port);
 643         unsigned long flags;
 644         unsigned char temp;
 645
 646         sport->port.fifosize = 0;
 647
 648         spin_lock_irqsave(&sport->port.lock, flags);
 649         /* Disable Rx & Tx */
 650         writeb(0, sport->port.membase + UARTCR2);
 651
 652         temp = readb(sport->port.membase + UARTPFIFO);
 653         /* Enable Rx and Tx FIFO */
 654         writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
 655                         sport->port.membase + UARTPFIFO);
 656
 657         /* flush Tx and Rx FIFO */
 658         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
 659                         sport->port.membase + UARTCFIFO);
 660
 661         /* explicitly clear RDRF */
 662         if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
 663                 readb(sport->port.membase + UARTDR);
 664                 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
 665         }
 666
 667         writeb(0, sport->port.membase + UARTTWFIFO);
 668         writeb(1, sport->port.membase + UARTRWFIFO);
 669
 670         /* Enable Rx and Tx */
 671         writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
 672         spin_unlock_irqrestore(&sport->port.lock, flags);
 673
 674         return 0;
 675 }
 676
 677 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
 678 {
 679         /* drain */
 680         lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
 681         writeb(c, port->membase + UARTDR);
 682 }
 683
 684 static int lpuart_poll_get_char(struct uart_port *port)
 685 {
 686         if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
 687                 return NO_POLL_CHAR;
 688
 689         return readb(port->membase + UARTDR);
 690 }
 691
 692 static int lpuart32_poll_init(struct uart_port *port)
 693 {
 694         unsigned long flags;
 695         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 696         u32 temp;
 697
 698         sport->port.fifosize = 0;
 699
 700         spin_lock_irqsave(&sport->port.lock, flags);
 701
 702         /* Disable Rx & Tx */
 703         lpuart32_write(&sport->port, 0, UARTCTRL);
 704
 705         temp = lpuart32_read(&sport->port, UARTFIFO);
 706
 707         /* Enable Rx and Tx FIFO */
 708         lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);
 709
 710         /* flush Tx and Rx FIFO */
 711         lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO);
 712
 713         /* explicitly clear RDRF */
 714         if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
 715                 lpuart32_read(&sport->port, UARTDATA);
 716                 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO);
 717         }
 718
 719         /* Enable Rx and Tx */
 720         lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL);
 721         spin_unlock_irqrestore(&sport->port.lock, flags);
 722
 723         return 0;
 724 }
 725
 726 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
 727 {
 728         lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
 729         lpuart32_write(port, c, UARTDATA);
 730 }
 731
 732 static int lpuart32_poll_get_char(struct uart_port *port)
 733 {
 734         if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF))
 735                 return NO_POLL_CHAR;
 736
 737         return lpuart32_read(port, UARTDATA);
 738 }
 739 #endif
 740
 741 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
 742 {
 743         struct circ_buf *xmit = &sport->port.state->xmit;
 744
 745         if (sport->port.x_char) {
 746                 writeb(sport->port.x_char, sport->port.membase + UARTDR);
 747                 sport->port.icount.tx++;
 748                 sport->port.x_char = 0;
 749                 return;
 750         }
 751
 752         if (lpuart_stopped_or_empty(&sport->port)) {
 753                 lpuart_stop_tx(&sport->port);
 754                 return;
 755         }
 756
 757         while (!uart_circ_empty(xmit) &&
 758                 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
 759                 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
 760                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 761                 sport->port.icount.tx++;
 762         }
 763
 764         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 765                 uart_write_wakeup(&sport->port);
 766
 767         if (uart_circ_empty(xmit))
 768                 lpuart_stop_tx(&sport->port);
 769 }
 770
 771 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
 772 {
 773         struct circ_buf *xmit = &sport->port.state->xmit;
 774         unsigned long txcnt;
 775
 776         if (sport->port.x_char) {
 777                 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
 778                 sport->port.icount.tx++;
 779                 sport->port.x_char = 0;
 780                 return;
 781         }
 782
 783         if (lpuart_stopped_or_empty(&sport->port)) {
 784                 lpuart32_stop_tx(&sport->port);
 785                 return;
 786         }
 787
 788         txcnt = lpuart32_read(&sport->port, UARTWATER);
 789         txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 790         txcnt &= UARTWATER_COUNT_MASK;
 791         while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
 792                 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
 793                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 794                 sport->port.icount.tx++;
 795                 txcnt = lpuart32_read(&sport->port, UARTWATER);
 796                 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 797                 txcnt &= UARTWATER_COUNT_MASK;
 798         }
 799
 800         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 801                 uart_write_wakeup(&sport->port);
 802
 803         if (uart_circ_empty(xmit))
 804                 lpuart32_stop_tx(&sport->port);
 805 }
 806
 807 static void lpuart_start_tx(struct uart_port *port)
 808 {
 809         struct lpuart_port *sport = container_of(port,
 810                         struct lpuart_port, port);
 811         unsigned char temp;
 812
 813         temp = readb(port->membase + UARTCR2);
 814         writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
 815
 816         if (sport->lpuart_dma_tx_use) {
 817                 if (!lpuart_stopped_or_empty(port))
 818                         lpuart_dma_tx(sport);
 819         } else {
 820                 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
 821                         lpuart_transmit_buffer(sport);
 822         }
 823 }
 824
 825 static void lpuart32_start_tx(struct uart_port *port)
 826 {
 827         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 828         unsigned long temp;
 829
 830         if (sport->lpuart_dma_tx_use) {
 831                 if (!lpuart_stopped_or_empty(port))
 832                         lpuart_dma_tx(sport);
 833         } else {
 834                 temp = lpuart32_read(port, UARTCTRL);
 835                 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
 836
 837                 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
 838                         lpuart32_transmit_buffer(sport);
 839         }
 840 }
 841
 842 /* return TIOCSER_TEMT when transmitter is not busy */
 843 static unsigned int lpuart_tx_empty(struct uart_port *port)
 844 {
 845         struct lpuart_port *sport = container_of(port,
 846                         struct lpuart_port, port);
 847         unsigned char sr1 = readb(port->membase + UARTSR1);
 848         unsigned char sfifo = readb(port->membase + UARTSFIFO);
 849
 850         if (sport->dma_tx_in_progress)
 851                 return 0;
 852
 853         if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
 854                 return TIOCSER_TEMT;
 855
 856         return 0;
 857 }
 858
 859 static unsigned int lpuart32_tx_empty(struct uart_port *port)
 860 {
 861         struct lpuart_port *sport = container_of(port,
 862                         struct lpuart_port, port);
 863         unsigned long stat = lpuart32_read(port, UARTSTAT);
 864         unsigned long sfifo = lpuart32_read(port, UARTFIFO);
 865
 866         if (sport->dma_tx_in_progress)
 867                 return 0;
 868
 869         if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT)
 870                 return TIOCSER_TEMT;
 871
 872         return 0;
 873 }
 874
 875 static void lpuart_txint(struct lpuart_port *sport)
 876 {
 877         spin_lock(&sport->port.lock);
 878         lpuart_transmit_buffer(sport);
 879         spin_unlock(&sport->port.lock);
 880 }
 881
 882 static void lpuart_rxint(struct lpuart_port *sport)
 883 {
 884         unsigned int flg, ignored = 0, overrun = 0;
 885         struct tty_port *port = &sport->port.state->port;
 886         unsigned char rx, sr;
 887
 888         spin_lock(&sport->port.lock);
 889
 890         while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
 891                 flg = TTY_NORMAL;
 892                 sport->port.icount.rx++;
 893                 /*
 894                  * to clear the FE, OR, NF, FE, PE flags,
 895                  * read SR1 then read DR
 896                  */
 897                 sr = readb(sport->port.membase + UARTSR1);
 898                 rx = readb(sport->port.membase + UARTDR);
 899
 900                 if (uart_prepare_sysrq_char(&sport->port, rx))
 901                         continue;
 902
 903                 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
 904                         if (sr & UARTSR1_PE)
 905                                 sport->port.icount.parity++;
 906                         else if (sr & UARTSR1_FE)
 907                                 sport->port.icount.frame++;
 908
 909                         if (sr & UARTSR1_OR)
 910                                 overrun++;
 911
 912                         if (sr & sport->port.ignore_status_mask) {
 913                                 if (++ignored > 100)
 914                                         goto out;
 915                                 continue;
 916                         }
 917
 918                         sr &= sport->port.read_status_mask;
 919
 920                         if (sr & UARTSR1_PE)
 921                                 flg = TTY_PARITY;
 922                         else if (sr & UARTSR1_FE)
 923                                 flg = TTY_FRAME;
 924
 925                         if (sr & UARTSR1_OR)
 926                                 flg = TTY_OVERRUN;
 927
 928                         sport->port.sysrq = 0;
 929                 }
 930
 931                 if (tty_insert_flip_char(port, rx, flg) == 0)
 932                         sport->port.icount.buf_overrun++;
 933         }
 934
 935 out:
 936         if (overrun) {
 937                 sport->port.icount.overrun += overrun;
 938
 939                 /*
 940                  * Overruns cause FIFO pointers to become missaligned.
 941                  * Flushing the receive FIFO reinitializes the pointers.
 942                  */
 943                 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
 944                 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);
 945         }
 946
 947         uart_unlock_and_check_sysrq(&sport->port);
 948
 949         tty_flip_buffer_push(port);
 950 }
 951
 952 static void lpuart32_txint(struct lpuart_port *sport)
 953 {
 954         spin_lock(&sport->port.lock);
 955         lpuart32_transmit_buffer(sport);
 956         spin_unlock(&sport->port.lock);
 957 }
 958
 959 static void lpuart32_rxint(struct lpuart_port *sport)
 960 {
 961         unsigned int flg, ignored = 0;
 962         struct tty_port *port = &sport->port.state->port;
 963         unsigned long rx, sr;
 964         bool is_break;
 965
 966         spin_lock(&sport->port.lock);
 967
 968         while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
 969                 flg = TTY_NORMAL;
 970                 sport->port.icount.rx++;
 971                 /*
 972                  * to clear the FE, OR, NF, FE, PE flags,
 973                  * read STAT then read DATA reg
 974                  */
 975                 sr = lpuart32_read(&sport->port, UARTSTAT);
 976                 rx = lpuart32_read(&sport->port, UARTDATA);
 977                 rx &= UARTDATA_MASK;
 978
 979                 /*
 980                  * The LPUART can't distinguish between a break and a framing error,
 981                  * thus we assume it is a break if the received data is zero.
 982                  */
 983                 is_break = (sr & UARTSTAT_FE) && !rx;
 984
 985                 if (is_break && uart_handle_break(&sport->port))
 986                         continue;
 987
 988                 if (uart_prepare_sysrq_char(&sport->port, rx))
 989                         continue;
 990
 991                 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
 992                         if (sr & UARTSTAT_PE) {
 993                                 sport->port.icount.parity++;
 994                         } else if (sr & UARTSTAT_FE) {
 995                                 if (is_break)
 996                                         sport->port.icount.brk++;
 997                                 else
 998                                         sport->port.icount.frame++;
 999                         }
1000
1001                         if (sr & UARTSTAT_OR)
1002                                 sport->port.icount.overrun++;
1003
1004                         if (sr & sport->port.ignore_status_mask) {
1005                                 if (++ignored > 100)
1006                                         goto out;
1007                                 continue;
1008                         }
1009
1010                         sr &= sport->port.read_status_mask;
1011
1012                         if (sr & UARTSTAT_PE) {
1013                                 flg = TTY_PARITY;
1014                         } else if (sr & UARTSTAT_FE) {
1015                                 if (is_break)
1016                                         flg = TTY_BREAK;
1017                                 else
1018                                         flg = TTY_FRAME;
1019                         }
1020
1021                         if (sr & UARTSTAT_OR)
1022                                 flg = TTY_OVERRUN;
1023                 }
1024
1025                 if (tty_insert_flip_char(port, rx, flg) == 0)
1026                         sport->port.icount.buf_overrun++;
1027         }
1028
1029 out:
1030         uart_unlock_and_check_sysrq(&sport->port);
1031
1032         tty_flip_buffer_push(port);
1033 }
1034
1035 static irqreturn_t lpuart_int(int irq, void *dev_id)
1036 {
1037         struct lpuart_port *sport = dev_id;
1038         unsigned char sts;
1039
1040         sts = readb(sport->port.membase + UARTSR1);
1041
1042         /* SysRq, using dma, check for linebreak by framing err. */
1043         if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) {
1044                 readb(sport->port.membase + UARTDR);
1045                 uart_handle_break(&sport->port);
1046                 /* linebreak produces some garbage, removing it */
1047                 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
1048                 return IRQ_HANDLED;
1049         }
1050
1051         if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use)
1052                 lpuart_rxint(sport);
1053
1054         if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use)
1055                 lpuart_txint(sport);
1056
1057         return IRQ_HANDLED;
1058 }
1059
1060 static irqreturn_t lpuart32_int(int irq, void *dev_id)
1061 {
1062         struct lpuart_port *sport = dev_id;
1063         unsigned long sts, rxcount;
1064
1065         sts = lpuart32_read(&sport->port, UARTSTAT);
1066         rxcount = lpuart32_read(&sport->port, UARTWATER);
1067         rxcount = rxcount >> UARTWATER_RXCNT_OFF;
1068
1069         if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use)
1070                 lpuart32_rxint(sport);
1071
1072         if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
1073                 lpuart32_txint(sport);
1074
1075         lpuart32_write(&sport->port, sts, UARTSTAT);
1076         return IRQ_HANDLED;
1077 }
1078
1079
1080 static inline void lpuart_handle_sysrq_chars(struct uart_port *port,
1081                                              unsigned char *p, int count)
1082 {
1083         while (count--) {
1084                 if (*p && uart_handle_sysrq_char(port, *p))
1085                         return;
1086                 p++;
1087         }
1088 }
1089
1090 static void lpuart_handle_sysrq(struct lpuart_port *sport)
1091 {
1092         struct circ_buf *ring = &sport->rx_ring;
1093         int count;
1094
1095         if (ring->head < ring->tail) {
1096                 count = sport->rx_sgl.length - ring->tail;
1097                 lpuart_handle_sysrq_chars(&sport->port,
1098                                           ring->buf + ring->tail, count);
1099                 ring->tail = 0;
1100         }
1101
1102         if (ring->head > ring->tail) {
1103                 count = ring->head - ring->tail;
1104                 lpuart_handle_sysrq_chars(&sport->port,
1105                                           ring->buf + ring->tail, count);
1106                 ring->tail = ring->head;
1107         }
1108 }
1109
1110 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
1111 {
1112         struct tty_port *port = &sport->port.state->port;
1113         struct dma_tx_state state;
1114         enum dma_status dmastat;
1115         struct dma_chan *chan = sport->dma_rx_chan;
1116         struct circ_buf *ring = &sport->rx_ring;
1117         unsigned long flags;
1118         int count, copied;
1119
1120         if (lpuart_is_32(sport)) {
1121                 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
1122
1123                 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) {
1124                         /* Read DR to clear the error flags */
1125                         lpuart32_read(&sport->port, UARTDATA);
1126
1127                         if (sr & UARTSTAT_PE)
1128                                 sport->port.icount.parity++;
1129                         else if (sr & UARTSTAT_FE)
1130                                 sport->port.icount.frame++;
1131                 }
1132         } else {
1133                 unsigned char sr = readb(sport->port.membase + UARTSR1);
1134
1135                 if (sr & (UARTSR1_PE | UARTSR1_FE)) {
1136                         unsigned char cr2;
1137
1138                         /* Disable receiver during this operation... */
1139                         cr2 = readb(sport->port.membase + UARTCR2);
1140                         cr2 &= ~UARTCR2_RE;
1141                         writeb(cr2, sport->port.membase + UARTCR2);
1142
1143                         /* Read DR to clear the error flags */
1144                         readb(sport->port.membase + UARTDR);
1145
1146                         if (sr & UARTSR1_PE)
1147                                 sport->port.icount.parity++;
1148                         else if (sr & UARTSR1_FE)
1149                                 sport->port.icount.frame++;
1150                         /*
1151                          * At this point parity/framing error is
1152                          * cleared However, since the DMA already read
1153                          * the data register and we had to read it
1154                          * again after reading the status register to
1155                          * properly clear the flags, the FIFO actually
1156                          * underflowed... This requires a clearing of
1157                          * the FIFO...
1158                          */
1159                         if (readb(sport->port.membase + UARTSFIFO) &
1160                             UARTSFIFO_RXUF) {
1161                                 writeb(UARTSFIFO_RXUF,
1162                                        sport->port.membase + UARTSFIFO);
1163                                 writeb(UARTCFIFO_RXFLUSH,
1164                                        sport->port.membase + UARTCFIFO);
1165                         }
1166
1167                         cr2 |= UARTCR2_RE;
1168                         writeb(cr2, sport->port.membase + UARTCR2);
1169                 }
1170         }
1171
1172         async_tx_ack(sport->dma_rx_desc);
1173
1174         spin_lock_irqsave(&sport->port.lock, flags);
1175
1176         dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
1177         if (dmastat == DMA_ERROR) {
1178                 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1179                 spin_unlock_irqrestore(&sport->port.lock, flags);
1180                 return;
1181         }
1182
1183         /* CPU claims ownership of RX DMA buffer */
1184         dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1,
1185                             DMA_FROM_DEVICE);
1186
1187         /*
1188          * ring->head points to the end of data already written by the DMA.
1189          * ring->tail points to the beginning of data to be read by the
1190          * framework.
1191          * The current transfer size should not be larger than the dma buffer
1192          * length.
1193          */
1194         ring->head = sport->rx_sgl.length - state.residue;
1195         BUG_ON(ring->head > sport->rx_sgl.length);
1196
1197         /*
1198          * Silent handling of keys pressed in the sysrq timeframe
1199          */
1200         if (sport->port.sysrq) {
1201                 lpuart_handle_sysrq(sport);
1202                 goto exit;
1203         }
1204
1205         /*
1206          * At this point ring->head may point to the first byte right after the
1207          * last byte of the dma buffer:
1208          * 0 <= ring->head <= sport->rx_sgl.length
1209          *
1210          * However ring->tail must always points inside the dma buffer:
1211          * 0 <= ring->tail <= sport->rx_sgl.length - 1
1212          *
1213          * Since we use a ring buffer, we have to handle the case
1214          * where head is lower than tail. In such a case, we first read from
1215          * tail to the end of the buffer then reset tail.
1216          */
1217         if (ring->head < ring->tail) {
1218                 count = sport->rx_sgl.length - ring->tail;
1219
1220                 copied = tty_insert_flip_string(port, ring->buf + ring->tail, count);
1221                 if (copied != count)
1222                         sport->port.icount.buf_overrun++;
1223                 ring->tail = 0;
1224                 sport->port.icount.rx += copied;
1225         }
1226
1227         /* Finally we read data from tail to head */
1228         if (ring->tail < ring->head) {
1229                 count = ring->head - ring->tail;
1230                 copied = tty_insert_flip_string(port, ring->buf + ring->tail, count);
1231                 if (copied != count)
1232                         sport->port.icount.buf_overrun++;
1233                 /* Wrap ring->head if needed */
1234                 if (ring->head >= sport->rx_sgl.length)
1235                         ring->head = 0;
1236                 ring->tail = ring->head;
1237                 sport->port.icount.rx += copied;
1238         }
1239
1240 exit:
1241         dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1,
1242                                DMA_FROM_DEVICE);
1243
1244         spin_unlock_irqrestore(&sport->port.lock, flags);
1245
1246         tty_flip_buffer_push(port);
1247         mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
1248 }
1249
1250 static void lpuart_dma_rx_complete(void *arg)
1251 {
1252         struct lpuart_port *sport = arg;
1253
1254         lpuart_copy_rx_to_tty(sport);
1255 }
1256
1257 static void lpuart_timer_func(struct timer_list *t)
1258 {
1259         struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);
1260
1261         lpuart_copy_rx_to_tty(sport);
1262 }
1263
1264 static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
1265 {
1266         struct dma_slave_config dma_rx_sconfig = {};
1267         struct circ_buf *ring = &sport->rx_ring;
1268         int ret, nent;
1269         int bits, baud;
1270         struct tty_port *port = &sport->port.state->port;
1271         struct tty_struct *tty = port->tty;
1272         struct ktermios *termios = &tty->termios;
1273         struct dma_chan *chan = sport->dma_rx_chan;
1274
1275         baud = tty_get_baud_rate(tty);
1276
1277         bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10;
1278         if (termios->c_cflag & PARENB)
1279                 bits++;
1280
1281         /*
1282          * Calculate length of one DMA buffer size to keep latency below
1283          * 10ms at any baud rate.
1284          */
1285         sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud /  bits / 1000) * 2;
1286         sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
1287         if (sport->rx_dma_rng_buf_len < 16)
1288                 sport->rx_dma_rng_buf_len = 16;
1289
1290         ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1291         if (!ring->buf)
1292                 return -ENOMEM;
1293
1294         sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1295         nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1,
1296                           DMA_FROM_DEVICE);
1297
1298         if (!nent) {
1299                 dev_err(sport->port.dev, "DMA Rx mapping error\n");
1300                 return -EINVAL;
1301         }
1302
1303         dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);
1304         dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1305         dma_rx_sconfig.src_maxburst = 1;
1306         dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1307         ret = dmaengine_slave_config(chan, &dma_rx_sconfig);
1308
1309         if (ret < 0) {
1310                 dev_err(sport->port.dev,
1311                                 "DMA Rx slave config failed, err = %d\n", ret);
1312                 return ret;
1313         }
1314
1315         sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan,
1316                                  sg_dma_address(&sport->rx_sgl),
1317                                  sport->rx_sgl.length,
1318                                  sport->rx_sgl.length / 2,
1319                                  DMA_DEV_TO_MEM,
1320                                  DMA_PREP_INTERRUPT);
1321         if (!sport->dma_rx_desc) {
1322                 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1323                 return -EFAULT;
1324         }
1325
1326         sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1327         sport->dma_rx_desc->callback_param = sport;
1328         sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1329         dma_async_issue_pending(chan);
1330
1331         if (lpuart_is_32(sport)) {
1332                 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
1333
1334                 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
1335         } else {
1336                 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1337                        sport->port.membase + UARTCR5);
1338         }
1339
1340         return 0;
1341 }
1342
1343 static void lpuart_dma_rx_free(struct uart_port *port)
1344 {
1345         struct lpuart_port *sport = container_of(port,
1346                                         struct lpuart_port, port);
1347         struct dma_chan *chan = sport->dma_rx_chan;
1348
1349         dmaengine_terminate_all(chan);
1350         dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1351         kfree(sport->rx_ring.buf);
1352         sport->rx_ring.tail = 0;
1353         sport->rx_ring.head = 0;
1354         sport->dma_rx_desc = NULL;
1355         sport->dma_rx_cookie = -EINVAL;
1356 }
1357
1358 static int lpuart_config_rs485(struct uart_port *port,
1359                         struct serial_rs485 *rs485)
1360 {
1361         struct lpuart_port *sport = container_of(port,
1362                         struct lpuart_port, port);
1363
1364         u8 modem = readb(sport->port.membase + UARTMODEM) &
1365                 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1366         writeb(modem, sport->port.membase + UARTMODEM);
1367
1368         /* clear unsupported configurations */
1369         rs485->delay_rts_before_send = 0;
1370         rs485->delay_rts_after_send = 0;
1371         rs485->flags &= ~SER_RS485_RX_DURING_TX;
1372
1373         if (rs485->flags & SER_RS485_ENABLED) {
1374                 /* Enable auto RS-485 RTS mode */
1375                 modem |= UARTMODEM_TXRTSE;
1376
1377                 /*
1378                  * The hardware defaults to RTS logic HIGH while transfer.
1379                  * Switch polarity in case RTS shall be logic HIGH
1380                  * after transfer.
1381                  * Note: UART is assumed to be active high.
1382                  */
1383                 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1384                         modem |= UARTMODEM_TXRTSPOL;
1385                 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1386                         modem &= ~UARTMODEM_TXRTSPOL;
1387         }
1388
1389         writeb(modem, sport->port.membase + UARTMODEM);
1390         return 0;
1391 }
1392
1393 static int lpuart32_config_rs485(struct uart_port *port,
1394                         struct serial_rs485 *rs485)
1395 {
1396         struct lpuart_port *sport = container_of(port,
1397                         struct lpuart_port, port);
1398
1399         unsigned long modem = lpuart32_read(&sport->port, UARTMODIR)
1400                                 & ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1401         lpuart32_write(&sport->port, modem, UARTMODIR);
1402
1403         /* clear unsupported configurations */
1404         rs485->delay_rts_before_send = 0;
1405         rs485->delay_rts_after_send = 0;
1406         rs485->flags &= ~SER_RS485_RX_DURING_TX;
1407
1408         if (rs485->flags & SER_RS485_ENABLED) {
1409                 /* Enable auto RS-485 RTS mode */
1410                 modem |= UARTMODEM_TXRTSE;
1411
1412                 /*
1413                  * The hardware defaults to RTS logic HIGH while transfer.
1414                  * Switch polarity in case RTS shall be logic HIGH
1415                  * after transfer.
1416                  * Note: UART is assumed to be active high.
1417                  */
1418                 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1419                         modem &= ~UARTMODEM_TXRTSPOL;
1420                 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1421                         modem |= UARTMODEM_TXRTSPOL;
1422         }
1423
1424         lpuart32_write(&sport->port, modem, UARTMODIR);
1425         return 0;
1426 }
1427
1428 static unsigned int lpuart_get_mctrl(struct uart_port *port)
1429 {
1430         unsigned int mctrl = 0;
1431         u8 reg;
1432
1433         reg = readb(port->membase + UARTCR1);
1434         if (reg & UARTCR1_LOOPS)
1435                 mctrl |= TIOCM_LOOP;
1436
1437         return mctrl;
1438 }
1439
1440 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1441 {
1442         unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
1443         u32 reg;
1444
1445         reg = lpuart32_read(port, UARTCTRL);
1446         if (reg & UARTCTRL_LOOPS)
1447                 mctrl |= TIOCM_LOOP;
1448
1449         return mctrl;
1450 }
1451
1452 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1453 {
1454         u8 reg;
1455
1456         reg = readb(port->membase + UARTCR1);
1457
1458         /* for internal loopback we need LOOPS=1 and RSRC=0 */
1459         reg &= ~(UARTCR1_LOOPS | UARTCR1_RSRC);
1460         if (mctrl & TIOCM_LOOP)
1461                 reg |= UARTCR1_LOOPS;
1462
1463         writeb(reg, port->membase + UARTCR1);
1464 }
1465
1466 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1467 {
1468         u32 reg;
1469
1470         reg = lpuart32_read(port, UARTCTRL);
1471
1472         /* for internal loopback we need LOOPS=1 and RSRC=0 */
1473         reg &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC);
1474         if (mctrl & TIOCM_LOOP)
1475                 reg |= UARTCTRL_LOOPS;
1476
1477         lpuart32_write(port, reg, UARTCTRL);
1478 }
1479
1480 static void lpuart_break_ctl(struct uart_port *port, int break_state)
1481 {
1482         unsigned char temp;
1483
1484         temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1485
1486         if (break_state != 0)
1487                 temp |= UARTCR2_SBK;
1488
1489         writeb(temp, port->membase + UARTCR2);
1490 }
1491
1492 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1493 {
1494         unsigned long temp;
1495
1496         temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK;
1497
1498         if (break_state != 0)
1499                 temp |= UARTCTRL_SBK;
1500
1501         lpuart32_write(port, temp, UARTCTRL);
1502 }
1503
1504 static void lpuart_setup_watermark(struct lpuart_port *sport)
1505 {
1506         unsigned char val, cr2;
1507         unsigned char cr2_saved;
1508
1509         cr2 = readb(sport->port.membase + UARTCR2);
1510         cr2_saved = cr2;
1511         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1512                         UARTCR2_RIE | UARTCR2_RE);
1513         writeb(cr2, sport->port.membase + UARTCR2);
1514
1515         val = readb(sport->port.membase + UARTPFIFO);
1516         writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1517                         sport->port.membase + UARTPFIFO);
1518
1519         /* flush Tx and Rx FIFO */
1520         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1521                         sport->port.membase + UARTCFIFO);
1522
1523         /* explicitly clear RDRF */
1524         if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1525                 readb(sport->port.membase + UARTDR);
1526                 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1527         }
1528
1529         writeb(0, sport->port.membase + UARTTWFIFO);
1530         writeb(1, sport->port.membase + UARTRWFIFO);
1531
1532         /* Restore cr2 */
1533         writeb(cr2_saved, sport->port.membase + UARTCR2);
1534 }
1535
1536 static void lpuart_setup_watermark_enable(struct lpuart_port *sport)
1537 {
1538         unsigned char cr2;
1539
1540         lpuart_setup_watermark(sport);
1541
1542         cr2 = readb(sport->port.membase + UARTCR2);
1543         cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE;
1544         writeb(cr2, sport->port.membase + UARTCR2);
1545 }
1546
1547 static void lpuart32_setup_watermark(struct lpuart_port *sport)
1548 {
1549         unsigned long val, ctrl;
1550         unsigned long ctrl_saved;
1551
1552         ctrl = lpuart32_read(&sport->port, UARTCTRL);
1553         ctrl_saved = ctrl;
1554         ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1555                         UARTCTRL_RIE | UARTCTRL_RE);
1556         lpuart32_write(&sport->port, ctrl, UARTCTRL);
1557
1558         /* enable FIFO mode */
1559         val = lpuart32_read(&sport->port, UARTFIFO);
1560         val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1561         val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1562         lpuart32_write(&sport->port, val, UARTFIFO);
1563
1564         /* set the watermark */
1565         val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
1566         lpuart32_write(&sport->port, val, UARTWATER);
1567
1568         /* Restore cr2 */
1569         lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1570 }
1571
1572 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
1573 {
1574         u32 temp;
1575
1576         lpuart32_setup_watermark(sport);
1577
1578         temp = lpuart32_read(&sport->port, UARTCTRL);
1579         temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE;
1580         lpuart32_write(&sport->port, temp, UARTCTRL);
1581 }
1582
1583 static void rx_dma_timer_init(struct lpuart_port *sport)
1584 {
1585         timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
1586         sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1587         add_timer(&sport->lpuart_timer);
1588 }
1589
1590 static void lpuart_request_dma(struct lpuart_port *sport)
1591 {
1592         sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx");
1593         if (IS_ERR(sport->dma_tx_chan)) {
1594                 dev_dbg_once(sport->port.dev,
1595                              "DMA tx channel request failed, operating without tx DMA (%ld)\n",
1596                              PTR_ERR(sport->dma_tx_chan));
1597                 sport->dma_tx_chan = NULL;
1598         }
1599
1600         sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx");
1601         if (IS_ERR(sport->dma_rx_chan)) {
1602                 dev_dbg_once(sport->port.dev,
1603                              "DMA rx channel request failed, operating without rx DMA (%ld)\n",
1604                              PTR_ERR(sport->dma_rx_chan));
1605                 sport->dma_rx_chan = NULL;
1606         }
1607 }
1608
1609 static void lpuart_tx_dma_startup(struct lpuart_port *sport)
1610 {
1611         u32 uartbaud;
1612         int ret;
1613
1614         if (uart_console(&sport->port))
1615                 goto err;
1616
1617         if (!sport->dma_tx_chan)
1618                 goto err;
1619
1620         ret = lpuart_dma_tx_request(&sport->port);
1621         if (ret)
1622                 goto err;
1623
1624         init_waitqueue_head(&sport->dma_wait);
1625         sport->lpuart_dma_tx_use = true;
1626         if (lpuart_is_32(sport)) {
1627                 uartbaud = lpuart32_read(&sport->port, UARTBAUD);
1628                 lpuart32_write(&sport->port,
1629                                uartbaud | UARTBAUD_TDMAE, UARTBAUD);
1630         } else {
1631                 writeb(readb(sport->port.membase + UARTCR5) |
1632                        UARTCR5_TDMAS, sport->port.membase + UARTCR5);
1633         }
1634
1635         return;
1636
1637 err:
1638         sport->lpuart_dma_tx_use = false;
1639 }
1640
1641 static void lpuart_rx_dma_startup(struct lpuart_port *sport)
1642 {
1643         int ret;
1644         unsigned char cr3;
1645
1646         if (uart_console(&sport->port))
1647                 goto err;
1648
1649         if (!sport->dma_rx_chan)
1650                 goto err;
1651
1652         ret = lpuart_start_rx_dma(sport);
1653         if (ret)
1654                 goto err;
1655
1656         /* set Rx DMA timeout */
1657         sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1658         if (!sport->dma_rx_timeout)
1659                 sport->dma_rx_timeout = 1;
1660
1661         sport->lpuart_dma_rx_use = true;
1662         rx_dma_timer_init(sport);
1663
1664         if (sport->port.has_sysrq && !lpuart_is_32(sport)) {
1665                 cr3 = readb(sport->port.membase + UARTCR3);
1666                 cr3 |= UARTCR3_FEIE;
1667                 writeb(cr3, sport->port.membase + UARTCR3);
1668         }
1669
1670         return;
1671
1672 err:
1673         sport->lpuart_dma_rx_use = false;
1674 }
1675
1676 static int lpuart_startup(struct uart_port *port)
1677 {
1678         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1679         unsigned long flags;
1680         unsigned char temp;
1681
1682         /* determine FIFO size and enable FIFO mode */
1683         temp = readb(sport->port.membase + UARTPFIFO);
1684
1685         sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
1686                                             UARTPFIFO_FIFOSIZE_MASK);
1687         sport->port.fifosize = sport->txfifo_size;
1688
1689         sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
1690                                             UARTPFIFO_FIFOSIZE_MASK);
1691
1692         lpuart_request_dma(sport);
1693
1694         spin_lock_irqsave(&sport->port.lock, flags);
1695
1696         lpuart_setup_watermark_enable(sport);
1697
1698         lpuart_rx_dma_startup(sport);
1699         lpuart_tx_dma_startup(sport);
1700
1701         spin_unlock_irqrestore(&sport->port.lock, flags);
1702
1703         return 0;
1704 }
1705
1706 static void lpuart32_configure(struct lpuart_port *sport)
1707 {
1708         unsigned long temp;
1709
1710         if (sport->lpuart_dma_rx_use) {
1711                 /* RXWATER must be 0 */
1712                 temp = lpuart32_read(&sport->port, UARTWATER);
1713                 temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF);
1714                 lpuart32_write(&sport->port, temp, UARTWATER);
1715         }
1716         temp = lpuart32_read(&sport->port, UARTCTRL);
1717         if (!sport->lpuart_dma_rx_use)
1718                 temp |= UARTCTRL_RIE;
1719         if (!sport->lpuart_dma_tx_use)
1720                 temp |= UARTCTRL_TIE;
1721         lpuart32_write(&sport->port, temp, UARTCTRL);
1722 }
1723
1724 static int lpuart32_startup(struct uart_port *port)
1725 {
1726         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1727         unsigned long flags;
1728         unsigned long temp;
1729
1730         /* determine FIFO size */
1731         temp = lpuart32_read(&sport->port, UARTFIFO);
1732
1733         sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
1734                                             UARTFIFO_FIFOSIZE_MASK);
1735         sport->port.fifosize = sport->txfifo_size;
1736
1737         sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
1738                                             UARTFIFO_FIFOSIZE_MASK);
1739
1740         /*
1741          * The LS1021A and LS1028A have a fixed FIFO depth of 16 words.
1742          * Although they support the RX/TXSIZE fields, their encoding is
1743          * different. Eg the reference manual states 0b101 is 16 words.
1744          */
1745         if (is_layerscape_lpuart(sport)) {
1746                 sport->rxfifo_size = 16;
1747                 sport->txfifo_size = 16;
1748                 sport->port.fifosize = sport->txfifo_size;
1749         }
1750
1751         lpuart_request_dma(sport);
1752
1753         spin_lock_irqsave(&sport->port.lock, flags);
1754
1755         lpuart32_setup_watermark_enable(sport);
1756
1757         lpuart_rx_dma_startup(sport);
1758         lpuart_tx_dma_startup(sport);
1759
1760         lpuart32_configure(sport);
1761
1762         spin_unlock_irqrestore(&sport->port.lock, flags);
1763         return 0;
1764 }
1765
1766 static void lpuart_dma_shutdown(struct lpuart_port *sport)
1767 {
1768         if (sport->lpuart_dma_rx_use) {
1769                 del_timer_sync(&sport->lpuart_timer);
1770                 lpuart_dma_rx_free(&sport->port);
1771         }
1772
1773         if (sport->lpuart_dma_tx_use) {
1774                 if (wait_event_interruptible_timeout(sport->dma_wait,
1775                         !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) {
1776                         sport->dma_tx_in_progress = false;
1777                         dmaengine_terminate_all(sport->dma_tx_chan);
1778                 }
1779         }
1780
1781         if (sport->dma_tx_chan)
1782                 dma_release_channel(sport->dma_tx_chan);
1783         if (sport->dma_rx_chan)
1784                 dma_release_channel(sport->dma_rx_chan);
1785 }
1786
1787 static void lpuart_shutdown(struct uart_port *port)
1788 {
1789         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1790         unsigned char temp;
1791         unsigned long flags;
1792
1793         spin_lock_irqsave(&port->lock, flags);
1794
1795         /* disable Rx/Tx and interrupts */
1796         temp = readb(port->membase + UARTCR2);
1797         temp &= ~(UARTCR2_TE | UARTCR2_RE |
1798                         UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1799         writeb(temp, port->membase + UARTCR2);
1800
1801         spin_unlock_irqrestore(&port->lock, flags);
1802
1803         lpuart_dma_shutdown(sport);
1804 }
1805
1806 static void lpuart32_shutdown(struct uart_port *port)
1807 {
1808         struct lpuart_port *sport =
1809                 container_of(port, struct lpuart_port, port);
1810         unsigned long temp;
1811         unsigned long flags;
1812
1813         spin_lock_irqsave(&port->lock, flags);
1814
1815         /* disable Rx/Tx and interrupts */
1816         temp = lpuart32_read(port, UARTCTRL);
1817         temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1818                         UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1819         lpuart32_write(port, temp, UARTCTRL);
1820
1821         spin_unlock_irqrestore(&port->lock, flags);
1822
1823         lpuart_dma_shutdown(sport);
1824 }
1825
1826 static void
1827 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1828                    struct ktermios *old)
1829 {
1830         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1831         unsigned long flags;
1832         unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
1833         unsigned int  baud;
1834         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1835         unsigned int sbr, brfa;
1836
1837         cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1838         old_cr2 = readb(sport->port.membase + UARTCR2);
1839         cr3 = readb(sport->port.membase + UARTCR3);
1840         cr4 = readb(sport->port.membase + UARTCR4);
1841         bdh = readb(sport->port.membase + UARTBDH);
1842         modem = readb(sport->port.membase + UARTMODEM);
1843         /*
1844          * only support CS8 and CS7, and for CS7 must enable PE.
1845          * supported mode:
1846          *  - (7,e/o,1)
1847          *  - (8,n,1)
1848          *  - (8,m/s,1)
1849          *  - (8,e/o,1)
1850          */
1851         while ((termios->c_cflag & CSIZE) != CS8 &&
1852                 (termios->c_cflag & CSIZE) != CS7) {
1853                 termios->c_cflag &= ~CSIZE;
1854                 termios->c_cflag |= old_csize;
1855                 old_csize = CS8;
1856         }
1857
1858         if ((termios->c_cflag & CSIZE) == CS8 ||
1859                 (termios->c_cflag & CSIZE) == CS7)
1860                 cr1 = old_cr1 & ~UARTCR1_M;
1861
1862         if (termios->c_cflag & CMSPAR) {
1863                 if ((termios->c_cflag & CSIZE) != CS8) {
1864                         termios->c_cflag &= ~CSIZE;
1865                         termios->c_cflag |= CS8;
1866                 }
1867                 cr1 |= UARTCR1_M;
1868         }
1869
1870         /*
1871          * When auto RS-485 RTS mode is enabled,
1872          * hardware flow control need to be disabled.
1873          */
1874         if (sport->port.rs485.flags & SER_RS485_ENABLED)
1875                 termios->c_cflag &= ~CRTSCTS;
1876
1877         if (termios->c_cflag & CRTSCTS)
1878                 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE;
1879         else
1880                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1881
1882         termios->c_cflag &= ~CSTOPB;
1883
1884         /* parity must be enabled when CS7 to match 8-bits format */
1885         if ((termios->c_cflag & CSIZE) == CS7)
1886                 termios->c_cflag |= PARENB;
1887
1888         if (termios->c_cflag & PARENB) {
1889                 if (termios->c_cflag & CMSPAR) {
1890                         cr1 &= ~UARTCR1_PE;
1891                         if (termios->c_cflag & PARODD)
1892                                 cr3 |= UARTCR3_T8;
1893                         else
1894                                 cr3 &= ~UARTCR3_T8;
1895                 } else {
1896                         cr1 |= UARTCR1_PE;
1897                         if ((termios->c_cflag & CSIZE) == CS8)
1898                                 cr1 |= UARTCR1_M;
1899                         if (termios->c_cflag & PARODD)
1900                                 cr1 |= UARTCR1_PT;
1901                         else
1902                                 cr1 &= ~UARTCR1_PT;
1903                 }
1904         } else {
1905                 cr1 &= ~UARTCR1_PE;
1906         }
1907
1908         /* ask the core to calculate the divisor */
1909         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1910
1911         /*
1912          * Need to update the Ring buffer length according to the selected
1913          * baud rate and restart Rx DMA path.
1914          *
1915          * Since timer function acqures sport->port.lock, need to stop before
1916          * acquring same lock because otherwise del_timer_sync() can deadlock.
1917          */
1918         if (old && sport->lpuart_dma_rx_use) {
1919                 del_timer_sync(&sport->lpuart_timer);
1920                 lpuart_dma_rx_free(&sport->port);
1921         }
1922
1923         spin_lock_irqsave(&sport->port.lock, flags);
1924
1925         sport->port.read_status_mask = 0;
1926         if (termios->c_iflag & INPCK)
1927                 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE;
1928         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1929                 sport->port.read_status_mask |= UARTSR1_FE;
1930
1931         /* characters to ignore */
1932         sport->port.ignore_status_mask = 0;
1933         if (termios->c_iflag & IGNPAR)
1934                 sport->port.ignore_status_mask |= UARTSR1_PE;
1935         if (termios->c_iflag & IGNBRK) {
1936                 sport->port.ignore_status_mask |= UARTSR1_FE;
1937                 /*
1938                  * if we're ignoring parity and break indicators,
1939                  * ignore overruns too (for real raw support).
1940                  */
1941                 if (termios->c_iflag & IGNPAR)
1942                         sport->port.ignore_status_mask |= UARTSR1_OR;
1943         }
1944
1945         /* update the per-port timeout */
1946         uart_update_timeout(port, termios->c_cflag, baud);
1947
1948         /* wait transmit engin complete */
1949         lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
1950
1951         /* disable transmit and receive */
1952         writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1953                         sport->port.membase + UARTCR2);
1954
1955         sbr = sport->port.uartclk / (16 * baud);
1956         brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1957         bdh &= ~UARTBDH_SBR_MASK;
1958         bdh |= (sbr >> 8) & 0x1F;
1959         cr4 &= ~UARTCR4_BRFA_MASK;
1960         brfa &= UARTCR4_BRFA_MASK;
1961         writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1962         writeb(bdh, sport->port.membase + UARTBDH);
1963         writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1964         writeb(cr3, sport->port.membase + UARTCR3);
1965         writeb(cr1, sport->port.membase + UARTCR1);
1966         writeb(modem, sport->port.membase + UARTMODEM);
1967
1968         /* restore control register */
1969         writeb(old_cr2, sport->port.membase + UARTCR2);
1970
1971         if (old && sport->lpuart_dma_rx_use) {
1972                 if (!lpuart_start_rx_dma(sport))
1973                         rx_dma_timer_init(sport);
1974                 else
1975                         sport->lpuart_dma_rx_use = false;
1976         }
1977
1978         spin_unlock_irqrestore(&sport->port.lock, flags);
1979 }
1980
1981 static void __lpuart32_serial_setbrg(struct uart_port *port,
1982                                      unsigned int baudrate, bool use_rx_dma,
1983                                      bool use_tx_dma)
1984 {
1985         u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
1986         u32 clk = port->uartclk;
1987
1988         /*
1989          * The idea is to use the best OSR (over-sampling rate) possible.
1990          * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
1991          * Loop to find the best OSR value possible, one that generates minimum
1992          * baud_diff iterate through the rest of the supported values of OSR.
1993          *
1994          * Calculation Formula:
1995          *  Baud Rate = baud clock / ((OSR+1) × SBR)
1996          */
1997         baud_diff = baudrate;
1998         osr = 0;
1999         sbr = 0;
2000
2001         for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
2002                 /* calculate the temporary sbr value  */
2003                 tmp_sbr = (clk / (baudrate * tmp_osr));
2004                 if (tmp_sbr == 0)
2005                         tmp_sbr = 1;
2006
2007                 /*
2008                  * calculate the baud rate difference based on the temporary
2009                  * osr and sbr values
2010                  */
2011                 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
2012
2013                 /* select best values between sbr and sbr+1 */
2014                 tmp = clk / (tmp_osr * (tmp_sbr + 1));
2015                 if (tmp_diff > (baudrate - tmp)) {
2016                         tmp_diff = baudrate - tmp;
2017                         tmp_sbr++;
2018                 }
2019
2020                 if (tmp_sbr > UARTBAUD_SBR_MASK)
2021                         continue;
2022
2023                 if (tmp_diff <= baud_diff) {
2024                         baud_diff = tmp_diff;
2025                         osr = tmp_osr;
2026                         sbr = tmp_sbr;
2027
2028                         if (!baud_diff)
2029                                 break;
2030                 }
2031         }
2032
2033         /* handle buadrate outside acceptable rate */
2034         if (baud_diff > ((baudrate / 100) * 3))
2035                 dev_warn(port->dev,
2036                          "unacceptable baud rate difference of more than 3%%\n");
2037
2038         tmp = lpuart32_read(port, UARTBAUD);
2039
2040         if ((osr > 3) && (osr < 8))
2041                 tmp |= UARTBAUD_BOTHEDGE;
2042
2043         tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
2044         tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;
2045
2046         tmp &= ~UARTBAUD_SBR_MASK;
2047         tmp |= sbr & UARTBAUD_SBR_MASK;
2048
2049         if (!use_rx_dma)
2050                 tmp &= ~UARTBAUD_RDMAE;
2051         if (!use_tx_dma)
2052                 tmp &= ~UARTBAUD_TDMAE;
2053
2054         lpuart32_write(port, tmp, UARTBAUD);
2055 }
2056
2057 static void lpuart32_serial_setbrg(struct lpuart_port *sport,
2058                                    unsigned int baudrate)
2059 {
2060         __lpuart32_serial_setbrg(&sport->port, baudrate,
2061                                  sport->lpuart_dma_rx_use,
2062                                  sport->lpuart_dma_tx_use);
2063 }
2064
2065
2066 static void
2067 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
2068                    struct ktermios *old)
2069 {
2070         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
2071         unsigned long flags;
2072         unsigned long ctrl, old_ctrl, bd, modem;
2073         unsigned int  baud;
2074         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
2075
2076         ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
2077         bd = lpuart32_read(&sport->port, UARTBAUD);
2078         modem = lpuart32_read(&sport->port, UARTMODIR);
2079         /*
2080          * only support CS8 and CS7, and for CS7 must enable PE.
2081          * supported mode:
2082          *  - (7,e/o,1)
2083          *  - (8,n,1)
2084          *  - (8,m/s,1)
2085          *  - (8,e/o,1)
2086          */
2087         while ((termios->c_cflag & CSIZE) != CS8 &&
2088                 (termios->c_cflag & CSIZE) != CS7) {
2089                 termios->c_cflag &= ~CSIZE;
2090                 termios->c_cflag |= old_csize;
2091                 old_csize = CS8;
2092         }
2093
2094         if ((termios->c_cflag & CSIZE) == CS8 ||
2095                 (termios->c_cflag & CSIZE) == CS7)
2096                 ctrl = old_ctrl & ~UARTCTRL_M;
2097
2098         if (termios->c_cflag & CMSPAR) {
2099                 if ((termios->c_cflag & CSIZE) != CS8) {
2100                         termios->c_cflag &= ~CSIZE;
2101                         termios->c_cflag |= CS8;
2102                 }
2103                 ctrl |= UARTCTRL_M;
2104         }
2105
2106         /*
2107          * When auto RS-485 RTS mode is enabled,
2108          * hardware flow control need to be disabled.
2109          */
2110         if (sport->port.rs485.flags & SER_RS485_ENABLED)
2111                 termios->c_cflag &= ~CRTSCTS;
2112
2113         if (termios->c_cflag & CRTSCTS)
2114                 modem |= UARTMODIR_RXRTSE | UARTMODIR_TXCTSE;
2115         else
2116                 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
2117
2118         if (termios->c_cflag & CSTOPB)
2119                 bd |= UARTBAUD_SBNS;
2120         else
2121                 bd &= ~UARTBAUD_SBNS;
2122
2123         /* parity must be enabled when CS7 to match 8-bits format */
2124         if ((termios->c_cflag & CSIZE) == CS7)
2125                 termios->c_cflag |= PARENB;
2126
2127         if ((termios->c_cflag & PARENB)) {
2128                 if (termios->c_cflag & CMSPAR) {
2129                         ctrl &= ~UARTCTRL_PE;
2130                         ctrl |= UARTCTRL_M;
2131                 } else {
2132                         ctrl |= UARTCTRL_PE;
2133                         if ((termios->c_cflag & CSIZE) == CS8)
2134                                 ctrl |= UARTCTRL_M;
2135                         if (termios->c_cflag & PARODD)
2136                                 ctrl |= UARTCTRL_PT;
2137                         else
2138                                 ctrl &= ~UARTCTRL_PT;
2139                 }
2140         } else {
2141                 ctrl &= ~UARTCTRL_PE;
2142         }
2143
2144         /* ask the core to calculate the divisor */
2145         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
2146
2147         /*
2148          * Need to update the Ring buffer length according to the selected
2149          * baud rate and restart Rx DMA path.
2150          *
2151          * Since timer function acqures sport->port.lock, need to stop before
2152          * acquring same lock because otherwise del_timer_sync() can deadlock.
2153          */
2154         if (old && sport->lpuart_dma_rx_use) {
2155                 del_timer_sync(&sport->lpuart_timer);
2156                 lpuart_dma_rx_free(&sport->port);
2157         }
2158
2159         spin_lock_irqsave(&sport->port.lock, flags);
2160
2161         sport->port.read_status_mask = 0;
2162         if (termios->c_iflag & INPCK)
2163                 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE;
2164         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2165                 sport->port.read_status_mask |= UARTSTAT_FE;
2166
2167         /* characters to ignore */
2168         sport->port.ignore_status_mask = 0;
2169         if (termios->c_iflag & IGNPAR)
2170                 sport->port.ignore_status_mask |= UARTSTAT_PE;
2171         if (termios->c_iflag & IGNBRK) {
2172                 sport->port.ignore_status_mask |= UARTSTAT_FE;
2173                 /*
2174                  * if we're ignoring parity and break indicators,
2175                  * ignore overruns too (for real raw support).
2176                  */
2177                 if (termios->c_iflag & IGNPAR)
2178                         sport->port.ignore_status_mask |= UARTSTAT_OR;
2179         }
2180
2181         /* update the per-port timeout */
2182         uart_update_timeout(port, termios->c_cflag, baud);
2183
2184         /* wait transmit engin complete */
2185         lpuart32_write(&sport->port, 0, UARTMODIR);
2186         lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2187
2188         /* disable transmit and receive */
2189         lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
2190                        UARTCTRL);
2191
2192         lpuart32_write(&sport->port, bd, UARTBAUD);
2193         lpuart32_serial_setbrg(sport, baud);
2194         lpuart32_write(&sport->port, modem, UARTMODIR);
2195         lpuart32_write(&sport->port, ctrl, UARTCTRL);
2196         /* restore control register */
2197
2198         if (old && sport->lpuart_dma_rx_use) {
2199                 if (!lpuart_start_rx_dma(sport))
2200                         rx_dma_timer_init(sport);
2201                 else
2202                         sport->lpuart_dma_rx_use = false;
2203         }
2204
2205         spin_unlock_irqrestore(&sport->port.lock, flags);
2206 }
2207
2208 static const char *lpuart_type(struct uart_port *port)
2209 {
2210         return "FSL_LPUART";
2211 }
2212
2213 static void lpuart_release_port(struct uart_port *port)
2214 {
2215         /* nothing to do */
2216 }
2217
2218 static int lpuart_request_port(struct uart_port *port)
2219 {
2220         return  0;
2221 }
2222
2223 /* configure/autoconfigure the port */
2224 static void lpuart_config_port(struct uart_port *port, int flags)
2225 {
2226         if (flags & UART_CONFIG_TYPE)
2227                 port->type = PORT_LPUART;
2228 }
2229
2230 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
2231 {
2232         int ret = 0;
2233
2234         if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
2235                 ret = -EINVAL;
2236         if (port->irq != ser->irq)
2237                 ret = -EINVAL;
2238         if (ser->io_type != UPIO_MEM)
2239                 ret = -EINVAL;
2240         if (port->uartclk / 16 != ser->baud_base)
2241                 ret = -EINVAL;
2242         if (port->iobase != ser->port)
2243                 ret = -EINVAL;
2244         if (ser->hub6 != 0)
2245                 ret = -EINVAL;
2246         return ret;
2247 }
2248
2249 static const struct uart_ops lpuart_pops = {
2250         .tx_empty       = lpuart_tx_empty,
2251         .set_mctrl      = lpuart_set_mctrl,
2252         .get_mctrl      = lpuart_get_mctrl,
2253         .stop_tx        = lpuart_stop_tx,
2254         .start_tx       = lpuart_start_tx,
2255         .stop_rx        = lpuart_stop_rx,
2256         .break_ctl      = lpuart_break_ctl,
2257         .startup        = lpuart_startup,
2258         .shutdown       = lpuart_shutdown,
2259         .set_termios    = lpuart_set_termios,
2260         .type           = lpuart_type,
2261         .request_port   = lpuart_request_port,
2262         .release_port   = lpuart_release_port,
2263         .config_port    = lpuart_config_port,
2264         .verify_port    = lpuart_verify_port,
2265         .flush_buffer   = lpuart_flush_buffer,
2266 #if defined(CONFIG_CONSOLE_POLL)
2267         .poll_init      = lpuart_poll_init,
2268         .poll_get_char  = lpuart_poll_get_char,
2269         .poll_put_char  = lpuart_poll_put_char,
2270 #endif
2271 };
2272
2273 static const struct uart_ops lpuart32_pops = {
2274         .tx_empty       = lpuart32_tx_empty,
2275         .set_mctrl      = lpuart32_set_mctrl,
2276         .get_mctrl      = lpuart32_get_mctrl,
2277         .stop_tx        = lpuart32_stop_tx,
2278         .start_tx       = lpuart32_start_tx,
2279         .stop_rx        = lpuart32_stop_rx,
2280         .break_ctl      = lpuart32_break_ctl,
2281         .startup        = lpuart32_startup,
2282         .shutdown       = lpuart32_shutdown,
2283         .set_termios    = lpuart32_set_termios,
2284         .type           = lpuart_type,
2285         .request_port   = lpuart_request_port,
2286         .release_port   = lpuart_release_port,
2287         .config_port    = lpuart_config_port,
2288         .verify_port    = lpuart_verify_port,
2289         .flush_buffer   = lpuart_flush_buffer,
2290 #if defined(CONFIG_CONSOLE_POLL)
2291         .poll_init      = lpuart32_poll_init,
2292         .poll_get_char  = lpuart32_poll_get_char,
2293         .poll_put_char  = lpuart32_poll_put_char,
2294 #endif
2295 };
2296
2297 static struct lpuart_port *lpuart_ports[UART_NR];
2298
2299 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
2300 static void lpuart_console_putchar(struct uart_port *port, unsigned char ch)
2301 {
2302         lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
2303         writeb(ch, port->membase + UARTDR);
2304 }
2305
2306 static void lpuart32_console_putchar(struct uart_port *port, unsigned char ch)
2307 {
2308         lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
2309         lpuart32_write(port, ch, UARTDATA);
2310 }
2311
2312 static void
2313 lpuart_console_write(struct console *co, const char *s, unsigned int count)
2314 {
2315         struct lpuart_port *sport = lpuart_ports[co->index];
2316         unsigned char  old_cr2, cr2;
2317         unsigned long flags;
2318         int locked = 1;
2319
2320         if (oops_in_progress)
2321                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2322         else
2323                 spin_lock_irqsave(&sport->port.lock, flags);
2324
2325         /* first save CR2 and then disable interrupts */
2326         cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
2327         cr2 |= UARTCR2_TE | UARTCR2_RE;
2328         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
2329         writeb(cr2, sport->port.membase + UARTCR2);
2330
2331         uart_console_write(&sport->port, s, count, lpuart_console_putchar);
2332
2333         /* wait for transmitter finish complete and restore CR2 */
2334         lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2335
2336         writeb(old_cr2, sport->port.membase + UARTCR2);
2337
2338         if (locked)
2339                 spin_unlock_irqrestore(&sport->port.lock, flags);
2340 }
2341
2342 static void
2343 lpuart32_console_write(struct console *co, const char *s, unsigned int count)
2344 {
2345         struct lpuart_port *sport = lpuart_ports[co->index];
2346         unsigned long  old_cr, cr;
2347         unsigned long flags;
2348         int locked = 1;
2349
2350         if (oops_in_progress)
2351                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2352         else
2353                 spin_lock_irqsave(&sport->port.lock, flags);
2354
2355         /* first save CR2 and then disable interrupts */
2356         cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
2357         cr |= UARTCTRL_TE | UARTCTRL_RE;
2358         cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
2359         lpuart32_write(&sport->port, cr, UARTCTRL);
2360
2361         uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
2362
2363         /* wait for transmitter finish complete and restore CR2 */
2364         lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2365
2366         lpuart32_write(&sport->port, old_cr, UARTCTRL);
2367
2368         if (locked)
2369                 spin_unlock_irqrestore(&sport->port.lock, flags);
2370 }
2371
2372 /*
2373  * if the port was already initialised (eg, by a boot loader),
2374  * try to determine the current setup.
2375  */
2376 static void __init
2377 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
2378                            int *parity, int *bits)
2379 {
2380         unsigned char cr, bdh, bdl, brfa;
2381         unsigned int sbr, uartclk, baud_raw;
2382
2383         cr = readb(sport->port.membase + UARTCR2);
2384         cr &= UARTCR2_TE | UARTCR2_RE;
2385         if (!cr)
2386                 return;
2387
2388         /* ok, the port was enabled */
2389
2390         cr = readb(sport->port.membase + UARTCR1);
2391
2392         *parity = 'n';
2393         if (cr & UARTCR1_PE) {
2394                 if (cr & UARTCR1_PT)
2395                         *parity = 'o';
2396                 else
2397                         *parity = 'e';
2398         }
2399
2400         if (cr & UARTCR1_M)
2401                 *bits = 9;
2402         else
2403                 *bits = 8;
2404
2405         bdh = readb(sport->port.membase + UARTBDH);
2406         bdh &= UARTBDH_SBR_MASK;
2407         bdl = readb(sport->port.membase + UARTBDL);
2408         sbr = bdh;
2409         sbr <<= 8;
2410         sbr |= bdl;
2411         brfa = readb(sport->port.membase + UARTCR4);
2412         brfa &= UARTCR4_BRFA_MASK;
2413
2414         uartclk = lpuart_get_baud_clk_rate(sport);
2415         /*
2416          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2417          */
2418         baud_raw = uartclk / (16 * (sbr + brfa / 32));
2419
2420         if (*baud != baud_raw)
2421                 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2422                                 "from %d to %d\n", baud_raw, *baud);
2423 }
2424
2425 static void __init
2426 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
2427                            int *parity, int *bits)
2428 {
2429         unsigned long cr, bd;
2430         unsigned int sbr, uartclk, baud_raw;
2431
2432         cr = lpuart32_read(&sport->port, UARTCTRL);
2433         cr &= UARTCTRL_TE | UARTCTRL_RE;
2434         if (!cr)
2435                 return;
2436
2437         /* ok, the port was enabled */
2438
2439         cr = lpuart32_read(&sport->port, UARTCTRL);
2440
2441         *parity = 'n';
2442         if (cr & UARTCTRL_PE) {
2443                 if (cr & UARTCTRL_PT)
2444                         *parity = 'o';
2445                 else
2446                         *parity = 'e';
2447         }
2448
2449         if (cr & UARTCTRL_M)
2450                 *bits = 9;
2451         else
2452                 *bits = 8;
2453
2454         bd = lpuart32_read(&sport->port, UARTBAUD);
2455         bd &= UARTBAUD_SBR_MASK;
2456         if (!bd)
2457                 return;
2458
2459         sbr = bd;
2460         uartclk = lpuart_get_baud_clk_rate(sport);
2461         /*
2462          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2463          */
2464         baud_raw = uartclk / (16 * sbr);
2465
2466         if (*baud != baud_raw)
2467                 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2468                                 "from %d to %d\n", baud_raw, *baud);
2469 }
2470
2471 static int __init lpuart_console_setup(struct console *co, char *options)
2472 {
2473         struct lpuart_port *sport;
2474         int baud = 115200;
2475         int bits = 8;
2476         int parity = 'n';
2477         int flow = 'n';
2478
2479         /*
2480          * check whether an invalid uart number has been specified, and
2481          * if so, search for the first available port that does have
2482          * console support.
2483          */
2484         if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
2485                 co->index = 0;
2486
2487         sport = lpuart_ports[co->index];
2488         if (sport == NULL)
2489                 return -ENODEV;
2490
2491         if (options)
2492                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2493         else
2494                 if (lpuart_is_32(sport))
2495                         lpuart32_console_get_options(sport, &baud, &parity, &bits);
2496                 else
2497                         lpuart_console_get_options(sport, &baud, &parity, &bits);
2498
2499         if (lpuart_is_32(sport))
2500                 lpuart32_setup_watermark(sport);
2501         else
2502                 lpuart_setup_watermark(sport);
2503
2504         return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2505 }
2506
2507 static struct uart_driver lpuart_reg;
2508 static struct console lpuart_console = {
2509         .name           = DEV_NAME,
2510         .write          = lpuart_console_write,
2511         .device         = uart_console_device,
2512         .setup          = lpuart_console_setup,
2513         .flags          = CON_PRINTBUFFER,
2514         .index          = -1,
2515         .data           = &lpuart_reg,
2516 };
2517
2518 static struct console lpuart32_console = {
2519         .name           = DEV_NAME,
2520         .write          = lpuart32_console_write,
2521         .device         = uart_console_device,
2522         .setup          = lpuart_console_setup,
2523         .flags          = CON_PRINTBUFFER,
2524         .index          = -1,
2525         .data           = &lpuart_reg,
2526 };
2527
2528 static void lpuart_early_write(struct console *con, const char *s, unsigned n)
2529 {
2530         struct earlycon_device *dev = con->data;
2531
2532         uart_console_write(&dev->port, s, n, lpuart_console_putchar);
2533 }
2534
2535 static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
2536 {
2537         struct earlycon_device *dev = con->data;
2538
2539         uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
2540 }
2541
2542 static int __init lpuart_early_console_setup(struct earlycon_device *device,
2543                                           const char *opt)
2544 {
2545         if (!device->port.membase)
2546                 return -ENODEV;
2547
2548         device->con->write = lpuart_early_write;
2549         return 0;
2550 }
2551
2552 static int __init lpuart32_early_console_setup(struct earlycon_device *device,
2553                                           const char *opt)
2554 {
2555         if (!device->port.membase)
2556                 return -ENODEV;
2557
2558         if (device->port.iotype != UPIO_MEM32)
2559                 device->port.iotype = UPIO_MEM32BE;
2560
2561         device->con->write = lpuart32_early_write;
2562         return 0;
2563 }
2564
2565 static int __init ls1028a_early_console_setup(struct earlycon_device *device,
2566                                               const char *opt)
2567 {
2568         u32 cr;
2569
2570         if (!device->port.membase)
2571                 return -ENODEV;
2572
2573         device->port.iotype = UPIO_MEM32;
2574         device->con->write = lpuart32_early_write;
2575
2576         /* set the baudrate */
2577         if (device->port.uartclk && device->baud)
2578                 __lpuart32_serial_setbrg(&device->port, device->baud,
2579                                          false, false);
2580
2581         /* enable transmitter */
2582         cr = lpuart32_read(&device->port, UARTCTRL);
2583         cr |= UARTCTRL_TE;
2584         lpuart32_write(&device->port, cr, UARTCTRL);
2585
2586         return 0;
2587 }
2588
2589 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
2590                                                    const char *opt)
2591 {
2592         if (!device->port.membase)
2593                 return -ENODEV;
2594
2595         device->port.iotype = UPIO_MEM32;
2596         device->port.membase += IMX_REG_OFF;
2597         device->con->write = lpuart32_early_write;
2598
2599         return 0;
2600 }
2601 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2602 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2603 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
2604 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2605 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup);
2606 OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup);
2607 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2608 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2609
2610 #define LPUART_CONSOLE  (&lpuart_console)
2611 #define LPUART32_CONSOLE        (&lpuart32_console)
2612 #else
2613 #define LPUART_CONSOLE  NULL
2614 #define LPUART32_CONSOLE        NULL
2615 #endif
2616
2617 static struct uart_driver lpuart_reg = {
2618         .owner          = THIS_MODULE,
2619         .driver_name    = DRIVER_NAME,
2620         .dev_name       = DEV_NAME,
2621         .nr             = ARRAY_SIZE(lpuart_ports),
2622         .cons           = LPUART_CONSOLE,
2623 };
2624
2625 static int lpuart_probe(struct platform_device *pdev)
2626 {
2627         const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev);
2628         struct device_node *np = pdev->dev.of_node;
2629         struct lpuart_port *sport;
2630         struct resource *res;
2631         irq_handler_t handler;
2632         int ret;
2633
2634         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2635         if (!sport)
2636                 return -ENOMEM;
2637
2638         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2639         sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2640         if (IS_ERR(sport->port.membase))
2641                 return PTR_ERR(sport->port.membase);
2642
2643         sport->port.membase += sdata->reg_off;
2644         sport->port.mapbase = res->start + sdata->reg_off;
2645         sport->port.dev = &pdev->dev;
2646         sport->port.type = PORT_LPUART;
2647         sport->devtype = sdata->devtype;
2648         ret = platform_get_irq(pdev, 0);
2649         if (ret < 0)
2650                 return ret;
2651         sport->port.irq = ret;
2652         sport->port.iotype = sdata->iotype;
2653         if (lpuart_is_32(sport))
2654                 sport->port.ops = &lpuart32_pops;
2655         else
2656                 sport->port.ops = &lpuart_pops;
2657         sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE);
2658         sport->port.flags = UPF_BOOT_AUTOCONF;
2659
2660         if (lpuart_is_32(sport))
2661                 sport->port.rs485_config = lpuart32_config_rs485;
2662         else
2663                 sport->port.rs485_config = lpuart_config_rs485;
2664
2665         sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
2666         if (IS_ERR(sport->ipg_clk)) {
2667                 ret = PTR_ERR(sport->ipg_clk);
2668                 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret);
2669                 return ret;
2670         }
2671
2672         sport->baud_clk = NULL;
2673         if (is_imx8qxp_lpuart(sport)) {
2674                 sport->baud_clk = devm_clk_get(&pdev->dev, "baud");
2675                 if (IS_ERR(sport->baud_clk)) {
2676                         ret = PTR_ERR(sport->baud_clk);
2677                         dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret);
2678                         return ret;
2679                 }
2680         }
2681
2682         ret = of_alias_get_id(np, "serial");
2683         if (ret < 0) {
2684                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2685                 return ret;
2686         }
2687         if (ret >= ARRAY_SIZE(lpuart_ports)) {
2688                 dev_err(&pdev->dev, "serial%d out of range\n", ret);
2689                 return -EINVAL;
2690         }
2691         sport->port.line = ret;
2692
2693         ret = lpuart_enable_clks(sport);
2694         if (ret)
2695                 return ret;
2696         sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
2697
2698         lpuart_ports[sport->port.line] = sport;
2699
2700         platform_set_drvdata(pdev, &sport->port);
2701
2702         if (lpuart_is_32(sport)) {
2703                 lpuart_reg.cons = LPUART32_CONSOLE;
2704                 handler = lpuart32_int;
2705         } else {
2706                 lpuart_reg.cons = LPUART_CONSOLE;
2707                 handler = lpuart_int;
2708         }
2709
2710         ret = lpuart_global_reset(sport);
2711         if (ret)
2712                 goto failed_reset;
2713
2714         ret = uart_add_one_port(&lpuart_reg, &sport->port);
2715         if (ret)
2716                 goto failed_attach_port;
2717
2718         ret = uart_get_rs485_mode(&sport->port);
2719         if (ret)
2720                 goto failed_get_rs485;
2721
2722         if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX)
2723                 dev_err(&pdev->dev, "driver doesn't support RX during TX\n");
2724
2725         if (sport->port.rs485.delay_rts_before_send ||
2726             sport->port.rs485.delay_rts_after_send)
2727                 dev_err(&pdev->dev, "driver doesn't support RTS delays\n");
2728
2729         sport->port.rs485_config(&sport->port, &sport->port.rs485);
2730
2731         ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0,
2732                                 DRIVER_NAME, sport);
2733         if (ret)
2734                 goto failed_irq_request;
2735
2736         return 0;
2737
2738 failed_irq_request:
2739 failed_get_rs485:
2740         uart_remove_one_port(&lpuart_reg, &sport->port);
2741 failed_attach_port:
2742 failed_reset:
2743         lpuart_disable_clks(sport);
2744         return ret;
2745 }
2746
2747 static int lpuart_remove(struct platform_device *pdev)
2748 {
2749         struct lpuart_port *sport = platform_get_drvdata(pdev);
2750
2751         uart_remove_one_port(&lpuart_reg, &sport->port);
2752
2753         lpuart_disable_clks(sport);
2754
2755         if (sport->dma_tx_chan)
2756                 dma_release_channel(sport->dma_tx_chan);
2757
2758         if (sport->dma_rx_chan)
2759                 dma_release_channel(sport->dma_rx_chan);
2760
2761         return 0;
2762 }
2763
2764 static int __maybe_unused lpuart_suspend(struct device *dev)
2765 {
2766         struct lpuart_port *sport = dev_get_drvdata(dev);
2767         unsigned long temp;
2768         bool irq_wake;
2769
2770         if (lpuart_is_32(sport)) {
2771                 /* disable Rx/Tx and interrupts */
2772                 temp = lpuart32_read(&sport->port, UARTCTRL);
2773                 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
2774                 lpuart32_write(&sport->port, temp, UARTCTRL);
2775         } else {
2776                 /* disable Rx/Tx and interrupts */
2777                 temp = readb(sport->port.membase + UARTCR2);
2778                 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
2779                 writeb(temp, sport->port.membase + UARTCR2);
2780         }
2781
2782         uart_suspend_port(&lpuart_reg, &sport->port);
2783
2784         /* uart_suspend_port() might set wakeup flag */
2785         irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2786
2787         if (sport->lpuart_dma_rx_use) {
2788                 /*
2789                  * EDMA driver during suspend will forcefully release any
2790                  * non-idle DMA channels. If port wakeup is enabled or if port
2791                  * is console port or 'no_console_suspend' is set the Rx DMA
2792                  * cannot resume as as expected, hence gracefully release the
2793                  * Rx DMA path before suspend and start Rx DMA path on resume.
2794                  */
2795                 if (irq_wake) {
2796                         del_timer_sync(&sport->lpuart_timer);
2797                         lpuart_dma_rx_free(&sport->port);
2798                 }
2799
2800                 /* Disable Rx DMA to use UART port as wakeup source */
2801                 if (lpuart_is_32(sport)) {
2802                         temp = lpuart32_read(&sport->port, UARTBAUD);
2803                         lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
2804                                        UARTBAUD);
2805                 } else {
2806                         writeb(readb(sport->port.membase + UARTCR5) &
2807                                ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
2808                 }
2809         }
2810
2811         if (sport->lpuart_dma_tx_use) {
2812                 sport->dma_tx_in_progress = false;
2813                 dmaengine_terminate_all(sport->dma_tx_chan);
2814         }
2815
2816         if (sport->port.suspended && !irq_wake)
2817                 lpuart_disable_clks(sport);
2818
2819         return 0;
2820 }
2821
2822 static int __maybe_unused lpuart_resume(struct device *dev)
2823 {
2824         struct lpuart_port *sport = dev_get_drvdata(dev);
2825         bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2826
2827         if (sport->port.suspended && !irq_wake)
2828                 lpuart_enable_clks(sport);
2829
2830         if (lpuart_is_32(sport))
2831                 lpuart32_setup_watermark_enable(sport);
2832         else
2833                 lpuart_setup_watermark_enable(sport);
2834
2835         if (sport->lpuart_dma_rx_use) {
2836                 if (irq_wake) {
2837                         if (!lpuart_start_rx_dma(sport))
2838                                 rx_dma_timer_init(sport);
2839                         else
2840                                 sport->lpuart_dma_rx_use = false;
2841                 }
2842         }
2843
2844         lpuart_tx_dma_startup(sport);
2845
2846         if (lpuart_is_32(sport))
2847                 lpuart32_configure(sport);
2848
2849         uart_resume_port(&lpuart_reg, &sport->port);
2850
2851         return 0;
2852 }
2853
2854 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2855
2856 static struct platform_driver lpuart_driver = {
2857         .probe          = lpuart_probe,
2858         .remove         = lpuart_remove,
2859         .driver         = {
2860                 .name   = "fsl-lpuart",
2861                 .of_match_table = lpuart_dt_ids,
2862                 .pm     = &lpuart_pm_ops,
2863         },
2864 };
2865
2866 static int __init lpuart_serial_init(void)
2867 {
2868         int ret = uart_register_driver(&lpuart_reg);
2869
2870         if (ret)
2871                 return ret;
2872
2873         ret = platform_driver_register(&lpuart_driver);
2874         if (ret)
2875                 uart_unregister_driver(&lpuart_reg);
2876
2877         return ret;
2878 }
2879
2880 static void __exit lpuart_serial_exit(void)
2881 {
2882         platform_driver_unregister(&lpuart_driver);
2883         uart_unregister_driver(&lpuart_reg);
2884 }
2885
2886 module_init(lpuart_serial_init);
2887 module_exit(lpuart_serial_exit);
2888
2889 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2890 MODULE_LICENSE("GPL v2");