git.itanic.dy.fi Git - linux-stable/blob - drivers/usb/host/xhci-hub.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11
  12 #include <linux/slab.h>
  13 #include <asm/unaligned.h>
  14
  15 #include "xhci.h"
  16 #include "xhci-trace.h"
  17
  18 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  19 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  20                          PORT_RC | PORT_PLC | PORT_PE)
  21
  22 /* USB 3 BOS descriptor and a capability descriptors, combined.
  23  * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
  24  */
  25 static u8 usb_bos_descriptor [] = {
  26         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  27         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  28         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  29         0x1,                            /*  __u8 bNumDeviceCaps */
  30         /* First device capability, SuperSpeed */
  31         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  32         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  33         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  34         0x00,                           /* bmAttributes, LTM off by default */
  35         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  36         0x03,                           /* bFunctionalitySupport,
  37                                            USB 3.0 speed only */
  38         0x00,                           /* bU1DevExitLat, set later. */
  39         0x00, 0x00,                     /* __le16 bU2DevExitLat, set later. */
  40         /* Second device capability, SuperSpeedPlus */
  41         0x1c,                           /* bLength 28, will be adjusted later */
  42         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  43         USB_SSP_CAP_TYPE,               /* bDevCapabilityType SUPERSPEED_PLUS */
  44         0x00,                           /* bReserved 0 */
  45         0x23, 0x00, 0x00, 0x00,         /* bmAttributes, SSAC=3 SSIC=1 */
  46         0x01, 0x00,                     /* wFunctionalitySupport */
  47         0x00, 0x00,                     /* wReserved 0 */
  48         /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
  49         0x34, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, rx, ID = 4 */
  50         0xb4, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, tx, ID = 4 */
  51         0x35, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, rx, ID = 5 */
  52         0xb5, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, tx, ID = 5 */
  53 };
  54
  55 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
  56                                      u16 wLength)
  57 {
  58         struct xhci_port_cap *port_cap = NULL;
  59         int i, ssa_count;
  60         u32 temp;
  61         u16 desc_size, ssp_cap_size, ssa_size = 0;
  62         bool usb3_1 = false;
  63
  64         desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
  65         ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
  66
  67         /* does xhci support USB 3.1 Enhanced SuperSpeed */
  68         for (i = 0; i < xhci->num_port_caps; i++) {
  69                 if (xhci->port_caps[i].maj_rev == 0x03 &&
  70                     xhci->port_caps[i].min_rev >= 0x01) {
  71                         usb3_1 = true;
  72                         port_cap = &xhci->port_caps[i];
  73                         break;
  74                 }
  75         }
  76
  77         if (usb3_1) {
  78                 /* does xhci provide a PSI table for SSA speed attributes? */
  79                 if (port_cap->psi_count) {
  80                         /* two SSA entries for each unique PSI ID, RX and TX */
  81                         ssa_count = port_cap->psi_uid_count * 2;
  82                         ssa_size = ssa_count * sizeof(u32);
  83                         ssp_cap_size -= 16; /* skip copying the default SSA */
  84                 }
  85                 desc_size += ssp_cap_size;
  86         }
  87         memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
  88
  89         if (usb3_1) {
  90                 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
  91                 buf[4] += 1;
  92                 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
  93         }
  94
  95         if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
  96                 return wLength;
  97
  98         /* Indicate whether the host has LTM support. */
  99         temp = readl(&xhci->cap_regs->hcc_params);
 100         if (HCC_LTC(temp))
 101                 buf[8] |= USB_LTM_SUPPORT;
 102
 103         /* Set the U1 and U2 exit latencies. */
 104         if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
 105                 temp = readl(&xhci->cap_regs->hcs_params3);
 106                 buf[12] = HCS_U1_LATENCY(temp);
 107                 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
 108         }
 109
 110         /* If PSI table exists, add the custom speed attributes from it */
 111         if (usb3_1 && port_cap->psi_count) {
 112                 u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
 113                 int offset;
 114
 115                 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 116
 117                 if (wLength < desc_size)
 118                         return wLength;
 119                 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
 120
 121                 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
 122                 bm_attrib = (ssa_count - 1) & 0x1f;
 123                 bm_attrib |= (port_cap->psi_uid_count - 1) << 5;
 124                 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
 125
 126                 if (wLength < desc_size + ssa_size)
 127                         return wLength;
 128                 /*
 129                  * Create the Sublink Speed Attributes (SSA) array.
 130                  * The xhci PSI field and USB 3.1 SSA fields are very similar,
 131                  * but link type bits 7:6 differ for values 01b and 10b.
 132                  * xhci has also only one PSI entry for a symmetric link when
 133                  * USB 3.1 requires two SSA entries (RX and TX) for every link
 134                  */
 135                 offset = desc_size;
 136                 for (i = 0; i < port_cap->psi_count; i++) {
 137                         psi = port_cap->psi[i];
 138                         psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
 139                         psi_exp = XHCI_EXT_PORT_PSIE(psi);
 140                         psi_mant = XHCI_EXT_PORT_PSIM(psi);
 141
 142                         /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
 143                         for (; psi_exp < 3; psi_exp++)
 144                                 psi_mant /= 1000;
 145                         if (psi_mant >= 10)
 146                                 psi |= BIT(14);
 147
 148                         if ((psi & PLT_MASK) == PLT_SYM) {
 149                         /* Symmetric, create SSA RX and TX from one PSI entry */
 150                                 put_unaligned_le32(psi, &buf[offset]);
 151                                 psi |= 1 << 7;  /* turn entry to TX */
 152                                 offset += 4;
 153                                 if (offset >= desc_size + ssa_size)
 154                                         return desc_size + ssa_size;
 155                         } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
 156                                 /* Asymetric RX, flip bits 7:6 for SSA */
 157                                 psi ^= PLT_MASK;
 158                         }
 159                         put_unaligned_le32(psi, &buf[offset]);
 160                         offset += 4;
 161                         if (offset >= desc_size + ssa_size)
 162                                 return desc_size + ssa_size;
 163                 }
 164         }
 165         /* ssa_size is 0 for other than usb 3.1 hosts */
 166         return desc_size + ssa_size;
 167 }
 168
 169 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
 170                 struct usb_hub_descriptor *desc, int ports)
 171 {
 172         u16 temp;
 173
 174         desc->bHubContrCurrent = 0;
 175
 176         desc->bNbrPorts = ports;
 177         temp = 0;
 178         /* Bits 1:0 - support per-port power switching, or power always on */
 179         if (HCC_PPC(xhci->hcc_params))
 180                 temp |= HUB_CHAR_INDV_PORT_LPSM;
 181         else
 182                 temp |= HUB_CHAR_NO_LPSM;
 183         /* Bit  2 - root hubs are not part of a compound device */
 184         /* Bits 4:3 - individual port over current protection */
 185         temp |= HUB_CHAR_INDV_PORT_OCPM;
 186         /* Bits 6:5 - no TTs in root ports */
 187         /* Bit  7 - no port indicators */
 188         desc->wHubCharacteristics = cpu_to_le16(temp);
 189 }
 190
 191 /* Fill in the USB 2.0 roothub descriptor */
 192 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 193                 struct usb_hub_descriptor *desc)
 194 {
 195         int ports;
 196         u16 temp;
 197         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
 198         u32 portsc;
 199         unsigned int i;
 200         struct xhci_hub *rhub;
 201
 202         rhub = &xhci->usb2_rhub;
 203         ports = rhub->num_ports;
 204         xhci_common_hub_descriptor(xhci, desc, ports);
 205         desc->bDescriptorType = USB_DT_HUB;
 206         temp = 1 + (ports / 8);
 207         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
 208         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.8 says 20ms */
 209
 210         /* The Device Removable bits are reported on a byte granularity.
 211          * If the port doesn't exist within that byte, the bit is set to 0.
 212          */
 213         memset(port_removable, 0, sizeof(port_removable));
 214         for (i = 0; i < ports; i++) {
 215                 portsc = readl(rhub->ports[i]->addr);
 216                 /* If a device is removable, PORTSC reports a 0, same as in the
 217                  * hub descriptor DeviceRemovable bits.
 218                  */
 219                 if (portsc & PORT_DEV_REMOVE)
 220                         /* This math is hairy because bit 0 of DeviceRemovable
 221                          * is reserved, and bit 1 is for port 1, etc.
 222                          */
 223                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 224         }
 225
 226         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 227          * ports on it.  The USB 2.0 specification says that there are two
 228          * variable length fields at the end of the hub descriptor:
 229          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 230          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 231          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 232          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 233          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 234          * set of ports that actually exist.
 235          */
 236         memset(desc->u.hs.DeviceRemovable, 0xff,
 237                         sizeof(desc->u.hs.DeviceRemovable));
 238         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 239                         sizeof(desc->u.hs.PortPwrCtrlMask));
 240
 241         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 242                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 243                                 sizeof(__u8));
 244 }
 245
 246 /* Fill in the USB 3.0 roothub descriptor */
 247 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 248                 struct usb_hub_descriptor *desc)
 249 {
 250         int ports;
 251         u16 port_removable;
 252         u32 portsc;
 253         unsigned int i;
 254         struct xhci_hub *rhub;
 255
 256         rhub = &xhci->usb3_rhub;
 257         ports = rhub->num_ports;
 258         xhci_common_hub_descriptor(xhci, desc, ports);
 259         desc->bDescriptorType = USB_DT_SS_HUB;
 260         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 261         desc->bPwrOn2PwrGood = 50;      /* usb 3.1 may fail if less than 100ms */
 262
 263         /* header decode latency should be zero for roothubs,
 264          * see section 4.23.5.2.
 265          */
 266         desc->u.ss.bHubHdrDecLat = 0;
 267         desc->u.ss.wHubDelay = 0;
 268
 269         port_removable = 0;
 270         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 271         for (i = 0; i < ports; i++) {
 272                 portsc = readl(rhub->ports[i]->addr);
 273                 if (portsc & PORT_DEV_REMOVE)
 274                         port_removable |= 1 << (i + 1);
 275         }
 276
 277         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 278 }
 279
 280 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 281                 struct usb_hub_descriptor *desc)
 282 {
 283
 284         if (hcd->speed >= HCD_USB3)
 285                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 286         else
 287                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 288
 289 }
 290
 291 static unsigned int xhci_port_speed(unsigned int port_status)
 292 {
 293         if (DEV_LOWSPEED(port_status))
 294                 return USB_PORT_STAT_LOW_SPEED;
 295         if (DEV_HIGHSPEED(port_status))
 296                 return USB_PORT_STAT_HIGH_SPEED;
 297         /*
 298          * FIXME: Yes, we should check for full speed, but the core uses that as
 299          * a default in portspeed() in usb/core/hub.c (which is the only place
 300          * USB_PORT_STAT_*_SPEED is used).
 301          */
 302         return 0;
 303 }
 304
 305 /*
 306  * These bits are Read Only (RO) and should be saved and written to the
 307  * registers: 0, 3, 10:13, 30
 308  * connect status, over-current status, port speed, and device removable.
 309  * connect status and port speed are also sticky - meaning they're in
 310  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 311  */
 312 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 313 /*
 314  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 315  * bits 5:8, 9, 14:15, 25:27
 316  * link state, port power, port indicator state, "wake on" enable state
 317  */
 318 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 319 /*
 320  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 321  * bit 4 (port reset)
 322  */
 323 #define XHCI_PORT_RW1S  ((1<<4))
 324 /*
 325  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 326  * bits 1, 17, 18, 19, 20, 21, 22, 23
 327  * port enable/disable, and
 328  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 329  * over-current, reset, link state, and L1 change
 330  */
 331 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 332 /*
 333  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 334  * latched in
 335  */
 336 #define XHCI_PORT_RW    ((1<<16))
 337 /*
 338  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 339  * bits 2, 24, 28:31
 340  */
 341 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 342
 343 /*
 344  * Given a port state, this function returns a value that would result in the
 345  * port being in the same state, if the value was written to the port status
 346  * control register.
 347  * Save Read Only (RO) bits and save read/write bits where
 348  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 349  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 350  */
 351 u32 xhci_port_state_to_neutral(u32 state)
 352 {
 353         /* Save read-only status and port state */
 354         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 355 }
 356
 357 /*
 358  * find slot id based on port number.
 359  * @port: The one-based port number from one of the two split roothubs.
 360  */
 361 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 362                 u16 port)
 363 {
 364         int slot_id;
 365         int i;
 366         enum usb_device_speed speed;
 367
 368         slot_id = 0;
 369         for (i = 0; i < MAX_HC_SLOTS; i++) {
 370                 if (!xhci->devs[i] || !xhci->devs[i]->udev)
 371                         continue;
 372                 speed = xhci->devs[i]->udev->speed;
 373                 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
 374                                 && xhci->devs[i]->fake_port == port) {
 375                         slot_id = i;
 376                         break;
 377                 }
 378         }
 379
 380         return slot_id;
 381 }
 382
 383 /*
 384  * Stop device
 385  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 386  * to complete.
 387  * suspend will set to 1, if suspend bit need to set in command.
 388  */
 389 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 390 {
 391         struct xhci_virt_device *virt_dev;
 392         struct xhci_command *cmd;
 393         unsigned long flags;
 394         int ret;
 395         int i;
 396
 397         ret = 0;
 398         virt_dev = xhci->devs[slot_id];
 399         if (!virt_dev)
 400                 return -ENODEV;
 401
 402         trace_xhci_stop_device(virt_dev);
 403
 404         cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
 405         if (!cmd)
 406                 return -ENOMEM;
 407
 408         spin_lock_irqsave(&xhci->lock, flags);
 409         for (i = LAST_EP_INDEX; i > 0; i--) {
 410                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
 411                         struct xhci_ep_ctx *ep_ctx;
 412                         struct xhci_command *command;
 413
 414                         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
 415
 416                         /* Check ep is running, required by AMD SNPS 3.1 xHC */
 417                         if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
 418                                 continue;
 419
 420                         command = xhci_alloc_command(xhci, false, GFP_NOWAIT);
 421                         if (!command) {
 422                                 spin_unlock_irqrestore(&xhci->lock, flags);
 423                                 ret = -ENOMEM;
 424                                 goto cmd_cleanup;
 425                         }
 426
 427                         ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
 428                                                        i, suspend);
 429                         if (ret) {
 430                                 spin_unlock_irqrestore(&xhci->lock, flags);
 431                                 xhci_free_command(xhci, command);
 432                                 goto cmd_cleanup;
 433                         }
 434                 }
 435         }
 436         ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
 437         if (ret) {
 438                 spin_unlock_irqrestore(&xhci->lock, flags);
 439                 goto cmd_cleanup;
 440         }
 441
 442         xhci_ring_cmd_db(xhci);
 443         spin_unlock_irqrestore(&xhci->lock, flags);
 444
 445         /* Wait for last stop endpoint command to finish */
 446         wait_for_completion(cmd->completion);
 447
 448         if (cmd->status == COMP_COMMAND_ABORTED ||
 449             cmd->status == COMP_COMMAND_RING_STOPPED) {
 450                 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
 451                 ret = -ETIME;
 452         }
 453
 454 cmd_cleanup:
 455         xhci_free_command(xhci, cmd);
 456         return ret;
 457 }
 458
 459 /*
 460  * Ring device, it rings the all doorbells unconditionally.
 461  */
 462 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 463 {
 464         int i, s;
 465         struct xhci_virt_ep *ep;
 466
 467         for (i = 0; i < LAST_EP_INDEX + 1; i++) {
 468                 ep = &xhci->devs[slot_id]->eps[i];
 469
 470                 if (ep->ep_state & EP_HAS_STREAMS) {
 471                         for (s = 1; s < ep->stream_info->num_streams; s++)
 472                                 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
 473                 } else if (ep->ring && ep->ring->dequeue) {
 474                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 475                 }
 476         }
 477
 478         return;
 479 }
 480
 481 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 482                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 483 {
 484         /* Don't allow the USB core to disable SuperSpeed ports. */
 485         if (hcd->speed >= HCD_USB3) {
 486                 xhci_dbg(xhci, "Ignoring request to disable "
 487                                 "SuperSpeed port.\n");
 488                 return;
 489         }
 490
 491         if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
 492                 xhci_dbg(xhci,
 493                          "Broken Port Enabled/Disabled, ignoring port disable request.\n");
 494                 return;
 495         }
 496
 497         /* Write 1 to disable the port */
 498         writel(port_status | PORT_PE, addr);
 499         port_status = readl(addr);
 500         xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
 501                         wIndex, port_status);
 502 }
 503
 504 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 505                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 506 {
 507         char *port_change_bit;
 508         u32 status;
 509
 510         switch (wValue) {
 511         case USB_PORT_FEAT_C_RESET:
 512                 status = PORT_RC;
 513                 port_change_bit = "reset";
 514                 break;
 515         case USB_PORT_FEAT_C_BH_PORT_RESET:
 516                 status = PORT_WRC;
 517                 port_change_bit = "warm(BH) reset";
 518                 break;
 519         case USB_PORT_FEAT_C_CONNECTION:
 520                 status = PORT_CSC;
 521                 port_change_bit = "connect";
 522                 break;
 523         case USB_PORT_FEAT_C_OVER_CURRENT:
 524                 status = PORT_OCC;
 525                 port_change_bit = "over-current";
 526                 break;
 527         case USB_PORT_FEAT_C_ENABLE:
 528                 status = PORT_PEC;
 529                 port_change_bit = "enable/disable";
 530                 break;
 531         case USB_PORT_FEAT_C_SUSPEND:
 532                 status = PORT_PLC;
 533                 port_change_bit = "suspend/resume";
 534                 break;
 535         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 536                 status = PORT_PLC;
 537                 port_change_bit = "link state";
 538                 break;
 539         case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
 540                 status = PORT_CEC;
 541                 port_change_bit = "config error";
 542                 break;
 543         default:
 544                 /* Should never happen */
 545                 return;
 546         }
 547         /* Change bits are all write 1 to clear */
 548         writel(port_status | status, addr);
 549         port_status = readl(addr);
 550         xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
 551                         port_change_bit, wIndex, port_status);
 552 }
 553
 554 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
 555 {
 556         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 557
 558         if (hcd->speed >= HCD_USB3)
 559                 return &xhci->usb3_rhub;
 560         return &xhci->usb2_rhub;
 561 }
 562
 563 /*
 564  * xhci_set_port_power() must be called with xhci->lock held.
 565  * It will release and re-aquire the lock while calling ACPI
 566  * method.
 567  */
 568 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
 569                                 u16 index, bool on, unsigned long *flags)
 570 {
 571         struct xhci_hub *rhub;
 572         struct xhci_port *port;
 573         u32 temp;
 574
 575         rhub = xhci_get_rhub(hcd);
 576         port = rhub->ports[index];
 577         temp = readl(port->addr);
 578         temp = xhci_port_state_to_neutral(temp);
 579         if (on) {
 580                 /* Power on */
 581                 writel(temp | PORT_POWER, port->addr);
 582                 temp = readl(port->addr);
 583                 xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n",
 584                                                 index, temp);
 585         } else {
 586                 /* Power off */
 587                 writel(temp & ~PORT_POWER, port->addr);
 588         }
 589
 590         spin_unlock_irqrestore(&xhci->lock, *flags);
 591         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 592                                         index);
 593         if (temp)
 594                 usb_acpi_set_power_state(hcd->self.root_hub,
 595                         index, on);
 596         spin_lock_irqsave(&xhci->lock, *flags);
 597 }
 598
 599 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
 600         u16 test_mode, u16 wIndex)
 601 {
 602         u32 temp;
 603         struct xhci_port *port;
 604
 605         /* xhci only supports test mode for usb2 ports */
 606         port = xhci->usb2_rhub.ports[wIndex];
 607         temp = readl(port->addr + PORTPMSC);
 608         temp |= test_mode << PORT_TEST_MODE_SHIFT;
 609         writel(temp, port->addr + PORTPMSC);
 610         xhci->test_mode = test_mode;
 611         if (test_mode == TEST_FORCE_EN)
 612                 xhci_start(xhci);
 613 }
 614
 615 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
 616                                 u16 test_mode, u16 wIndex, unsigned long *flags)
 617 {
 618         int i, retval;
 619
 620         /* Disable all Device Slots */
 621         xhci_dbg(xhci, "Disable all slots\n");
 622         spin_unlock_irqrestore(&xhci->lock, *flags);
 623         for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
 624                 if (!xhci->devs[i])
 625                         continue;
 626
 627                 retval = xhci_disable_slot(xhci, i);
 628                 xhci_free_virt_device(xhci, i);
 629                 if (retval)
 630                         xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
 631                                  i, retval);
 632         }
 633         spin_lock_irqsave(&xhci->lock, *flags);
 634         /* Put all ports to the Disable state by clear PP */
 635         xhci_dbg(xhci, "Disable all port (PP = 0)\n");
 636         /* Power off USB3 ports*/
 637         for (i = 0; i < xhci->usb3_rhub.num_ports; i++)
 638                 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
 639         /* Power off USB2 ports*/
 640         for (i = 0; i < xhci->usb2_rhub.num_ports; i++)
 641                 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
 642         /* Stop the controller */
 643         xhci_dbg(xhci, "Stop controller\n");
 644         retval = xhci_halt(xhci);
 645         if (retval)
 646                 return retval;
 647         /* Disable runtime PM for test mode */
 648         pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
 649         /* Set PORTPMSC.PTC field to enter selected test mode */
 650         /* Port is selected by wIndex. port_id = wIndex + 1 */
 651         xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
 652                                         test_mode, wIndex + 1);
 653         xhci_port_set_test_mode(xhci, test_mode, wIndex);
 654         return retval;
 655 }
 656
 657 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
 658 {
 659         int retval;
 660
 661         if (!xhci->test_mode) {
 662                 xhci_err(xhci, "Not in test mode, do nothing.\n");
 663                 return 0;
 664         }
 665         if (xhci->test_mode == TEST_FORCE_EN &&
 666                 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
 667                 retval = xhci_halt(xhci);
 668                 if (retval)
 669                         return retval;
 670         }
 671         pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
 672         xhci->test_mode = 0;
 673         return xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
 674 }
 675
 676 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
 677                          u32 link_state)
 678 {
 679         u32 temp;
 680
 681         temp = readl(port->addr);
 682         temp = xhci_port_state_to_neutral(temp);
 683         temp &= ~PORT_PLS_MASK;
 684         temp |= PORT_LINK_STROBE | link_state;
 685         writel(temp, port->addr);
 686 }
 687
 688 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 689                                       struct xhci_port *port, u16 wake_mask)
 690 {
 691         u32 temp;
 692
 693         temp = readl(port->addr);
 694         temp = xhci_port_state_to_neutral(temp);
 695
 696         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 697                 temp |= PORT_WKCONN_E;
 698         else
 699                 temp &= ~PORT_WKCONN_E;
 700
 701         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 702                 temp |= PORT_WKDISC_E;
 703         else
 704                 temp &= ~PORT_WKDISC_E;
 705
 706         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 707                 temp |= PORT_WKOC_E;
 708         else
 709                 temp &= ~PORT_WKOC_E;
 710
 711         writel(temp, port->addr);
 712 }
 713
 714 /* Test and clear port RWC bit */
 715 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
 716                              u32 port_bit)
 717 {
 718         u32 temp;
 719
 720         temp = readl(port->addr);
 721         if (temp & port_bit) {
 722                 temp = xhci_port_state_to_neutral(temp);
 723                 temp |= port_bit;
 724                 writel(temp, port->addr);
 725         }
 726 }
 727
 728 /* Updates Link Status for USB 2.1 port */
 729 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
 730 {
 731         if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
 732                 *status |= USB_PORT_STAT_L1;
 733 }
 734
 735 /* Updates Link Status for super Speed port */
 736 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
 737                 u32 *status, u32 status_reg)
 738 {
 739         u32 pls = status_reg & PORT_PLS_MASK;
 740
 741         /* When the CAS bit is set then warm reset
 742          * should be performed on port
 743          */
 744         if (status_reg & PORT_CAS) {
 745                 /* The CAS bit can be set while the port is
 746                  * in any link state.
 747                  * Only roothubs have CAS bit, so we
 748                  * pretend to be in compliance mode
 749                  * unless we're already in compliance
 750                  * or the inactive state.
 751                  */
 752                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 753                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 754                         pls = USB_SS_PORT_LS_COMP_MOD;
 755                 }
 756                 /* Return also connection bit -
 757                  * hub state machine resets port
 758                  * when this bit is set.
 759                  */
 760                 pls |= USB_PORT_STAT_CONNECTION;
 761         } else {
 762                 /*
 763                  * Resume state is an xHCI internal state.  Do not report it to
 764                  * usb core, instead, pretend to be U3, thus usb core knows
 765                  * it's not ready for transfer.
 766                  */
 767                 if (pls == XDEV_RESUME) {
 768                         *status |= USB_SS_PORT_LS_U3;
 769                         return;
 770                 }
 771
 772                 /*
 773                  * If CAS bit isn't set but the Port is already at
 774                  * Compliance Mode, fake a connection so the USB core
 775                  * notices the Compliance state and resets the port.
 776                  * This resolves an issue generated by the SN65LVPE502CP
 777                  * in which sometimes the port enters compliance mode
 778                  * caused by a delay on the host-device negotiation.
 779                  */
 780                 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 781                                 (pls == USB_SS_PORT_LS_COMP_MOD))
 782                         pls |= USB_PORT_STAT_CONNECTION;
 783         }
 784
 785         /* update status field */
 786         *status |= pls;
 787 }
 788
 789 /*
 790  * Function for Compliance Mode Quirk.
 791  *
 792  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 793  * the compliance mode timer is deleted. A port won't enter
 794  * compliance mode if it has previously entered U0.
 795  */
 796 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
 797                                     u16 wIndex)
 798 {
 799         u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1);
 800         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 801
 802         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 803                 return;
 804
 805         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 806                 xhci->port_status_u0 |= 1 << wIndex;
 807                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 808                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 809                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 810                                 "All USB3 ports have entered U0 already!");
 811                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 812                                 "Compliance Mode Recovery Timer Deleted.");
 813                 }
 814         }
 815 }
 816
 817 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
 818 {
 819         u32 ext_stat = 0;
 820         int speed_id;
 821
 822         /* only support rx and tx lane counts of 1 in usb3.1 spec */
 823         speed_id = DEV_PORT_SPEED(raw_port_status);
 824         ext_stat |= speed_id;           /* bits 3:0, RX speed id */
 825         ext_stat |= speed_id << 4;      /* bits 7:4, TX speed id */
 826
 827         ext_stat |= PORT_RX_LANES(port_li) << 8;  /* bits 11:8 Rx lane count */
 828         ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
 829
 830         return ext_stat;
 831 }
 832
 833 /*
 834  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
 835  * 3.0 hubs use.
 836  *
 837  * Possible side effects:
 838  *  - Mark a port as being done with device resume,
 839  *    and ring the endpoint doorbells.
 840  *  - Stop the Synopsys redriver Compliance Mode polling.
 841  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
 842  */
 843 static u32 xhci_get_port_status(struct usb_hcd *hcd,
 844                 struct xhci_bus_state *bus_state,
 845         u16 wIndex, u32 raw_port_status,
 846                 unsigned long *flags)
 847         __releases(&xhci->lock)
 848         __acquires(&xhci->lock)
 849 {
 850         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 851         u32 status = 0;
 852         int slot_id;
 853         struct xhci_hub *rhub;
 854         struct xhci_port *port;
 855
 856         rhub = xhci_get_rhub(hcd);
 857         port = rhub->ports[wIndex];
 858
 859         /* wPortChange bits */
 860         if (raw_port_status & PORT_CSC)
 861                 status |= USB_PORT_STAT_C_CONNECTION << 16;
 862         if (raw_port_status & PORT_PEC)
 863                 status |= USB_PORT_STAT_C_ENABLE << 16;
 864         if ((raw_port_status & PORT_OCC))
 865                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
 866         if ((raw_port_status & PORT_RC))
 867                 status |= USB_PORT_STAT_C_RESET << 16;
 868         /* USB3.0 only */
 869         if (hcd->speed >= HCD_USB3) {
 870                 /* Port link change with port in resume state should not be
 871                  * reported to usbcore, as this is an internal state to be
 872                  * handled by xhci driver. Reporting PLC to usbcore may
 873                  * cause usbcore clearing PLC first and port change event
 874                  * irq won't be generated.
 875                  */
 876                 if ((raw_port_status & PORT_PLC) &&
 877                         (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
 878                         status |= USB_PORT_STAT_C_LINK_STATE << 16;
 879                 if ((raw_port_status & PORT_WRC))
 880                         status |= USB_PORT_STAT_C_BH_RESET << 16;
 881                 if ((raw_port_status & PORT_CEC))
 882                         status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
 883
 884                 /* USB3 remote wake resume signaling completed */
 885                 if (bus_state->port_remote_wakeup & (1 << wIndex) &&
 886                     (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME &&
 887                     (raw_port_status & PORT_PLS_MASK) != XDEV_RECOVERY) {
 888                         bus_state->port_remote_wakeup &= ~(1 << wIndex);
 889                         usb_hcd_end_port_resume(&hcd->self, wIndex);
 890                 }
 891         }
 892
 893         if (hcd->speed < HCD_USB3) {
 894                 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
 895                                 && (raw_port_status & PORT_POWER))
 896                         status |= USB_PORT_STAT_SUSPEND;
 897         }
 898         if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
 899                 !DEV_SUPERSPEED_ANY(raw_port_status) && hcd->speed < HCD_USB3) {
 900                 if ((raw_port_status & PORT_RESET) ||
 901                                 !(raw_port_status & PORT_PE))
 902                         return 0xffffffff;
 903                 /* did port event handler already start resume timing? */
 904                 if (!bus_state->resume_done[wIndex]) {
 905                         /* If not, maybe we are in a host initated resume? */
 906                         if (test_bit(wIndex, &bus_state->resuming_ports)) {
 907                                 /* Host initated resume doesn't time the resume
 908                                  * signalling using resume_done[].
 909                                  * It manually sets RESUME state, sleeps 20ms
 910                                  * and sets U0 state. This should probably be
 911                                  * changed, but not right now.
 912                                  */
 913                         } else {
 914                                 /* port resume was discovered now and here,
 915                                  * start resume timing
 916                                  */
 917                                 unsigned long timeout = jiffies +
 918                                         msecs_to_jiffies(USB_RESUME_TIMEOUT);
 919
 920                                 set_bit(wIndex, &bus_state->resuming_ports);
 921                                 bus_state->resume_done[wIndex] = timeout;
 922                                 mod_timer(&hcd->rh_timer, timeout);
 923                                 usb_hcd_start_port_resume(&hcd->self, wIndex);
 924                         }
 925                 /* Has resume been signalled for USB_RESUME_TIME yet? */
 926                 } else if (time_after_eq(jiffies,
 927                                          bus_state->resume_done[wIndex])) {
 928                         int time_left;
 929
 930                         xhci_dbg(xhci, "Resume USB2 port %d\n",
 931                                         wIndex + 1);
 932                         bus_state->resume_done[wIndex] = 0;
 933                         clear_bit(wIndex, &bus_state->resuming_ports);
 934
 935                         set_bit(wIndex, &bus_state->rexit_ports);
 936
 937                         xhci_test_and_clear_bit(xhci, port, PORT_PLC);
 938                         xhci_set_link_state(xhci, port, XDEV_U0);
 939
 940                         spin_unlock_irqrestore(&xhci->lock, *flags);
 941                         time_left = wait_for_completion_timeout(
 942                                         &bus_state->rexit_done[wIndex],
 943                                         msecs_to_jiffies(
 944                                                 XHCI_MAX_REXIT_TIMEOUT_MS));
 945                         spin_lock_irqsave(&xhci->lock, *flags);
 946
 947                         if (time_left) {
 948                                 slot_id = xhci_find_slot_id_by_port(hcd,
 949                                                 xhci, wIndex + 1);
 950                                 if (!slot_id) {
 951                                         xhci_dbg(xhci, "slot_id is zero\n");
 952                                         return 0xffffffff;
 953                                 }
 954                                 xhci_ring_device(xhci, slot_id);
 955                         } else {
 956                                 int port_status = readl(port->addr);
 957                                 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
 958                                                 XHCI_MAX_REXIT_TIMEOUT_MS,
 959                                                 port_status);
 960                                 status |= USB_PORT_STAT_SUSPEND;
 961                                 clear_bit(wIndex, &bus_state->rexit_ports);
 962                         }
 963
 964                         usb_hcd_end_port_resume(&hcd->self, wIndex);
 965                         bus_state->port_c_suspend |= 1 << wIndex;
 966                         bus_state->suspended_ports &= ~(1 << wIndex);
 967                 } else {
 968                         /*
 969                          * The resume has been signaling for less than
 970                          * USB_RESUME_TIME. Report the port status as SUSPEND,
 971                          * let the usbcore check port status again and clear
 972                          * resume signaling later.
 973                          */
 974                         status |= USB_PORT_STAT_SUSPEND;
 975                 }
 976         }
 977         /*
 978          * Clear stale usb2 resume signalling variables in case port changed
 979          * state during resume signalling. For example on error
 980          */
 981         if ((bus_state->resume_done[wIndex] ||
 982              test_bit(wIndex, &bus_state->resuming_ports)) &&
 983             (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
 984             (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
 985                 bus_state->resume_done[wIndex] = 0;
 986                 clear_bit(wIndex, &bus_state->resuming_ports);
 987                 usb_hcd_end_port_resume(&hcd->self, wIndex);
 988         }
 989
 990
 991         if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
 992             (raw_port_status & PORT_POWER)) {
 993                 if (bus_state->suspended_ports & (1 << wIndex)) {
 994                         bus_state->suspended_ports &= ~(1 << wIndex);
 995                         if (hcd->speed < HCD_USB3)
 996                                 bus_state->port_c_suspend |= 1 << wIndex;
 997                 }
 998                 bus_state->resume_done[wIndex] = 0;
 999                 clear_bit(wIndex, &bus_state->resuming_ports);
1000         }
1001         if (raw_port_status & PORT_CONNECT) {
1002                 status |= USB_PORT_STAT_CONNECTION;
1003                 status |= xhci_port_speed(raw_port_status);
1004         }
1005         if (raw_port_status & PORT_PE)
1006                 status |= USB_PORT_STAT_ENABLE;
1007         if (raw_port_status & PORT_OC)
1008                 status |= USB_PORT_STAT_OVERCURRENT;
1009         if (raw_port_status & PORT_RESET)
1010                 status |= USB_PORT_STAT_RESET;
1011         if (raw_port_status & PORT_POWER) {
1012                 if (hcd->speed >= HCD_USB3)
1013                         status |= USB_SS_PORT_STAT_POWER;
1014                 else
1015                         status |= USB_PORT_STAT_POWER;
1016         }
1017         /* Update Port Link State */
1018         if (hcd->speed >= HCD_USB3) {
1019                 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
1020                 /*
1021                  * Verify if all USB3 Ports Have entered U0 already.
1022                  * Delete Compliance Mode Timer if so.
1023                  */
1024                 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
1025         } else {
1026                 xhci_hub_report_usb2_link_state(&status, raw_port_status);
1027         }
1028         if (bus_state->port_c_suspend & (1 << wIndex))
1029                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1030
1031         return status;
1032 }
1033
1034 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1035                 u16 wIndex, char *buf, u16 wLength)
1036 {
1037         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1038         int max_ports;
1039         unsigned long flags;
1040         u32 temp, status;
1041         int retval = 0;
1042         int slot_id;
1043         struct xhci_bus_state *bus_state;
1044         u16 link_state = 0;
1045         u16 wake_mask = 0;
1046         u16 timeout = 0;
1047         u16 test_mode = 0;
1048         struct xhci_hub *rhub;
1049         struct xhci_port **ports;
1050
1051         rhub = xhci_get_rhub(hcd);
1052         ports = rhub->ports;
1053         max_ports = rhub->num_ports;
1054         bus_state = &xhci->bus_state[hcd_index(hcd)];
1055
1056         spin_lock_irqsave(&xhci->lock, flags);
1057         switch (typeReq) {
1058         case GetHubStatus:
1059                 /* No power source, over-current reported per port */
1060                 memset(buf, 0, 4);
1061                 break;
1062         case GetHubDescriptor:
1063                 /* Check to make sure userspace is asking for the USB 3.0 hub
1064                  * descriptor for the USB 3.0 roothub.  If not, we stall the
1065                  * endpoint, like external hubs do.
1066                  */
1067                 if (hcd->speed >= HCD_USB3 &&
1068                                 (wLength < USB_DT_SS_HUB_SIZE ||
1069                                  wValue != (USB_DT_SS_HUB << 8))) {
1070                         xhci_dbg(xhci, "Wrong hub descriptor type for "
1071                                         "USB 3.0 roothub.\n");
1072                         goto error;
1073                 }
1074                 xhci_hub_descriptor(hcd, xhci,
1075                                 (struct usb_hub_descriptor *) buf);
1076                 break;
1077         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1078                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1079                         goto error;
1080
1081                 if (hcd->speed < HCD_USB3)
1082                         goto error;
1083
1084                 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
1085                 spin_unlock_irqrestore(&xhci->lock, flags);
1086                 return retval;
1087         case GetPortStatus:
1088                 if (!wIndex || wIndex > max_ports)
1089                         goto error;
1090                 wIndex--;
1091                 temp = readl(ports[wIndex]->addr);
1092                 if (temp == ~(u32)0) {
1093                         xhci_hc_died(xhci);
1094                         retval = -ENODEV;
1095                         break;
1096                 }
1097                 trace_xhci_get_port_status(wIndex, temp);
1098                 status = xhci_get_port_status(hcd, bus_state, wIndex, temp,
1099                                               &flags);
1100                 if (status == 0xffffffff)
1101                         goto error;
1102
1103                 xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n",
1104                                 wIndex, temp);
1105                 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
1106
1107                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1108                 /* if USB 3.1 extended port status return additional 4 bytes */
1109                 if (wValue == 0x02) {
1110                         u32 port_li;
1111
1112                         if (hcd->speed < HCD_USB31 || wLength != 8) {
1113                                 xhci_err(xhci, "get ext port status invalid parameter\n");
1114                                 retval = -EINVAL;
1115                                 break;
1116                         }
1117                         port_li = readl(ports[wIndex]->addr + PORTLI);
1118                         status = xhci_get_ext_port_status(temp, port_li);
1119                         put_unaligned_le32(status, &buf[4]);
1120                 }
1121                 break;
1122         case SetPortFeature:
1123                 if (wValue == USB_PORT_FEAT_LINK_STATE)
1124                         link_state = (wIndex & 0xff00) >> 3;
1125                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1126                         wake_mask = wIndex & 0xff00;
1127                 if (wValue == USB_PORT_FEAT_TEST)
1128                         test_mode = (wIndex & 0xff00) >> 8;
1129                 /* The MSB of wIndex is the U1/U2 timeout */
1130                 timeout = (wIndex & 0xff00) >> 8;
1131                 wIndex &= 0xff;
1132                 if (!wIndex || wIndex > max_ports)
1133                         goto error;
1134                 wIndex--;
1135                 temp = readl(ports[wIndex]->addr);
1136                 if (temp == ~(u32)0) {
1137                         xhci_hc_died(xhci);
1138                         retval = -ENODEV;
1139                         break;
1140                 }
1141                 temp = xhci_port_state_to_neutral(temp);
1142                 /* FIXME: What new port features do we need to support? */
1143                 switch (wValue) {
1144                 case USB_PORT_FEAT_SUSPEND:
1145                         temp = readl(ports[wIndex]->addr);
1146                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1147                                 /* Resume the port to U0 first */
1148                                 xhci_set_link_state(xhci, ports[wIndex],
1149                                                         XDEV_U0);
1150                                 spin_unlock_irqrestore(&xhci->lock, flags);
1151                                 msleep(10);
1152                                 spin_lock_irqsave(&xhci->lock, flags);
1153                         }
1154                         /* In spec software should not attempt to suspend
1155                          * a port unless the port reports that it is in the
1156                          * enabled (PED = ‘1’,PLS < ‘3’) state.
1157                          */
1158                         temp = readl(ports[wIndex]->addr);
1159                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1160                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1161                                 xhci_warn(xhci, "USB core suspending device not in U0/U1/U2.\n");
1162                                 goto error;
1163                         }
1164
1165                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1166                                         wIndex + 1);
1167                         if (!slot_id) {
1168                                 xhci_warn(xhci, "slot_id is zero\n");
1169                                 goto error;
1170                         }
1171                         /* unlock to execute stop endpoint commands */
1172                         spin_unlock_irqrestore(&xhci->lock, flags);
1173                         xhci_stop_device(xhci, slot_id, 1);
1174                         spin_lock_irqsave(&xhci->lock, flags);
1175
1176                         xhci_set_link_state(xhci, ports[wIndex], XDEV_U3);
1177
1178                         spin_unlock_irqrestore(&xhci->lock, flags);
1179                         msleep(10); /* wait device to enter */
1180                         spin_lock_irqsave(&xhci->lock, flags);
1181
1182                         temp = readl(ports[wIndex]->addr);
1183                         bus_state->suspended_ports |= 1 << wIndex;
1184                         break;
1185                 case USB_PORT_FEAT_LINK_STATE:
1186                         temp = readl(ports[wIndex]->addr);
1187                         /* Disable port */
1188                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1189                                 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1190                                 temp = xhci_port_state_to_neutral(temp);
1191                                 /*
1192                                  * Clear all change bits, so that we get a new
1193                                  * connection event.
1194                                  */
1195                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1196                                         PORT_OCC | PORT_RC | PORT_PLC |
1197                                         PORT_CEC;
1198                                 writel(temp | PORT_PE, ports[wIndex]->addr);
1199                                 temp = readl(ports[wIndex]->addr);
1200                                 break;
1201                         }
1202
1203                         /* Put link in RxDetect (enable port) */
1204                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1205                                 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1206                                 xhci_set_link_state(xhci, ports[wIndex],
1207                                                         link_state);
1208                                 temp = readl(ports[wIndex]->addr);
1209                                 break;
1210                         }
1211
1212                         /*
1213                          * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1214                          * root hub port's transition to compliance mode upon
1215                          * detecting LFPS timeout may be controlled by an
1216                          * Compliance Transition Enabled (CTE) flag (not
1217                          * software visible). This flag is set by writing 0xA
1218                          * to PORTSC PLS field which will allow transition to
1219                          * compliance mode the next time LFPS timeout is
1220                          * encountered. A warm reset will clear it.
1221                          *
1222                          * The CTE flag is only supported if the HCCPARAMS2 CTC
1223                          * flag is set, otherwise, the compliance substate is
1224                          * automatically entered as on 1.0 and prior.
1225                          */
1226                         if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1227                                 if (!HCC2_CTC(xhci->hcc_params2)) {
1228                                         xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1229                                         break;
1230                                 }
1231
1232                                 if ((temp & PORT_CONNECT)) {
1233                                         xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1234                                         goto error;
1235                                 }
1236
1237                                 xhci_dbg(xhci, "Enable compliance mode transition for port %d\n",
1238                                                 wIndex);
1239                                 xhci_set_link_state(xhci, ports[wIndex],
1240                                                 link_state);
1241
1242                                 temp = readl(ports[wIndex]->addr);
1243                                 break;
1244                         }
1245                         /* Port must be enabled */
1246                         if (!(temp & PORT_PE)) {
1247                                 retval = -ENODEV;
1248                                 break;
1249                         }
1250                         /* Can't set port link state above '3' (U3) */
1251                         if (link_state > USB_SS_PORT_LS_U3) {
1252                                 xhci_warn(xhci, "Cannot set port %d link state %d\n",
1253                                          wIndex, link_state);
1254                                 goto error;
1255                         }
1256                         if (link_state == USB_SS_PORT_LS_U3) {
1257                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1258                                                 wIndex + 1);
1259                                 if (slot_id) {
1260                                         /* unlock to execute stop endpoint
1261                                          * commands */
1262                                         spin_unlock_irqrestore(&xhci->lock,
1263                                                                 flags);
1264                                         xhci_stop_device(xhci, slot_id, 1);
1265                                         spin_lock_irqsave(&xhci->lock, flags);
1266                                 }
1267                         }
1268
1269                         xhci_set_link_state(xhci, ports[wIndex], link_state);
1270
1271                         spin_unlock_irqrestore(&xhci->lock, flags);
1272                         if (link_state == USB_SS_PORT_LS_U3) {
1273                                 int retries = 16;
1274
1275                                 while (retries--) {
1276                                         usleep_range(4000, 8000);
1277                                         temp = readl(ports[wIndex]->addr);
1278                                         if ((temp & PORT_PLS_MASK) == XDEV_U3)
1279                                                 break;
1280                                 }
1281                         }
1282                         spin_lock_irqsave(&xhci->lock, flags);
1283
1284                         temp = readl(ports[wIndex]->addr);
1285                         if (link_state == USB_SS_PORT_LS_U3)
1286                                 bus_state->suspended_ports |= 1 << wIndex;
1287                         break;
1288                 case USB_PORT_FEAT_POWER:
1289                         /*
1290                          * Turn on ports, even if there isn't per-port switching.
1291                          * HC will report connect events even before this is set.
1292                          * However, hub_wq will ignore the roothub events until
1293                          * the roothub is registered.
1294                          */
1295                         xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1296                         break;
1297                 case USB_PORT_FEAT_RESET:
1298                         temp = (temp | PORT_RESET);
1299                         writel(temp, ports[wIndex]->addr);
1300
1301                         temp = readl(ports[wIndex]->addr);
1302                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
1303                         break;
1304                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1305                         xhci_set_remote_wake_mask(xhci, ports[wIndex],
1306                                                   wake_mask);
1307                         temp = readl(ports[wIndex]->addr);
1308                         xhci_dbg(xhci, "set port remote wake mask, "
1309                                         "actual port %d status  = 0x%x\n",
1310                                         wIndex, temp);
1311                         break;
1312                 case USB_PORT_FEAT_BH_PORT_RESET:
1313                         temp |= PORT_WR;
1314                         writel(temp, ports[wIndex]->addr);
1315                         temp = readl(ports[wIndex]->addr);
1316                         break;
1317                 case USB_PORT_FEAT_U1_TIMEOUT:
1318                         if (hcd->speed < HCD_USB3)
1319                                 goto error;
1320                         temp = readl(ports[wIndex]->addr + PORTPMSC);
1321                         temp &= ~PORT_U1_TIMEOUT_MASK;
1322                         temp |= PORT_U1_TIMEOUT(timeout);
1323                         writel(temp, ports[wIndex]->addr + PORTPMSC);
1324                         break;
1325                 case USB_PORT_FEAT_U2_TIMEOUT:
1326                         if (hcd->speed < HCD_USB3)
1327                                 goto error;
1328                         temp = readl(ports[wIndex]->addr + PORTPMSC);
1329                         temp &= ~PORT_U2_TIMEOUT_MASK;
1330                         temp |= PORT_U2_TIMEOUT(timeout);
1331                         writel(temp, ports[wIndex]->addr + PORTPMSC);
1332                         break;
1333                 case USB_PORT_FEAT_TEST:
1334                         /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1335                         if (hcd->speed != HCD_USB2)
1336                                 goto error;
1337                         if (test_mode > TEST_FORCE_EN || test_mode < TEST_J)
1338                                 goto error;
1339                         retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1340                                                       &flags);
1341                         break;
1342                 default:
1343                         goto error;
1344                 }
1345                 /* unblock any posted writes */
1346                 temp = readl(ports[wIndex]->addr);
1347                 break;
1348         case ClearPortFeature:
1349                 if (!wIndex || wIndex > max_ports)
1350                         goto error;
1351                 wIndex--;
1352                 temp = readl(ports[wIndex]->addr);
1353                 if (temp == ~(u32)0) {
1354                         xhci_hc_died(xhci);
1355                         retval = -ENODEV;
1356                         break;
1357                 }
1358                 /* FIXME: What new port features do we need to support? */
1359                 temp = xhci_port_state_to_neutral(temp);
1360                 switch (wValue) {
1361                 case USB_PORT_FEAT_SUSPEND:
1362                         temp = readl(ports[wIndex]->addr);
1363                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1364                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
1365                         if (temp & PORT_RESET)
1366                                 goto error;
1367                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1368                                 if ((temp & PORT_PE) == 0)
1369                                         goto error;
1370
1371                                 set_bit(wIndex, &bus_state->resuming_ports);
1372                                 usb_hcd_start_port_resume(&hcd->self, wIndex);
1373                                 xhci_set_link_state(xhci, ports[wIndex],
1374                                                     XDEV_RESUME);
1375                                 spin_unlock_irqrestore(&xhci->lock, flags);
1376                                 msleep(USB_RESUME_TIMEOUT);
1377                                 spin_lock_irqsave(&xhci->lock, flags);
1378                                 xhci_set_link_state(xhci, ports[wIndex],
1379                                                         XDEV_U0);
1380                                 clear_bit(wIndex, &bus_state->resuming_ports);
1381                                 usb_hcd_end_port_resume(&hcd->self, wIndex);
1382                         }
1383                         bus_state->port_c_suspend |= 1 << wIndex;
1384
1385                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1386                                         wIndex + 1);
1387                         if (!slot_id) {
1388                                 xhci_dbg(xhci, "slot_id is zero\n");
1389                                 goto error;
1390                         }
1391                         xhci_ring_device(xhci, slot_id);
1392                         break;
1393                 case USB_PORT_FEAT_C_SUSPEND:
1394                         bus_state->port_c_suspend &= ~(1 << wIndex);
1395                         /* fall through */
1396                 case USB_PORT_FEAT_C_RESET:
1397                 case USB_PORT_FEAT_C_BH_PORT_RESET:
1398                 case USB_PORT_FEAT_C_CONNECTION:
1399                 case USB_PORT_FEAT_C_OVER_CURRENT:
1400                 case USB_PORT_FEAT_C_ENABLE:
1401                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1402                 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1403                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1404                                         ports[wIndex]->addr, temp);
1405                         break;
1406                 case USB_PORT_FEAT_ENABLE:
1407                         xhci_disable_port(hcd, xhci, wIndex,
1408                                         ports[wIndex]->addr, temp);
1409                         break;
1410                 case USB_PORT_FEAT_POWER:
1411                         xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1412                         break;
1413                 case USB_PORT_FEAT_TEST:
1414                         retval = xhci_exit_test_mode(xhci);
1415                         break;
1416                 default:
1417                         goto error;
1418                 }
1419                 break;
1420         default:
1421 error:
1422                 /* "stall" on error */
1423                 retval = -EPIPE;
1424         }
1425         spin_unlock_irqrestore(&xhci->lock, flags);
1426         return retval;
1427 }
1428
1429 /*
1430  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1431  * Ports are 0-indexed from the HCD point of view,
1432  * and 1-indexed from the USB core pointer of view.
1433  *
1434  * Note that the status change bits will be cleared as soon as a port status
1435  * change event is generated, so we use the saved status from that event.
1436  */
1437 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1438 {
1439         unsigned long flags;
1440         u32 temp, status;
1441         u32 mask;
1442         int i, retval;
1443         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1444         int max_ports;
1445         struct xhci_bus_state *bus_state;
1446         bool reset_change = false;
1447         struct xhci_hub *rhub;
1448         struct xhci_port **ports;
1449
1450         rhub = xhci_get_rhub(hcd);
1451         ports = rhub->ports;
1452         max_ports = rhub->num_ports;
1453         bus_state = &xhci->bus_state[hcd_index(hcd)];
1454
1455         /* Initial status is no changes */
1456         retval = (max_ports + 8) / 8;
1457         memset(buf, 0, retval);
1458
1459         /*
1460          * Inform the usbcore about resume-in-progress by returning
1461          * a non-zero value even if there are no status changes.
1462          */
1463         spin_lock_irqsave(&xhci->lock, flags);
1464
1465         status = bus_state->resuming_ports;
1466
1467         /*
1468          * SS devices are only visible to roothub after link training completes.
1469          * Keep polling roothubs for a grace period after xHC start
1470          */
1471         if (xhci->run_graceperiod) {
1472                 if (time_before(jiffies, xhci->run_graceperiod))
1473                         status = 1;
1474                 else
1475                         xhci->run_graceperiod = 0;
1476         }
1477
1478         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1479
1480         /* For each port, did anything change?  If so, set that bit in buf. */
1481         for (i = 0; i < max_ports; i++) {
1482                 temp = readl(ports[i]->addr);
1483                 if (temp == ~(u32)0) {
1484                         xhci_hc_died(xhci);
1485                         retval = -ENODEV;
1486                         break;
1487                 }
1488                 trace_xhci_hub_status_data(i, temp);
1489
1490                 if ((temp & mask) != 0 ||
1491                         (bus_state->port_c_suspend & 1 << i) ||
1492                         (bus_state->resume_done[i] && time_after_eq(
1493                             jiffies, bus_state->resume_done[i]))) {
1494                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1495                         status = 1;
1496                 }
1497                 if ((temp & PORT_RC))
1498                         reset_change = true;
1499                 if (temp & PORT_OC)
1500                         status = 1;
1501         }
1502         if (!status && !reset_change) {
1503                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1504                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1505         }
1506         spin_unlock_irqrestore(&xhci->lock, flags);
1507         return status ? retval : 0;
1508 }
1509
1510 #ifdef CONFIG_PM
1511
1512 int xhci_bus_suspend(struct usb_hcd *hcd)
1513 {
1514         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1515         int max_ports, port_index;
1516         struct xhci_bus_state *bus_state;
1517         unsigned long flags;
1518         struct xhci_hub *rhub;
1519         struct xhci_port **ports;
1520         u32 portsc_buf[USB_MAXCHILDREN];
1521         bool wake_enabled;
1522
1523         rhub = xhci_get_rhub(hcd);
1524         ports = rhub->ports;
1525         max_ports = rhub->num_ports;
1526         bus_state = &xhci->bus_state[hcd_index(hcd)];
1527         wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1528
1529         spin_lock_irqsave(&xhci->lock, flags);
1530
1531         if (wake_enabled) {
1532                 if (bus_state->resuming_ports ||        /* USB2 */
1533                     bus_state->port_remote_wakeup) {    /* USB3 */
1534                         spin_unlock_irqrestore(&xhci->lock, flags);
1535                         xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1536                         return -EBUSY;
1537                 }
1538         }
1539         /*
1540          * Prepare ports for suspend, but don't write anything before all ports
1541          * are checked and we know bus suspend can proceed
1542          */
1543         bus_state->bus_suspended = 0;
1544         port_index = max_ports;
1545         while (port_index--) {
1546                 u32 t1, t2;
1547                 int retries = 10;
1548 retry:
1549                 t1 = readl(ports[port_index]->addr);
1550                 t2 = xhci_port_state_to_neutral(t1);
1551                 portsc_buf[port_index] = 0;
1552
1553                 /*
1554                  * Give a USB3 port in link training time to finish, but don't
1555                  * prevent suspend as port might be stuck
1556                  */
1557                 if ((hcd->speed >= HCD_USB3) && retries-- &&
1558                     (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1559                         spin_unlock_irqrestore(&xhci->lock, flags);
1560                         msleep(XHCI_PORT_POLLING_LFPS_TIME);
1561                         spin_lock_irqsave(&xhci->lock, flags);
1562                         xhci_dbg(xhci, "port %d polling in bus suspend, waiting\n",
1563                                  port_index);
1564                         goto retry;
1565                 }
1566                 /* bail out if port detected a over-current condition */
1567                 if (t1 & PORT_OC) {
1568                         bus_state->bus_suspended = 0;
1569                         spin_unlock_irqrestore(&xhci->lock, flags);
1570                         xhci_dbg(xhci, "Bus suspend bailout, port over-current detected\n");
1571                         return -EBUSY;
1572                 }
1573                 /* suspend ports in U0, or bail out for new connect changes */
1574                 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1575                         if ((t1 & PORT_CSC) && wake_enabled) {
1576                                 bus_state->bus_suspended = 0;
1577                                 spin_unlock_irqrestore(&xhci->lock, flags);
1578                                 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1579                                 return -EBUSY;
1580                         }
1581                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1582                         t2 &= ~PORT_PLS_MASK;
1583                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1584                         set_bit(port_index, &bus_state->bus_suspended);
1585                 }
1586                 /* USB core sets remote wake mask for USB 3.0 hubs,
1587                  * including the USB 3.0 roothub, but only if CONFIG_PM
1588                  * is enabled, so also enable remote wake here.
1589                  */
1590                 if (wake_enabled) {
1591                         if (t1 & PORT_CONNECT) {
1592                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1593                                 t2 &= ~PORT_WKCONN_E;
1594                         } else {
1595                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1596                                 t2 &= ~PORT_WKDISC_E;
1597                         }
1598
1599                         if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1600                             (hcd->speed < HCD_USB3)) {
1601                                 if (usb_amd_pt_check_port(hcd->self.controller,
1602                                                           port_index))
1603                                         t2 &= ~PORT_WAKE_BITS;
1604                         }
1605                 } else
1606                         t2 &= ~PORT_WAKE_BITS;
1607
1608                 t1 = xhci_port_state_to_neutral(t1);
1609                 if (t1 != t2)
1610                         portsc_buf[port_index] = t2;
1611         }
1612
1613         /* write port settings, stopping and suspending ports if needed */
1614         port_index = max_ports;
1615         while (port_index--) {
1616                 if (!portsc_buf[port_index])
1617                         continue;
1618                 if (test_bit(port_index, &bus_state->bus_suspended)) {
1619                         int slot_id;
1620
1621                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1622                                                             port_index + 1);
1623                         if (slot_id) {
1624                                 spin_unlock_irqrestore(&xhci->lock, flags);
1625                                 xhci_stop_device(xhci, slot_id, 1);
1626                                 spin_lock_irqsave(&xhci->lock, flags);
1627                         }
1628                 }
1629                 writel(portsc_buf[port_index], ports[port_index]->addr);
1630         }
1631         hcd->state = HC_STATE_SUSPENDED;
1632         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1633         spin_unlock_irqrestore(&xhci->lock, flags);
1634
1635         if (bus_state->bus_suspended)
1636                 usleep_range(5000, 10000);
1637
1638         return 0;
1639 }
1640
1641 /*
1642  * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1643  * warm reset a USB3 device stuck in polling or compliance mode after resume.
1644  * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1645  */
1646 static bool xhci_port_missing_cas_quirk(struct xhci_port *port)
1647 {
1648         u32 portsc;
1649
1650         portsc = readl(port->addr);
1651
1652         /* if any of these are set we are not stuck */
1653         if (portsc & (PORT_CONNECT | PORT_CAS))
1654                 return false;
1655
1656         if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1657             ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1658                 return false;
1659
1660         /* clear wakeup/change bits, and do a warm port reset */
1661         portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1662         portsc |= PORT_WR;
1663         writel(portsc, port->addr);
1664         /* flush write */
1665         readl(port->addr);
1666         return true;
1667 }
1668
1669 int xhci_bus_resume(struct usb_hcd *hcd)
1670 {
1671         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1672         struct xhci_bus_state *bus_state;
1673         unsigned long flags;
1674         int max_ports, port_index;
1675         int slot_id;
1676         int sret;
1677         u32 next_state;
1678         u32 temp, portsc;
1679         struct xhci_hub *rhub;
1680         struct xhci_port **ports;
1681
1682         rhub = xhci_get_rhub(hcd);
1683         ports = rhub->ports;
1684         max_ports = rhub->num_ports;
1685         bus_state = &xhci->bus_state[hcd_index(hcd)];
1686
1687         if (time_before(jiffies, bus_state->next_statechange))
1688                 msleep(5);
1689
1690         spin_lock_irqsave(&xhci->lock, flags);
1691         if (!HCD_HW_ACCESSIBLE(hcd)) {
1692                 spin_unlock_irqrestore(&xhci->lock, flags);
1693                 return -ESHUTDOWN;
1694         }
1695
1696         /* delay the irqs */
1697         temp = readl(&xhci->op_regs->command);
1698         temp &= ~CMD_EIE;
1699         writel(temp, &xhci->op_regs->command);
1700
1701         /* bus specific resume for ports we suspended at bus_suspend */
1702         if (hcd->speed >= HCD_USB3)
1703                 next_state = XDEV_U0;
1704         else
1705                 next_state = XDEV_RESUME;
1706
1707         port_index = max_ports;
1708         while (port_index--) {
1709                 portsc = readl(ports[port_index]->addr);
1710
1711                 /* warm reset CAS limited ports stuck in polling/compliance */
1712                 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1713                     (hcd->speed >= HCD_USB3) &&
1714                     xhci_port_missing_cas_quirk(ports[port_index])) {
1715                         xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1716                         clear_bit(port_index, &bus_state->bus_suspended);
1717                         continue;
1718                 }
1719                 /* resume if we suspended the link, and it is still suspended */
1720                 if (test_bit(port_index, &bus_state->bus_suspended))
1721                         switch (portsc & PORT_PLS_MASK) {
1722                         case XDEV_U3:
1723                                 portsc = xhci_port_state_to_neutral(portsc);
1724                                 portsc &= ~PORT_PLS_MASK;
1725                                 portsc |= PORT_LINK_STROBE | next_state;
1726                                 break;
1727                         case XDEV_RESUME:
1728                                 /* resume already initiated */
1729                                 break;
1730                         default:
1731                                 /* not in a resumeable state, ignore it */
1732                                 clear_bit(port_index,
1733                                           &bus_state->bus_suspended);
1734                                 break;
1735                         }
1736                 /* disable wake for all ports, write new link state if needed */
1737                 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1738                 writel(portsc, ports[port_index]->addr);
1739         }
1740
1741         /* USB2 specific resume signaling delay and U0 link state transition */
1742         if (hcd->speed < HCD_USB3) {
1743                 if (bus_state->bus_suspended) {
1744                         spin_unlock_irqrestore(&xhci->lock, flags);
1745                         msleep(USB_RESUME_TIMEOUT);
1746                         spin_lock_irqsave(&xhci->lock, flags);
1747                 }
1748                 for_each_set_bit(port_index, &bus_state->bus_suspended,
1749                                  BITS_PER_LONG) {
1750                         /* Clear PLC to poll it later for U0 transition */
1751                         xhci_test_and_clear_bit(xhci, ports[port_index],
1752                                                 PORT_PLC);
1753                         xhci_set_link_state(xhci, ports[port_index], XDEV_U0);
1754                 }
1755         }
1756
1757         /* poll for U0 link state complete, both USB2 and USB3 */
1758         for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1759                 sret = xhci_handshake(ports[port_index]->addr, PORT_PLC,
1760                                       PORT_PLC, 10 * 1000);
1761                 if (sret) {
1762                         xhci_warn(xhci, "port %d resume PLC timeout\n",
1763                                   port_index);
1764                         continue;
1765                 }
1766                 xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC);
1767                 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1768                 if (slot_id)
1769                         xhci_ring_device(xhci, slot_id);
1770         }
1771         (void) readl(&xhci->op_regs->command);
1772
1773         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1774         /* re-enable irqs */
1775         temp = readl(&xhci->op_regs->command);
1776         temp |= CMD_EIE;
1777         writel(temp, &xhci->op_regs->command);
1778         temp = readl(&xhci->op_regs->command);
1779
1780         spin_unlock_irqrestore(&xhci->lock, flags);
1781         return 0;
1782 }
1783
1784 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd)
1785 {
1786         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1787         struct xhci_bus_state *bus_state;
1788
1789         bus_state = &xhci->bus_state[hcd_index(hcd)];
1790
1791         /* USB3 port wakeups are reported via usb_wakeup_notification() */
1792         return bus_state->resuming_ports;       /* USB2 ports only */
1793 }
1794
1795 #endif  /* CONFIG_PM */