git.itanic.dy.fi Git - linux-stable/blob - include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  68         MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
  69         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  70         MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
  71         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2       = 0x20,
  72         MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION       = 0x25,
  73 };
  74
  75 enum {
  76         MLX5_SHARED_RESOURCE_UID = 0xffff,
  77 };
  78
  79 enum {
  80         MLX5_OBJ_TYPE_SW_ICM = 0x0008,
  81 };
  82
  83 enum {
  84         MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
  85         MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
  86         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
  87         MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
  88 };
  89
  90 enum {
  91         MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
  92         MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
  93         MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
  94         MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
  95         MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
  96         MLX5_OBJ_TYPE_MKEY = 0xff01,
  97         MLX5_OBJ_TYPE_QP = 0xff02,
  98         MLX5_OBJ_TYPE_PSV = 0xff03,
  99         MLX5_OBJ_TYPE_RMP = 0xff04,
 100         MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
 101         MLX5_OBJ_TYPE_RQ = 0xff06,
 102         MLX5_OBJ_TYPE_SQ = 0xff07,
 103         MLX5_OBJ_TYPE_TIR = 0xff08,
 104         MLX5_OBJ_TYPE_TIS = 0xff09,
 105         MLX5_OBJ_TYPE_DCT = 0xff0a,
 106         MLX5_OBJ_TYPE_XRQ = 0xff0b,
 107         MLX5_OBJ_TYPE_RQT = 0xff0e,
 108         MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
 109         MLX5_OBJ_TYPE_CQ = 0xff10,
 110 };
 111
 112 enum {
 113         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
 114         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
 115         MLX5_CMD_OP_INIT_HCA                      = 0x102,
 116         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
 117         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
 118         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
 119         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
 120         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
 121         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
 122         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
 123         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 124         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 125         MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
 126         MLX5_CMD_OP_ALLOC_SF                      = 0x113,
 127         MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
 128         MLX5_CMD_OP_SUSPEND_VHCA                  = 0x115,
 129         MLX5_CMD_OP_RESUME_VHCA                   = 0x116,
 130         MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE    = 0x117,
 131         MLX5_CMD_OP_SAVE_VHCA_STATE               = 0x118,
 132         MLX5_CMD_OP_LOAD_VHCA_STATE               = 0x119,
 133         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 134         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 135         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 136         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 137         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 138         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 139         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 140         MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
 141         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 142         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 143         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 144         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 145         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 146         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 147         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 148         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 149         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 150         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 151         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 152         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 153         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 154         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 155         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 156         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 157         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 158         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 159         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 160         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 161         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 162         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 163         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 164         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 165         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 166         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 167         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 168         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 169         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 170         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 171         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 172         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 173         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 174         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 175         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 176         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 177         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 178         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 179         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 180         MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
 181         MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
 182         MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
 183         MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
 184         MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
 185         MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
 186         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 187         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 188         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 189         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 190         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 191         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 192         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 193         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 194         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 195         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 196         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 197         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 198         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 199         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 200         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 201         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 202         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 203         MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
 204         MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
 205         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 206         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 207         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 208         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 209         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 210         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 211         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 212         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 213         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 214         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 215         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 216         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 217         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 218         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 219         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 220         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 221         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 222         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 223         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 224         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 225         MLX5_CMD_OP_NOP                           = 0x80d,
 226         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 227         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 228         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 229         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 230         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 231         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 232         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 233         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 234         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 235         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 236         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 237         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 238         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 239         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 240         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 241         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 242         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 243         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 244         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 245         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 246         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 247         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 248         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 249         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 250         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 251         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 252         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 253         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 254         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 255         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 256         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 257         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 258         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 259         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 260         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 261         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 262         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 263         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 264         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 265         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 266         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 267         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 268         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 269         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 270         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 271         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 272         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 273         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 274         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 275         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 276         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 277         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 278         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 279         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 280         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 281         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 282         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 283         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 284         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 285         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 286         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 287         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 288         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 289         MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
 290         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 291         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 292         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 293         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 294         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 295         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 296         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 297         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 298         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 299         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 300         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 301         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 302         MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
 303         MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
 304         MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
 305         MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
 306         MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
 307         MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
 308         MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
 309         MLX5_CMD_OP_SYNC_CRYPTO                   = 0xb12,
 310         MLX5_CMD_OP_MAX
 311 };
 312
 313 /* Valid range for general commands that don't work over an object */
 314 enum {
 315         MLX5_CMD_OP_GENERAL_START = 0xb00,
 316         MLX5_CMD_OP_GENERAL_END = 0xd00,
 317 };
 318
 319 enum {
 320         MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0),
 321         MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1),
 322 };
 323
 324 struct mlx5_ifc_flow_table_fields_supported_bits {
 325         u8         outer_dmac[0x1];
 326         u8         outer_smac[0x1];
 327         u8         outer_ether_type[0x1];
 328         u8         outer_ip_version[0x1];
 329         u8         outer_first_prio[0x1];
 330         u8         outer_first_cfi[0x1];
 331         u8         outer_first_vid[0x1];
 332         u8         outer_ipv4_ttl[0x1];
 333         u8         outer_second_prio[0x1];
 334         u8         outer_second_cfi[0x1];
 335         u8         outer_second_vid[0x1];
 336         u8         reserved_at_b[0x1];
 337         u8         outer_sip[0x1];
 338         u8         outer_dip[0x1];
 339         u8         outer_frag[0x1];
 340         u8         outer_ip_protocol[0x1];
 341         u8         outer_ip_ecn[0x1];
 342         u8         outer_ip_dscp[0x1];
 343         u8         outer_udp_sport[0x1];
 344         u8         outer_udp_dport[0x1];
 345         u8         outer_tcp_sport[0x1];
 346         u8         outer_tcp_dport[0x1];
 347         u8         outer_tcp_flags[0x1];
 348         u8         outer_gre_protocol[0x1];
 349         u8         outer_gre_key[0x1];
 350         u8         outer_vxlan_vni[0x1];
 351         u8         outer_geneve_vni[0x1];
 352         u8         outer_geneve_oam[0x1];
 353         u8         outer_geneve_protocol_type[0x1];
 354         u8         outer_geneve_opt_len[0x1];
 355         u8         source_vhca_port[0x1];
 356         u8         source_eswitch_port[0x1];
 357
 358         u8         inner_dmac[0x1];
 359         u8         inner_smac[0x1];
 360         u8         inner_ether_type[0x1];
 361         u8         inner_ip_version[0x1];
 362         u8         inner_first_prio[0x1];
 363         u8         inner_first_cfi[0x1];
 364         u8         inner_first_vid[0x1];
 365         u8         reserved_at_27[0x1];
 366         u8         inner_second_prio[0x1];
 367         u8         inner_second_cfi[0x1];
 368         u8         inner_second_vid[0x1];
 369         u8         reserved_at_2b[0x1];
 370         u8         inner_sip[0x1];
 371         u8         inner_dip[0x1];
 372         u8         inner_frag[0x1];
 373         u8         inner_ip_protocol[0x1];
 374         u8         inner_ip_ecn[0x1];
 375         u8         inner_ip_dscp[0x1];
 376         u8         inner_udp_sport[0x1];
 377         u8         inner_udp_dport[0x1];
 378         u8         inner_tcp_sport[0x1];
 379         u8         inner_tcp_dport[0x1];
 380         u8         inner_tcp_flags[0x1];
 381         u8         reserved_at_37[0x9];
 382
 383         u8         geneve_tlv_option_0_data[0x1];
 384         u8         geneve_tlv_option_0_exist[0x1];
 385         u8         reserved_at_42[0x3];
 386         u8         outer_first_mpls_over_udp[0x4];
 387         u8         outer_first_mpls_over_gre[0x4];
 388         u8         inner_first_mpls[0x4];
 389         u8         outer_first_mpls[0x4];
 390         u8         reserved_at_55[0x2];
 391         u8         outer_esp_spi[0x1];
 392         u8         reserved_at_58[0x2];
 393         u8         bth_dst_qp[0x1];
 394         u8         reserved_at_5b[0x5];
 395
 396         u8         reserved_at_60[0x18];
 397         u8         metadata_reg_c_7[0x1];
 398         u8         metadata_reg_c_6[0x1];
 399         u8         metadata_reg_c_5[0x1];
 400         u8         metadata_reg_c_4[0x1];
 401         u8         metadata_reg_c_3[0x1];
 402         u8         metadata_reg_c_2[0x1];
 403         u8         metadata_reg_c_1[0x1];
 404         u8         metadata_reg_c_0[0x1];
 405 };
 406
 407 struct mlx5_ifc_flow_table_fields_supported_2_bits {
 408         u8         reserved_at_0[0xe];
 409         u8         bth_opcode[0x1];
 410         u8         reserved_at_f[0x11];
 411
 412         u8         reserved_at_20[0x60];
 413 };
 414
 415 struct mlx5_ifc_flow_table_prop_layout_bits {
 416         u8         ft_support[0x1];
 417         u8         reserved_at_1[0x1];
 418         u8         flow_counter[0x1];
 419         u8         flow_modify_en[0x1];
 420         u8         modify_root[0x1];
 421         u8         identified_miss_table_mode[0x1];
 422         u8         flow_table_modify[0x1];
 423         u8         reformat[0x1];
 424         u8         decap[0x1];
 425         u8         reserved_at_9[0x1];
 426         u8         pop_vlan[0x1];
 427         u8         push_vlan[0x1];
 428         u8         reserved_at_c[0x1];
 429         u8         pop_vlan_2[0x1];
 430         u8         push_vlan_2[0x1];
 431         u8         reformat_and_vlan_action[0x1];
 432         u8         reserved_at_10[0x1];
 433         u8         sw_owner[0x1];
 434         u8         reformat_l3_tunnel_to_l2[0x1];
 435         u8         reformat_l2_to_l3_tunnel[0x1];
 436         u8         reformat_and_modify_action[0x1];
 437         u8         ignore_flow_level[0x1];
 438         u8         reserved_at_16[0x1];
 439         u8         table_miss_action_domain[0x1];
 440         u8         termination_table[0x1];
 441         u8         reformat_and_fwd_to_table[0x1];
 442         u8         reserved_at_1a[0x2];
 443         u8         ipsec_encrypt[0x1];
 444         u8         ipsec_decrypt[0x1];
 445         u8         sw_owner_v2[0x1];
 446         u8         reserved_at_1f[0x1];
 447
 448         u8         termination_table_raw_traffic[0x1];
 449         u8         reserved_at_21[0x1];
 450         u8         log_max_ft_size[0x6];
 451         u8         log_max_modify_header_context[0x8];
 452         u8         max_modify_header_actions[0x8];
 453         u8         max_ft_level[0x8];
 454
 455         u8         reformat_add_esp_trasport[0x1];
 456         u8         reserved_at_41[0x2];
 457         u8         reformat_del_esp_trasport[0x1];
 458         u8         reserved_at_44[0x2];
 459         u8         execute_aso[0x1];
 460         u8         reserved_at_47[0x19];
 461
 462         u8         reserved_at_60[0x2];
 463         u8         reformat_insert[0x1];
 464         u8         reformat_remove[0x1];
 465         u8         macsec_encrypt[0x1];
 466         u8         macsec_decrypt[0x1];
 467         u8         reserved_at_66[0x2];
 468         u8         reformat_add_macsec[0x1];
 469         u8         reformat_remove_macsec[0x1];
 470         u8         reserved_at_6a[0xe];
 471         u8         log_max_ft_num[0x8];
 472
 473         u8         reserved_at_80[0x10];
 474         u8         log_max_flow_counter[0x8];
 475         u8         log_max_destination[0x8];
 476
 477         u8         reserved_at_a0[0x18];
 478         u8         log_max_flow[0x8];
 479
 480         u8         reserved_at_c0[0x40];
 481
 482         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 483
 484         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 485 };
 486
 487 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 488         u8         send[0x1];
 489         u8         receive[0x1];
 490         u8         write[0x1];
 491         u8         read[0x1];
 492         u8         atomic[0x1];
 493         u8         srq_receive[0x1];
 494         u8         reserved_at_6[0x1a];
 495 };
 496
 497 struct mlx5_ifc_ipv4_layout_bits {
 498         u8         reserved_at_0[0x60];
 499
 500         u8         ipv4[0x20];
 501 };
 502
 503 struct mlx5_ifc_ipv6_layout_bits {
 504         u8         ipv6[16][0x8];
 505 };
 506
 507 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 508         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 509         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 510         u8         reserved_at_0[0x80];
 511 };
 512
 513 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 514         u8         smac_47_16[0x20];
 515
 516         u8         smac_15_0[0x10];
 517         u8         ethertype[0x10];
 518
 519         u8         dmac_47_16[0x20];
 520
 521         u8         dmac_15_0[0x10];
 522         u8         first_prio[0x3];
 523         u8         first_cfi[0x1];
 524         u8         first_vid[0xc];
 525
 526         u8         ip_protocol[0x8];
 527         u8         ip_dscp[0x6];
 528         u8         ip_ecn[0x2];
 529         u8         cvlan_tag[0x1];
 530         u8         svlan_tag[0x1];
 531         u8         frag[0x1];
 532         u8         ip_version[0x4];
 533         u8         tcp_flags[0x9];
 534
 535         u8         tcp_sport[0x10];
 536         u8         tcp_dport[0x10];
 537
 538         u8         reserved_at_c0[0x10];
 539         u8         ipv4_ihl[0x4];
 540         u8         reserved_at_c4[0x4];
 541
 542         u8         ttl_hoplimit[0x8];
 543
 544         u8         udp_sport[0x10];
 545         u8         udp_dport[0x10];
 546
 547         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 548
 549         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 550 };
 551
 552 struct mlx5_ifc_nvgre_key_bits {
 553         u8 hi[0x18];
 554         u8 lo[0x8];
 555 };
 556
 557 union mlx5_ifc_gre_key_bits {
 558         struct mlx5_ifc_nvgre_key_bits nvgre;
 559         u8 key[0x20];
 560 };
 561
 562 struct mlx5_ifc_fte_match_set_misc_bits {
 563         u8         gre_c_present[0x1];
 564         u8         reserved_at_1[0x1];
 565         u8         gre_k_present[0x1];
 566         u8         gre_s_present[0x1];
 567         u8         source_vhca_port[0x4];
 568         u8         source_sqn[0x18];
 569
 570         u8         source_eswitch_owner_vhca_id[0x10];
 571         u8         source_port[0x10];
 572
 573         u8         outer_second_prio[0x3];
 574         u8         outer_second_cfi[0x1];
 575         u8         outer_second_vid[0xc];
 576         u8         inner_second_prio[0x3];
 577         u8         inner_second_cfi[0x1];
 578         u8         inner_second_vid[0xc];
 579
 580         u8         outer_second_cvlan_tag[0x1];
 581         u8         inner_second_cvlan_tag[0x1];
 582         u8         outer_second_svlan_tag[0x1];
 583         u8         inner_second_svlan_tag[0x1];
 584         u8         reserved_at_64[0xc];
 585         u8         gre_protocol[0x10];
 586
 587         union mlx5_ifc_gre_key_bits gre_key;
 588
 589         u8         vxlan_vni[0x18];
 590         u8         bth_opcode[0x8];
 591
 592         u8         geneve_vni[0x18];
 593         u8         reserved_at_d8[0x6];
 594         u8         geneve_tlv_option_0_exist[0x1];
 595         u8         geneve_oam[0x1];
 596
 597         u8         reserved_at_e0[0xc];
 598         u8         outer_ipv6_flow_label[0x14];
 599
 600         u8         reserved_at_100[0xc];
 601         u8         inner_ipv6_flow_label[0x14];
 602
 603         u8         reserved_at_120[0xa];
 604         u8         geneve_opt_len[0x6];
 605         u8         geneve_protocol_type[0x10];
 606
 607         u8         reserved_at_140[0x8];
 608         u8         bth_dst_qp[0x18];
 609         u8         reserved_at_160[0x20];
 610         u8         outer_esp_spi[0x20];
 611         u8         reserved_at_1a0[0x60];
 612 };
 613
 614 struct mlx5_ifc_fte_match_mpls_bits {
 615         u8         mpls_label[0x14];
 616         u8         mpls_exp[0x3];
 617         u8         mpls_s_bos[0x1];
 618         u8         mpls_ttl[0x8];
 619 };
 620
 621 struct mlx5_ifc_fte_match_set_misc2_bits {
 622         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 623
 624         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 625
 626         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 627
 628         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 629
 630         u8         metadata_reg_c_7[0x20];
 631
 632         u8         metadata_reg_c_6[0x20];
 633
 634         u8         metadata_reg_c_5[0x20];
 635
 636         u8         metadata_reg_c_4[0x20];
 637
 638         u8         metadata_reg_c_3[0x20];
 639
 640         u8         metadata_reg_c_2[0x20];
 641
 642         u8         metadata_reg_c_1[0x20];
 643
 644         u8         metadata_reg_c_0[0x20];
 645
 646         u8         metadata_reg_a[0x20];
 647
 648         u8         reserved_at_1a0[0x8];
 649
 650         u8         macsec_syndrome[0x8];
 651         u8         ipsec_syndrome[0x8];
 652         u8         reserved_at_1b8[0x8];
 653
 654         u8         reserved_at_1c0[0x40];
 655 };
 656
 657 struct mlx5_ifc_fte_match_set_misc3_bits {
 658         u8         inner_tcp_seq_num[0x20];
 659
 660         u8         outer_tcp_seq_num[0x20];
 661
 662         u8         inner_tcp_ack_num[0x20];
 663
 664         u8         outer_tcp_ack_num[0x20];
 665
 666         u8         reserved_at_80[0x8];
 667         u8         outer_vxlan_gpe_vni[0x18];
 668
 669         u8         outer_vxlan_gpe_next_protocol[0x8];
 670         u8         outer_vxlan_gpe_flags[0x8];
 671         u8         reserved_at_b0[0x10];
 672
 673         u8         icmp_header_data[0x20];
 674
 675         u8         icmpv6_header_data[0x20];
 676
 677         u8         icmp_type[0x8];
 678         u8         icmp_code[0x8];
 679         u8         icmpv6_type[0x8];
 680         u8         icmpv6_code[0x8];
 681
 682         u8         geneve_tlv_option_0_data[0x20];
 683
 684         u8         gtpu_teid[0x20];
 685
 686         u8         gtpu_msg_type[0x8];
 687         u8         gtpu_msg_flags[0x8];
 688         u8         reserved_at_170[0x10];
 689
 690         u8         gtpu_dw_2[0x20];
 691
 692         u8         gtpu_first_ext_dw_0[0x20];
 693
 694         u8         gtpu_dw_0[0x20];
 695
 696         u8         reserved_at_1e0[0x20];
 697 };
 698
 699 struct mlx5_ifc_fte_match_set_misc4_bits {
 700         u8         prog_sample_field_value_0[0x20];
 701
 702         u8         prog_sample_field_id_0[0x20];
 703
 704         u8         prog_sample_field_value_1[0x20];
 705
 706         u8         prog_sample_field_id_1[0x20];
 707
 708         u8         prog_sample_field_value_2[0x20];
 709
 710         u8         prog_sample_field_id_2[0x20];
 711
 712         u8         prog_sample_field_value_3[0x20];
 713
 714         u8         prog_sample_field_id_3[0x20];
 715
 716         u8         reserved_at_100[0x100];
 717 };
 718
 719 struct mlx5_ifc_fte_match_set_misc5_bits {
 720         u8         macsec_tag_0[0x20];
 721
 722         u8         macsec_tag_1[0x20];
 723
 724         u8         macsec_tag_2[0x20];
 725
 726         u8         macsec_tag_3[0x20];
 727
 728         u8         tunnel_header_0[0x20];
 729
 730         u8         tunnel_header_1[0x20];
 731
 732         u8         tunnel_header_2[0x20];
 733
 734         u8         tunnel_header_3[0x20];
 735
 736         u8         reserved_at_100[0x100];
 737 };
 738
 739 struct mlx5_ifc_cmd_pas_bits {
 740         u8         pa_h[0x20];
 741
 742         u8         pa_l[0x14];
 743         u8         reserved_at_34[0xc];
 744 };
 745
 746 struct mlx5_ifc_uint64_bits {
 747         u8         hi[0x20];
 748
 749         u8         lo[0x20];
 750 };
 751
 752 enum {
 753         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 754         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 755         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 756         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 757         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 758         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 759         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 760         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 761         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 762         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 763 };
 764
 765 struct mlx5_ifc_ads_bits {
 766         u8         fl[0x1];
 767         u8         free_ar[0x1];
 768         u8         reserved_at_2[0xe];
 769         u8         pkey_index[0x10];
 770
 771         u8         reserved_at_20[0x8];
 772         u8         grh[0x1];
 773         u8         mlid[0x7];
 774         u8         rlid[0x10];
 775
 776         u8         ack_timeout[0x5];
 777         u8         reserved_at_45[0x3];
 778         u8         src_addr_index[0x8];
 779         u8         reserved_at_50[0x4];
 780         u8         stat_rate[0x4];
 781         u8         hop_limit[0x8];
 782
 783         u8         reserved_at_60[0x4];
 784         u8         tclass[0x8];
 785         u8         flow_label[0x14];
 786
 787         u8         rgid_rip[16][0x8];
 788
 789         u8         reserved_at_100[0x4];
 790         u8         f_dscp[0x1];
 791         u8         f_ecn[0x1];
 792         u8         reserved_at_106[0x1];
 793         u8         f_eth_prio[0x1];
 794         u8         ecn[0x2];
 795         u8         dscp[0x6];
 796         u8         udp_sport[0x10];
 797
 798         u8         dei_cfi[0x1];
 799         u8         eth_prio[0x3];
 800         u8         sl[0x4];
 801         u8         vhca_port_num[0x8];
 802         u8         rmac_47_32[0x10];
 803
 804         u8         rmac_31_0[0x20];
 805 };
 806
 807 struct mlx5_ifc_flow_table_nic_cap_bits {
 808         u8         nic_rx_multi_path_tirs[0x1];
 809         u8         nic_rx_multi_path_tirs_fts[0x1];
 810         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 811         u8         reserved_at_3[0x4];
 812         u8         sw_owner_reformat_supported[0x1];
 813         u8         reserved_at_8[0x18];
 814
 815         u8         encap_general_header[0x1];
 816         u8         reserved_at_21[0xa];
 817         u8         log_max_packet_reformat_context[0x5];
 818         u8         reserved_at_30[0x6];
 819         u8         max_encap_header_size[0xa];
 820         u8         reserved_at_40[0x1c0];
 821
 822         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 823
 824         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 825
 826         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 827
 828         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 829
 830         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
 831
 832         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 833
 834         u8         reserved_at_e00[0x700];
 835
 836         struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
 837
 838         u8         reserved_at_1580[0x280];
 839
 840         struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
 841
 842         u8         reserved_at_1880[0x780];
 843
 844         u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
 845
 846         u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
 847
 848         u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
 849
 850         u8         reserved_at_20c0[0x5f40];
 851 };
 852
 853 struct mlx5_ifc_port_selection_cap_bits {
 854         u8         reserved_at_0[0x10];
 855         u8         port_select_flow_table[0x1];
 856         u8         reserved_at_11[0x1];
 857         u8         port_select_flow_table_bypass[0x1];
 858         u8         reserved_at_13[0xd];
 859
 860         u8         reserved_at_20[0x1e0];
 861
 862         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
 863
 864         u8         reserved_at_400[0x7c00];
 865 };
 866
 867 enum {
 868         MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
 869         MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
 870         MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
 871         MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
 872         MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
 873         MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
 874         MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
 875         MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
 876 };
 877
 878 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 879         u8      fdb_to_vport_reg_c_id[0x8];
 880         u8      reserved_at_8[0xd];
 881         u8      fdb_modify_header_fwd_to_table[0x1];
 882         u8      fdb_ipv4_ttl_modify[0x1];
 883         u8      flow_source[0x1];
 884         u8      reserved_at_18[0x2];
 885         u8      multi_fdb_encap[0x1];
 886         u8      egress_acl_forward_to_vport[0x1];
 887         u8      fdb_multi_path_to_table[0x1];
 888         u8      reserved_at_1d[0x3];
 889
 890         u8      reserved_at_20[0x1e0];
 891
 892         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 893
 894         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 895
 896         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 897
 898         u8      reserved_at_800[0x1000];
 899
 900         u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
 901
 902         u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
 903
 904         u8      sw_steering_uplink_icm_address_rx[0x40];
 905
 906         u8      sw_steering_uplink_icm_address_tx[0x40];
 907
 908         u8      reserved_at_1900[0x6700];
 909 };
 910
 911 enum {
 912         MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
 913         MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
 914 };
 915
 916 struct mlx5_ifc_e_switch_cap_bits {
 917         u8         vport_svlan_strip[0x1];
 918         u8         vport_cvlan_strip[0x1];
 919         u8         vport_svlan_insert[0x1];
 920         u8         vport_cvlan_insert_if_not_exist[0x1];
 921         u8         vport_cvlan_insert_overwrite[0x1];
 922         u8         reserved_at_5[0x1];
 923         u8         vport_cvlan_insert_always[0x1];
 924         u8         esw_shared_ingress_acl[0x1];
 925         u8         esw_uplink_ingress_acl[0x1];
 926         u8         root_ft_on_other_esw[0x1];
 927         u8         reserved_at_a[0xf];
 928         u8         esw_functions_changed[0x1];
 929         u8         reserved_at_1a[0x1];
 930         u8         ecpf_vport_exists[0x1];
 931         u8         counter_eswitch_affinity[0x1];
 932         u8         merged_eswitch[0x1];
 933         u8         nic_vport_node_guid_modify[0x1];
 934         u8         nic_vport_port_guid_modify[0x1];
 935
 936         u8         vxlan_encap_decap[0x1];
 937         u8         nvgre_encap_decap[0x1];
 938         u8         reserved_at_22[0x1];
 939         u8         log_max_fdb_encap_uplink[0x5];
 940         u8         reserved_at_21[0x3];
 941         u8         log_max_packet_reformat_context[0x5];
 942         u8         reserved_2b[0x6];
 943         u8         max_encap_header_size[0xa];
 944
 945         u8         reserved_at_40[0xb];
 946         u8         log_max_esw_sf[0x5];
 947         u8         esw_sf_base_id[0x10];
 948
 949         u8         reserved_at_60[0x7a0];
 950
 951 };
 952
 953 struct mlx5_ifc_qos_cap_bits {
 954         u8         packet_pacing[0x1];
 955         u8         esw_scheduling[0x1];
 956         u8         esw_bw_share[0x1];
 957         u8         esw_rate_limit[0x1];
 958         u8         reserved_at_4[0x1];
 959         u8         packet_pacing_burst_bound[0x1];
 960         u8         packet_pacing_typical_size[0x1];
 961         u8         reserved_at_7[0x1];
 962         u8         nic_sq_scheduling[0x1];
 963         u8         nic_bw_share[0x1];
 964         u8         nic_rate_limit[0x1];
 965         u8         packet_pacing_uid[0x1];
 966         u8         log_esw_max_sched_depth[0x4];
 967         u8         reserved_at_10[0x10];
 968
 969         u8         reserved_at_20[0xb];
 970         u8         log_max_qos_nic_queue_group[0x5];
 971         u8         reserved_at_30[0x10];
 972
 973         u8         packet_pacing_max_rate[0x20];
 974
 975         u8         packet_pacing_min_rate[0x20];
 976
 977         u8         reserved_at_80[0x10];
 978         u8         packet_pacing_rate_table_size[0x10];
 979
 980         u8         esw_element_type[0x10];
 981         u8         esw_tsar_type[0x10];
 982
 983         u8         reserved_at_c0[0x10];
 984         u8         max_qos_para_vport[0x10];
 985
 986         u8         max_tsar_bw_share[0x20];
 987
 988         u8         reserved_at_100[0x20];
 989
 990         u8         reserved_at_120[0x3];
 991         u8         log_meter_aso_granularity[0x5];
 992         u8         reserved_at_128[0x3];
 993         u8         log_meter_aso_max_alloc[0x5];
 994         u8         reserved_at_130[0x3];
 995         u8         log_max_num_meter_aso[0x5];
 996         u8         reserved_at_138[0x8];
 997
 998         u8         reserved_at_140[0x6c0];
 999 };
1000
1001 struct mlx5_ifc_debug_cap_bits {
1002         u8         core_dump_general[0x1];
1003         u8         core_dump_qp[0x1];
1004         u8         reserved_at_2[0x7];
1005         u8         resource_dump[0x1];
1006         u8         reserved_at_a[0x16];
1007
1008         u8         reserved_at_20[0x2];
1009         u8         stall_detect[0x1];
1010         u8         reserved_at_23[0x1d];
1011
1012         u8         reserved_at_40[0x7c0];
1013 };
1014
1015 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1016         u8         csum_cap[0x1];
1017         u8         vlan_cap[0x1];
1018         u8         lro_cap[0x1];
1019         u8         lro_psh_flag[0x1];
1020         u8         lro_time_stamp[0x1];
1021         u8         reserved_at_5[0x2];
1022         u8         wqe_vlan_insert[0x1];
1023         u8         self_lb_en_modifiable[0x1];
1024         u8         reserved_at_9[0x2];
1025         u8         max_lso_cap[0x5];
1026         u8         multi_pkt_send_wqe[0x2];
1027         u8         wqe_inline_mode[0x2];
1028         u8         rss_ind_tbl_cap[0x4];
1029         u8         reg_umr_sq[0x1];
1030         u8         scatter_fcs[0x1];
1031         u8         enhanced_multi_pkt_send_wqe[0x1];
1032         u8         tunnel_lso_const_out_ip_id[0x1];
1033         u8         tunnel_lro_gre[0x1];
1034         u8         tunnel_lro_vxlan[0x1];
1035         u8         tunnel_stateless_gre[0x1];
1036         u8         tunnel_stateless_vxlan[0x1];
1037
1038         u8         swp[0x1];
1039         u8         swp_csum[0x1];
1040         u8         swp_lso[0x1];
1041         u8         cqe_checksum_full[0x1];
1042         u8         tunnel_stateless_geneve_tx[0x1];
1043         u8         tunnel_stateless_mpls_over_udp[0x1];
1044         u8         tunnel_stateless_mpls_over_gre[0x1];
1045         u8         tunnel_stateless_vxlan_gpe[0x1];
1046         u8         tunnel_stateless_ipv4_over_vxlan[0x1];
1047         u8         tunnel_stateless_ip_over_ip[0x1];
1048         u8         insert_trailer[0x1];
1049         u8         reserved_at_2b[0x1];
1050         u8         tunnel_stateless_ip_over_ip_rx[0x1];
1051         u8         tunnel_stateless_ip_over_ip_tx[0x1];
1052         u8         reserved_at_2e[0x2];
1053         u8         max_vxlan_udp_ports[0x8];
1054         u8         reserved_at_38[0x6];
1055         u8         max_geneve_opt_len[0x1];
1056         u8         tunnel_stateless_geneve_rx[0x1];
1057
1058         u8         reserved_at_40[0x10];
1059         u8         lro_min_mss_size[0x10];
1060
1061         u8         reserved_at_60[0x120];
1062
1063         u8         lro_timer_supported_periods[4][0x20];
1064
1065         u8         reserved_at_200[0x600];
1066 };
1067
1068 enum {
1069         MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1070         MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1071         MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1072 };
1073
1074 struct mlx5_ifc_roce_cap_bits {
1075         u8         roce_apm[0x1];
1076         u8         reserved_at_1[0x3];
1077         u8         sw_r_roce_src_udp_port[0x1];
1078         u8         fl_rc_qp_when_roce_disabled[0x1];
1079         u8         fl_rc_qp_when_roce_enabled[0x1];
1080         u8         reserved_at_7[0x17];
1081         u8         qp_ts_format[0x2];
1082
1083         u8         reserved_at_20[0x60];
1084
1085         u8         reserved_at_80[0xc];
1086         u8         l3_type[0x4];
1087         u8         reserved_at_90[0x8];
1088         u8         roce_version[0x8];
1089
1090         u8         reserved_at_a0[0x10];
1091         u8         r_roce_dest_udp_port[0x10];
1092
1093         u8         r_roce_max_src_udp_port[0x10];
1094         u8         r_roce_min_src_udp_port[0x10];
1095
1096         u8         reserved_at_e0[0x10];
1097         u8         roce_address_table_size[0x10];
1098
1099         u8         reserved_at_100[0x700];
1100 };
1101
1102 struct mlx5_ifc_sync_steering_in_bits {
1103         u8         opcode[0x10];
1104         u8         uid[0x10];
1105
1106         u8         reserved_at_20[0x10];
1107         u8         op_mod[0x10];
1108
1109         u8         reserved_at_40[0xc0];
1110 };
1111
1112 struct mlx5_ifc_sync_steering_out_bits {
1113         u8         status[0x8];
1114         u8         reserved_at_8[0x18];
1115
1116         u8         syndrome[0x20];
1117
1118         u8         reserved_at_40[0x40];
1119 };
1120
1121 struct mlx5_ifc_sync_crypto_in_bits {
1122         u8         opcode[0x10];
1123         u8         uid[0x10];
1124
1125         u8         reserved_at_20[0x10];
1126         u8         op_mod[0x10];
1127
1128         u8         reserved_at_40[0x20];
1129
1130         u8         reserved_at_60[0x10];
1131         u8         crypto_type[0x10];
1132
1133         u8         reserved_at_80[0x80];
1134 };
1135
1136 struct mlx5_ifc_sync_crypto_out_bits {
1137         u8         status[0x8];
1138         u8         reserved_at_8[0x18];
1139
1140         u8         syndrome[0x20];
1141
1142         u8         reserved_at_40[0x40];
1143 };
1144
1145 struct mlx5_ifc_device_mem_cap_bits {
1146         u8         memic[0x1];
1147         u8         reserved_at_1[0x1f];
1148
1149         u8         reserved_at_20[0xb];
1150         u8         log_min_memic_alloc_size[0x5];
1151         u8         reserved_at_30[0x8];
1152         u8         log_max_memic_addr_alignment[0x8];
1153
1154         u8         memic_bar_start_addr[0x40];
1155
1156         u8         memic_bar_size[0x20];
1157
1158         u8         max_memic_size[0x20];
1159
1160         u8         steering_sw_icm_start_address[0x40];
1161
1162         u8         reserved_at_100[0x8];
1163         u8         log_header_modify_sw_icm_size[0x8];
1164         u8         reserved_at_110[0x2];
1165         u8         log_sw_icm_alloc_granularity[0x6];
1166         u8         log_steering_sw_icm_size[0x8];
1167
1168         u8         reserved_at_120[0x18];
1169         u8         log_header_modify_pattern_sw_icm_size[0x8];
1170
1171         u8         header_modify_sw_icm_start_address[0x40];
1172
1173         u8         reserved_at_180[0x40];
1174
1175         u8         header_modify_pattern_sw_icm_start_address[0x40];
1176
1177         u8         memic_operations[0x20];
1178
1179         u8         reserved_at_220[0x5e0];
1180 };
1181
1182 struct mlx5_ifc_device_event_cap_bits {
1183         u8         user_affiliated_events[4][0x40];
1184
1185         u8         user_unaffiliated_events[4][0x40];
1186 };
1187
1188 struct mlx5_ifc_virtio_emulation_cap_bits {
1189         u8         desc_tunnel_offload_type[0x1];
1190         u8         eth_frame_offload_type[0x1];
1191         u8         virtio_version_1_0[0x1];
1192         u8         device_features_bits_mask[0xd];
1193         u8         event_mode[0x8];
1194         u8         virtio_queue_type[0x8];
1195
1196         u8         max_tunnel_desc[0x10];
1197         u8         reserved_at_30[0x3];
1198         u8         log_doorbell_stride[0x5];
1199         u8         reserved_at_38[0x3];
1200         u8         log_doorbell_bar_size[0x5];
1201
1202         u8         doorbell_bar_offset[0x40];
1203
1204         u8         max_emulated_devices[0x8];
1205         u8         max_num_virtio_queues[0x18];
1206
1207         u8         reserved_at_a0[0x60];
1208
1209         u8         umem_1_buffer_param_a[0x20];
1210
1211         u8         umem_1_buffer_param_b[0x20];
1212
1213         u8         umem_2_buffer_param_a[0x20];
1214
1215         u8         umem_2_buffer_param_b[0x20];
1216
1217         u8         umem_3_buffer_param_a[0x20];
1218
1219         u8         umem_3_buffer_param_b[0x20];
1220
1221         u8         reserved_at_1c0[0x640];
1222 };
1223
1224 enum {
1225         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1226         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1227         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1228         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1229         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1230         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1231         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1232         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1233         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1234 };
1235
1236 enum {
1237         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1238         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1239         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1240         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1241         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1242         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1243         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1244         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1245         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1246 };
1247
1248 struct mlx5_ifc_atomic_caps_bits {
1249         u8         reserved_at_0[0x40];
1250
1251         u8         atomic_req_8B_endianness_mode[0x2];
1252         u8         reserved_at_42[0x4];
1253         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1254
1255         u8         reserved_at_47[0x19];
1256
1257         u8         reserved_at_60[0x20];
1258
1259         u8         reserved_at_80[0x10];
1260         u8         atomic_operations[0x10];
1261
1262         u8         reserved_at_a0[0x10];
1263         u8         atomic_size_qp[0x10];
1264
1265         u8         reserved_at_c0[0x10];
1266         u8         atomic_size_dc[0x10];
1267
1268         u8         reserved_at_e0[0x720];
1269 };
1270
1271 struct mlx5_ifc_odp_cap_bits {
1272         u8         reserved_at_0[0x40];
1273
1274         u8         sig[0x1];
1275         u8         reserved_at_41[0x1f];
1276
1277         u8         reserved_at_60[0x20];
1278
1279         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1280
1281         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1282
1283         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1284
1285         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1286
1287         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1288
1289         u8         reserved_at_120[0x6E0];
1290 };
1291
1292 struct mlx5_ifc_calc_op {
1293         u8        reserved_at_0[0x10];
1294         u8        reserved_at_10[0x9];
1295         u8        op_swap_endianness[0x1];
1296         u8        op_min[0x1];
1297         u8        op_xor[0x1];
1298         u8        op_or[0x1];
1299         u8        op_and[0x1];
1300         u8        op_max[0x1];
1301         u8        op_add[0x1];
1302 };
1303
1304 struct mlx5_ifc_vector_calc_cap_bits {
1305         u8         calc_matrix[0x1];
1306         u8         reserved_at_1[0x1f];
1307         u8         reserved_at_20[0x8];
1308         u8         max_vec_count[0x8];
1309         u8         reserved_at_30[0xd];
1310         u8         max_chunk_size[0x3];
1311         struct mlx5_ifc_calc_op calc0;
1312         struct mlx5_ifc_calc_op calc1;
1313         struct mlx5_ifc_calc_op calc2;
1314         struct mlx5_ifc_calc_op calc3;
1315
1316         u8         reserved_at_c0[0x720];
1317 };
1318
1319 struct mlx5_ifc_tls_cap_bits {
1320         u8         tls_1_2_aes_gcm_128[0x1];
1321         u8         tls_1_3_aes_gcm_128[0x1];
1322         u8         tls_1_2_aes_gcm_256[0x1];
1323         u8         tls_1_3_aes_gcm_256[0x1];
1324         u8         reserved_at_4[0x1c];
1325
1326         u8         reserved_at_20[0x7e0];
1327 };
1328
1329 struct mlx5_ifc_ipsec_cap_bits {
1330         u8         ipsec_full_offload[0x1];
1331         u8         ipsec_crypto_offload[0x1];
1332         u8         ipsec_esn[0x1];
1333         u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1334         u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1335         u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1336         u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1337         u8         reserved_at_7[0x4];
1338         u8         log_max_ipsec_offload[0x5];
1339         u8         reserved_at_10[0x10];
1340
1341         u8         min_log_ipsec_full_replay_window[0x8];
1342         u8         max_log_ipsec_full_replay_window[0x8];
1343         u8         reserved_at_30[0x7d0];
1344 };
1345
1346 struct mlx5_ifc_macsec_cap_bits {
1347         u8    macsec_epn[0x1];
1348         u8    reserved_at_1[0x2];
1349         u8    macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1350         u8    macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1351         u8    macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1352         u8    macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1353         u8    reserved_at_7[0x4];
1354         u8    log_max_macsec_offload[0x5];
1355         u8    reserved_at_10[0x10];
1356
1357         u8    min_log_macsec_full_replay_window[0x8];
1358         u8    max_log_macsec_full_replay_window[0x8];
1359         u8    reserved_at_30[0x10];
1360
1361         u8    reserved_at_40[0x7c0];
1362 };
1363
1364 enum {
1365         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1366         MLX5_WQ_TYPE_CYCLIC       = 0x1,
1367         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1368         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1369 };
1370
1371 enum {
1372         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1373         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1374 };
1375
1376 enum {
1377         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1378         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1379         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1380         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1381         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1382 };
1383
1384 enum {
1385         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1386         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1387         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1388         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1389         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1390         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1391 };
1392
1393 enum {
1394         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1395         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1396 };
1397
1398 enum {
1399         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1400         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1401         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1402 };
1403
1404 enum {
1405         MLX5_CAP_PORT_TYPE_IB  = 0x0,
1406         MLX5_CAP_PORT_TYPE_ETH = 0x1,
1407 };
1408
1409 enum {
1410         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
1411         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
1412         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
1413 };
1414
1415 enum {
1416         MLX5_FLEX_PARSER_GENEVE_ENABLED         = 1 << 3,
1417         MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED  = 1 << 4,
1418         MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED  = 1 << 5,
1419         MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED      = 1 << 7,
1420         MLX5_FLEX_PARSER_ICMP_V4_ENABLED        = 1 << 8,
1421         MLX5_FLEX_PARSER_ICMP_V6_ENABLED        = 1 << 9,
1422         MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1423         MLX5_FLEX_PARSER_GTPU_ENABLED           = 1 << 11,
1424         MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED      = 1 << 16,
1425         MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1426         MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED      = 1 << 18,
1427         MLX5_FLEX_PARSER_GTPU_TEID_ENABLED      = 1 << 19,
1428 };
1429
1430 enum {
1431         MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1432         MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1433 };
1434
1435 #define MLX5_FC_BULK_SIZE_FACTOR 128
1436
1437 enum mlx5_fc_bulk_alloc_bitmask {
1438         MLX5_FC_BULK_128   = (1 << 0),
1439         MLX5_FC_BULK_256   = (1 << 1),
1440         MLX5_FC_BULK_512   = (1 << 2),
1441         MLX5_FC_BULK_1024  = (1 << 3),
1442         MLX5_FC_BULK_2048  = (1 << 4),
1443         MLX5_FC_BULK_4096  = (1 << 5),
1444         MLX5_FC_BULK_8192  = (1 << 6),
1445         MLX5_FC_BULK_16384 = (1 << 7),
1446 };
1447
1448 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1449
1450 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1451
1452 enum {
1453         MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1454         MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1455         MLX5_STEERING_FORMAT_CONNECTX_7   = 2,
1456 };
1457
1458 struct mlx5_ifc_cmd_hca_cap_bits {
1459         u8         reserved_at_0[0x10];
1460         u8         shared_object_to_user_object_allowed[0x1];
1461         u8         reserved_at_13[0xe];
1462         u8         vhca_resource_manager[0x1];
1463
1464         u8         hca_cap_2[0x1];
1465         u8         create_lag_when_not_master_up[0x1];
1466         u8         dtor[0x1];
1467         u8         event_on_vhca_state_teardown_request[0x1];
1468         u8         event_on_vhca_state_in_use[0x1];
1469         u8         event_on_vhca_state_active[0x1];
1470         u8         event_on_vhca_state_allocated[0x1];
1471         u8         event_on_vhca_state_invalid[0x1];
1472         u8         reserved_at_28[0x8];
1473         u8         vhca_id[0x10];
1474
1475         u8         reserved_at_40[0x40];
1476
1477         u8         log_max_srq_sz[0x8];
1478         u8         log_max_qp_sz[0x8];
1479         u8         event_cap[0x1];
1480         u8         reserved_at_91[0x2];
1481         u8         isolate_vl_tc_new[0x1];
1482         u8         reserved_at_94[0x4];
1483         u8         prio_tag_required[0x1];
1484         u8         reserved_at_99[0x2];
1485         u8         log_max_qp[0x5];
1486
1487         u8         reserved_at_a0[0x3];
1488         u8         ece_support[0x1];
1489         u8         reserved_at_a4[0x5];
1490         u8         reg_c_preserve[0x1];
1491         u8         reserved_at_aa[0x1];
1492         u8         log_max_srq[0x5];
1493         u8         reserved_at_b0[0x1];
1494         u8         uplink_follow[0x1];
1495         u8         ts_cqe_to_dest_cqn[0x1];
1496         u8         reserved_at_b3[0x7];
1497         u8         shampo[0x1];
1498         u8         reserved_at_bb[0x5];
1499
1500         u8         max_sgl_for_optimized_performance[0x8];
1501         u8         log_max_cq_sz[0x8];
1502         u8         relaxed_ordering_write_umr[0x1];
1503         u8         relaxed_ordering_read_umr[0x1];
1504         u8         reserved_at_d2[0x7];
1505         u8         virtio_net_device_emualtion_manager[0x1];
1506         u8         virtio_blk_device_emualtion_manager[0x1];
1507         u8         log_max_cq[0x5];
1508
1509         u8         log_max_eq_sz[0x8];
1510         u8         relaxed_ordering_write[0x1];
1511         u8         relaxed_ordering_read[0x1];
1512         u8         log_max_mkey[0x6];
1513         u8         reserved_at_f0[0x6];
1514         u8         terminate_scatter_list_mkey[0x1];
1515         u8         repeated_mkey[0x1];
1516         u8         dump_fill_mkey[0x1];
1517         u8         reserved_at_f9[0x2];
1518         u8         fast_teardown[0x1];
1519         u8         log_max_eq[0x4];
1520
1521         u8         max_indirection[0x8];
1522         u8         fixed_buffer_size[0x1];
1523         u8         log_max_mrw_sz[0x7];
1524         u8         force_teardown[0x1];
1525         u8         reserved_at_111[0x1];
1526         u8         log_max_bsf_list_size[0x6];
1527         u8         umr_extended_translation_offset[0x1];
1528         u8         null_mkey[0x1];
1529         u8         log_max_klm_list_size[0x6];
1530
1531         u8         reserved_at_120[0x2];
1532         u8         qpc_extension[0x1];
1533         u8         reserved_at_123[0x7];
1534         u8         log_max_ra_req_dc[0x6];
1535         u8         reserved_at_130[0x2];
1536         u8         eth_wqe_too_small[0x1];
1537         u8         reserved_at_133[0x6];
1538         u8         vnic_env_cq_overrun[0x1];
1539         u8         log_max_ra_res_dc[0x6];
1540
1541         u8         reserved_at_140[0x5];
1542         u8         release_all_pages[0x1];
1543         u8         must_not_use[0x1];
1544         u8         reserved_at_147[0x2];
1545         u8         roce_accl[0x1];
1546         u8         log_max_ra_req_qp[0x6];
1547         u8         reserved_at_150[0xa];
1548         u8         log_max_ra_res_qp[0x6];
1549
1550         u8         end_pad[0x1];
1551         u8         cc_query_allowed[0x1];
1552         u8         cc_modify_allowed[0x1];
1553         u8         start_pad[0x1];
1554         u8         cache_line_128byte[0x1];
1555         u8         reserved_at_165[0x4];
1556         u8         rts2rts_qp_counters_set_id[0x1];
1557         u8         reserved_at_16a[0x2];
1558         u8         vnic_env_int_rq_oob[0x1];
1559         u8         sbcam_reg[0x1];
1560         u8         reserved_at_16e[0x1];
1561         u8         qcam_reg[0x1];
1562         u8         gid_table_size[0x10];
1563
1564         u8         out_of_seq_cnt[0x1];
1565         u8         vport_counters[0x1];
1566         u8         retransmission_q_counters[0x1];
1567         u8         debug[0x1];
1568         u8         modify_rq_counter_set_id[0x1];
1569         u8         rq_delay_drop[0x1];
1570         u8         max_qp_cnt[0xa];
1571         u8         pkey_table_size[0x10];
1572
1573         u8         vport_group_manager[0x1];
1574         u8         vhca_group_manager[0x1];
1575         u8         ib_virt[0x1];
1576         u8         eth_virt[0x1];
1577         u8         vnic_env_queue_counters[0x1];
1578         u8         ets[0x1];
1579         u8         nic_flow_table[0x1];
1580         u8         eswitch_manager[0x1];
1581         u8         device_memory[0x1];
1582         u8         mcam_reg[0x1];
1583         u8         pcam_reg[0x1];
1584         u8         local_ca_ack_delay[0x5];
1585         u8         port_module_event[0x1];
1586         u8         enhanced_error_q_counters[0x1];
1587         u8         ports_check[0x1];
1588         u8         reserved_at_1b3[0x1];
1589         u8         disable_link_up[0x1];
1590         u8         beacon_led[0x1];
1591         u8         port_type[0x2];
1592         u8         num_ports[0x8];
1593
1594         u8         reserved_at_1c0[0x1];
1595         u8         pps[0x1];
1596         u8         pps_modify[0x1];
1597         u8         log_max_msg[0x5];
1598         u8         reserved_at_1c8[0x4];
1599         u8         max_tc[0x4];
1600         u8         temp_warn_event[0x1];
1601         u8         dcbx[0x1];
1602         u8         general_notification_event[0x1];
1603         u8         reserved_at_1d3[0x2];
1604         u8         fpga[0x1];
1605         u8         rol_s[0x1];
1606         u8         rol_g[0x1];
1607         u8         reserved_at_1d8[0x1];
1608         u8         wol_s[0x1];
1609         u8         wol_g[0x1];
1610         u8         wol_a[0x1];
1611         u8         wol_b[0x1];
1612         u8         wol_m[0x1];
1613         u8         wol_u[0x1];
1614         u8         wol_p[0x1];
1615
1616         u8         stat_rate_support[0x10];
1617         u8         reserved_at_1f0[0x1];
1618         u8         pci_sync_for_fw_update_event[0x1];
1619         u8         reserved_at_1f2[0x6];
1620         u8         init2_lag_tx_port_affinity[0x1];
1621         u8         reserved_at_1fa[0x3];
1622         u8         cqe_version[0x4];
1623
1624         u8         compact_address_vector[0x1];
1625         u8         striding_rq[0x1];
1626         u8         reserved_at_202[0x1];
1627         u8         ipoib_enhanced_offloads[0x1];
1628         u8         ipoib_basic_offloads[0x1];
1629         u8         reserved_at_205[0x1];
1630         u8         repeated_block_disabled[0x1];
1631         u8         umr_modify_entity_size_disabled[0x1];
1632         u8         umr_modify_atomic_disabled[0x1];
1633         u8         umr_indirect_mkey_disabled[0x1];
1634         u8         umr_fence[0x2];
1635         u8         dc_req_scat_data_cqe[0x1];
1636         u8         reserved_at_20d[0x2];
1637         u8         drain_sigerr[0x1];
1638         u8         cmdif_checksum[0x2];
1639         u8         sigerr_cqe[0x1];
1640         u8         reserved_at_213[0x1];
1641         u8         wq_signature[0x1];
1642         u8         sctr_data_cqe[0x1];
1643         u8         reserved_at_216[0x1];
1644         u8         sho[0x1];
1645         u8         tph[0x1];
1646         u8         rf[0x1];
1647         u8         dct[0x1];
1648         u8         qos[0x1];
1649         u8         eth_net_offloads[0x1];
1650         u8         roce[0x1];
1651         u8         atomic[0x1];
1652         u8         reserved_at_21f[0x1];
1653
1654         u8         cq_oi[0x1];
1655         u8         cq_resize[0x1];
1656         u8         cq_moderation[0x1];
1657         u8         reserved_at_223[0x3];
1658         u8         cq_eq_remap[0x1];
1659         u8         pg[0x1];
1660         u8         block_lb_mc[0x1];
1661         u8         reserved_at_229[0x1];
1662         u8         scqe_break_moderation[0x1];
1663         u8         cq_period_start_from_cqe[0x1];
1664         u8         cd[0x1];
1665         u8         reserved_at_22d[0x1];
1666         u8         apm[0x1];
1667         u8         vector_calc[0x1];
1668         u8         umr_ptr_rlky[0x1];
1669         u8         imaicl[0x1];
1670         u8         qp_packet_based[0x1];
1671         u8         reserved_at_233[0x3];
1672         u8         qkv[0x1];
1673         u8         pkv[0x1];
1674         u8         set_deth_sqpn[0x1];
1675         u8         reserved_at_239[0x3];
1676         u8         xrc[0x1];
1677         u8         ud[0x1];
1678         u8         uc[0x1];
1679         u8         rc[0x1];
1680
1681         u8         uar_4k[0x1];
1682         u8         reserved_at_241[0x7];
1683         u8         fl_rc_qp_when_roce_disabled[0x1];
1684         u8         regexp_params[0x1];
1685         u8         uar_sz[0x6];
1686         u8         port_selection_cap[0x1];
1687         u8         reserved_at_248[0x1];
1688         u8         umem_uid_0[0x1];
1689         u8         reserved_at_250[0x5];
1690         u8         log_pg_sz[0x8];
1691
1692         u8         bf[0x1];
1693         u8         driver_version[0x1];
1694         u8         pad_tx_eth_packet[0x1];
1695         u8         reserved_at_263[0x3];
1696         u8         mkey_by_name[0x1];
1697         u8         reserved_at_267[0x4];
1698
1699         u8         log_bf_reg_size[0x5];
1700
1701         u8         reserved_at_270[0x3];
1702         u8         qp_error_syndrome[0x1];
1703         u8         reserved_at_274[0x2];
1704         u8         lag_dct[0x2];
1705         u8         lag_tx_port_affinity[0x1];
1706         u8         lag_native_fdb_selection[0x1];
1707         u8         reserved_at_27a[0x1];
1708         u8         lag_master[0x1];
1709         u8         num_lag_ports[0x4];
1710
1711         u8         reserved_at_280[0x10];
1712         u8         max_wqe_sz_sq[0x10];
1713
1714         u8         reserved_at_2a0[0x10];
1715         u8         max_wqe_sz_rq[0x10];
1716
1717         u8         max_flow_counter_31_16[0x10];
1718         u8         max_wqe_sz_sq_dc[0x10];
1719
1720         u8         reserved_at_2e0[0x7];
1721         u8         max_qp_mcg[0x19];
1722
1723         u8         reserved_at_300[0x10];
1724         u8         flow_counter_bulk_alloc[0x8];
1725         u8         log_max_mcg[0x8];
1726
1727         u8         reserved_at_320[0x3];
1728         u8         log_max_transport_domain[0x5];
1729         u8         reserved_at_328[0x3];
1730         u8         log_max_pd[0x5];
1731         u8         reserved_at_330[0xb];
1732         u8         log_max_xrcd[0x5];
1733
1734         u8         nic_receive_steering_discard[0x1];
1735         u8         receive_discard_vport_down[0x1];
1736         u8         transmit_discard_vport_down[0x1];
1737         u8         eq_overrun_count[0x1];
1738         u8         reserved_at_344[0x1];
1739         u8         invalid_command_count[0x1];
1740         u8         quota_exceeded_count[0x1];
1741         u8         reserved_at_347[0x1];
1742         u8         log_max_flow_counter_bulk[0x8];
1743         u8         max_flow_counter_15_0[0x10];
1744
1745
1746         u8         reserved_at_360[0x3];
1747         u8         log_max_rq[0x5];
1748         u8         reserved_at_368[0x3];
1749         u8         log_max_sq[0x5];
1750         u8         reserved_at_370[0x3];
1751         u8         log_max_tir[0x5];
1752         u8         reserved_at_378[0x3];
1753         u8         log_max_tis[0x5];
1754
1755         u8         basic_cyclic_rcv_wqe[0x1];
1756         u8         reserved_at_381[0x2];
1757         u8         log_max_rmp[0x5];
1758         u8         reserved_at_388[0x3];
1759         u8         log_max_rqt[0x5];
1760         u8         reserved_at_390[0x3];
1761         u8         log_max_rqt_size[0x5];
1762         u8         reserved_at_398[0x3];
1763         u8         log_max_tis_per_sq[0x5];
1764
1765         u8         ext_stride_num_range[0x1];
1766         u8         roce_rw_supported[0x1];
1767         u8         log_max_current_uc_list_wr_supported[0x1];
1768         u8         log_max_stride_sz_rq[0x5];
1769         u8         reserved_at_3a8[0x3];
1770         u8         log_min_stride_sz_rq[0x5];
1771         u8         reserved_at_3b0[0x3];
1772         u8         log_max_stride_sz_sq[0x5];
1773         u8         reserved_at_3b8[0x3];
1774         u8         log_min_stride_sz_sq[0x5];
1775
1776         u8         hairpin[0x1];
1777         u8         reserved_at_3c1[0x2];
1778         u8         log_max_hairpin_queues[0x5];
1779         u8         reserved_at_3c8[0x3];
1780         u8         log_max_hairpin_wq_data_sz[0x5];
1781         u8         reserved_at_3d0[0x3];
1782         u8         log_max_hairpin_num_packets[0x5];
1783         u8         reserved_at_3d8[0x3];
1784         u8         log_max_wq_sz[0x5];
1785
1786         u8         nic_vport_change_event[0x1];
1787         u8         disable_local_lb_uc[0x1];
1788         u8         disable_local_lb_mc[0x1];
1789         u8         log_min_hairpin_wq_data_sz[0x5];
1790         u8         reserved_at_3e8[0x2];
1791         u8         vhca_state[0x1];
1792         u8         log_max_vlan_list[0x5];
1793         u8         reserved_at_3f0[0x3];
1794         u8         log_max_current_mc_list[0x5];
1795         u8         reserved_at_3f8[0x3];
1796         u8         log_max_current_uc_list[0x5];
1797
1798         u8         general_obj_types[0x40];
1799
1800         u8         sq_ts_format[0x2];
1801         u8         rq_ts_format[0x2];
1802         u8         steering_format_version[0x4];
1803         u8         create_qp_start_hint[0x18];
1804
1805         u8         reserved_at_460[0x1];
1806         u8         ats[0x1];
1807         u8         reserved_at_462[0x1];
1808         u8         log_max_uctx[0x5];
1809         u8         reserved_at_468[0x1];
1810         u8         crypto[0x1];
1811         u8         ipsec_offload[0x1];
1812         u8         log_max_umem[0x5];
1813         u8         max_num_eqs[0x10];
1814
1815         u8         reserved_at_480[0x1];
1816         u8         tls_tx[0x1];
1817         u8         tls_rx[0x1];
1818         u8         log_max_l2_table[0x5];
1819         u8         reserved_at_488[0x8];
1820         u8         log_uar_page_sz[0x10];
1821
1822         u8         reserved_at_4a0[0x20];
1823         u8         device_frequency_mhz[0x20];
1824         u8         device_frequency_khz[0x20];
1825
1826         u8         reserved_at_500[0x20];
1827         u8         num_of_uars_per_page[0x20];
1828
1829         u8         flex_parser_protocols[0x20];
1830
1831         u8         max_geneve_tlv_options[0x8];
1832         u8         reserved_at_568[0x3];
1833         u8         max_geneve_tlv_option_data_len[0x5];
1834         u8         reserved_at_570[0x9];
1835         u8         adv_virtualization[0x1];
1836         u8         reserved_at_57a[0x6];
1837
1838         u8         reserved_at_580[0xb];
1839         u8         log_max_dci_stream_channels[0x5];
1840         u8         reserved_at_590[0x3];
1841         u8         log_max_dci_errored_streams[0x5];
1842         u8         reserved_at_598[0x8];
1843
1844         u8         reserved_at_5a0[0x10];
1845         u8         enhanced_cqe_compression[0x1];
1846         u8         reserved_at_5b1[0x2];
1847         u8         log_max_dek[0x5];
1848         u8         reserved_at_5b8[0x4];
1849         u8         mini_cqe_resp_stride_index[0x1];
1850         u8         cqe_128_always[0x1];
1851         u8         cqe_compression_128[0x1];
1852         u8         cqe_compression[0x1];
1853
1854         u8         cqe_compression_timeout[0x10];
1855         u8         cqe_compression_max_num[0x10];
1856
1857         u8         reserved_at_5e0[0x8];
1858         u8         flex_parser_id_gtpu_dw_0[0x4];
1859         u8         reserved_at_5ec[0x4];
1860         u8         tag_matching[0x1];
1861         u8         rndv_offload_rc[0x1];
1862         u8         rndv_offload_dc[0x1];
1863         u8         log_tag_matching_list_sz[0x5];
1864         u8         reserved_at_5f8[0x3];
1865         u8         log_max_xrq[0x5];
1866
1867         u8         affiliate_nic_vport_criteria[0x8];
1868         u8         native_port_num[0x8];
1869         u8         num_vhca_ports[0x8];
1870         u8         flex_parser_id_gtpu_teid[0x4];
1871         u8         reserved_at_61c[0x2];
1872         u8         sw_owner_id[0x1];
1873         u8         reserved_at_61f[0x1];
1874
1875         u8         max_num_of_monitor_counters[0x10];
1876         u8         num_ppcnt_monitor_counters[0x10];
1877
1878         u8         max_num_sf[0x10];
1879         u8         num_q_monitor_counters[0x10];
1880
1881         u8         reserved_at_660[0x20];
1882
1883         u8         sf[0x1];
1884         u8         sf_set_partition[0x1];
1885         u8         reserved_at_682[0x1];
1886         u8         log_max_sf[0x5];
1887         u8         apu[0x1];
1888         u8         reserved_at_689[0x4];
1889         u8         migration[0x1];
1890         u8         reserved_at_68e[0x2];
1891         u8         log_min_sf_size[0x8];
1892         u8         max_num_sf_partitions[0x8];
1893
1894         u8         uctx_cap[0x20];
1895
1896         u8         reserved_at_6c0[0x4];
1897         u8         flex_parser_id_geneve_tlv_option_0[0x4];
1898         u8         flex_parser_id_icmp_dw1[0x4];
1899         u8         flex_parser_id_icmp_dw0[0x4];
1900         u8         flex_parser_id_icmpv6_dw1[0x4];
1901         u8         flex_parser_id_icmpv6_dw0[0x4];
1902         u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
1903         u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1904
1905         u8         max_num_match_definer[0x10];
1906         u8         sf_base_id[0x10];
1907
1908         u8         flex_parser_id_gtpu_dw_2[0x4];
1909         u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
1910         u8         num_total_dynamic_vf_msix[0x18];
1911         u8         reserved_at_720[0x14];
1912         u8         dynamic_msix_table_size[0xc];
1913         u8         reserved_at_740[0xc];
1914         u8         min_dynamic_vf_msix_table_size[0x4];
1915         u8         reserved_at_750[0x4];
1916         u8         max_dynamic_vf_msix_table_size[0xc];
1917
1918         u8         reserved_at_760[0x20];
1919         u8         vhca_tunnel_commands[0x40];
1920         u8         match_definer_format_supported[0x40];
1921 };
1922
1923 struct mlx5_ifc_cmd_hca_cap_2_bits {
1924         u8         reserved_at_0[0x80];
1925
1926         u8         migratable[0x1];
1927         u8         reserved_at_81[0x1f];
1928
1929         u8         max_reformat_insert_size[0x8];
1930         u8         max_reformat_insert_offset[0x8];
1931         u8         max_reformat_remove_size[0x8];
1932         u8         max_reformat_remove_offset[0x8];
1933
1934         u8         reserved_at_c0[0x8];
1935         u8         migration_multi_load[0x1];
1936         u8         migration_tracking_state[0x1];
1937         u8         reserved_at_ca[0x16];
1938
1939         u8         reserved_at_e0[0xc0];
1940
1941         u8         flow_table_type_2_type[0x8];
1942         u8         reserved_at_1a8[0x3];
1943         u8         log_min_mkey_entity_size[0x5];
1944         u8         reserved_at_1b0[0x10];
1945
1946         u8         reserved_at_1c0[0x60];
1947
1948         u8         reserved_at_220[0x1];
1949         u8         sw_vhca_id_valid[0x1];
1950         u8         sw_vhca_id[0xe];
1951         u8         reserved_at_230[0x10];
1952
1953         u8         reserved_at_240[0xb];
1954         u8         ts_cqe_metadata_size2wqe_counter[0x5];
1955         u8         reserved_at_250[0x10];
1956
1957         u8         reserved_at_260[0x5a0];
1958 };
1959
1960 enum mlx5_ifc_flow_destination_type {
1961         MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1962         MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1963         MLX5_IFC_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1964         MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1965         MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK       = 0x8,
1966         MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE   = 0xA,
1967 };
1968
1969 enum mlx5_flow_table_miss_action {
1970         MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1971         MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1972         MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1973 };
1974
1975 struct mlx5_ifc_dest_format_struct_bits {
1976         u8         destination_type[0x8];
1977         u8         destination_id[0x18];
1978
1979         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1980         u8         packet_reformat[0x1];
1981         u8         reserved_at_22[0x6];
1982         u8         destination_table_type[0x8];
1983         u8         destination_eswitch_owner_vhca_id[0x10];
1984 };
1985
1986 struct mlx5_ifc_flow_counter_list_bits {
1987         u8         flow_counter_id[0x20];
1988
1989         u8         reserved_at_20[0x20];
1990 };
1991
1992 struct mlx5_ifc_extended_dest_format_bits {
1993         struct mlx5_ifc_dest_format_struct_bits destination_entry;
1994
1995         u8         packet_reformat_id[0x20];
1996
1997         u8         reserved_at_60[0x20];
1998 };
1999
2000 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
2001         struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
2002         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
2003 };
2004
2005 struct mlx5_ifc_fte_match_param_bits {
2006         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
2007
2008         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
2009
2010         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
2011
2012         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
2013
2014         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
2015
2016         struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
2017
2018         struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
2019
2020         u8         reserved_at_e00[0x200];
2021 };
2022
2023 enum {
2024         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
2025         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
2026         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
2027         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
2028         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
2029 };
2030
2031 struct mlx5_ifc_rx_hash_field_select_bits {
2032         u8         l3_prot_type[0x1];
2033         u8         l4_prot_type[0x1];
2034         u8         selected_fields[0x1e];
2035 };
2036
2037 enum {
2038         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
2039         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
2040 };
2041
2042 enum {
2043         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
2044         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
2045 };
2046
2047 struct mlx5_ifc_wq_bits {
2048         u8         wq_type[0x4];
2049         u8         wq_signature[0x1];
2050         u8         end_padding_mode[0x2];
2051         u8         cd_slave[0x1];
2052         u8         reserved_at_8[0x18];
2053
2054         u8         hds_skip_first_sge[0x1];
2055         u8         log2_hds_buf_size[0x3];
2056         u8         reserved_at_24[0x7];
2057         u8         page_offset[0x5];
2058         u8         lwm[0x10];
2059
2060         u8         reserved_at_40[0x8];
2061         u8         pd[0x18];
2062
2063         u8         reserved_at_60[0x8];
2064         u8         uar_page[0x18];
2065
2066         u8         dbr_addr[0x40];
2067
2068         u8         hw_counter[0x20];
2069
2070         u8         sw_counter[0x20];
2071
2072         u8         reserved_at_100[0xc];
2073         u8         log_wq_stride[0x4];
2074         u8         reserved_at_110[0x3];
2075         u8         log_wq_pg_sz[0x5];
2076         u8         reserved_at_118[0x3];
2077         u8         log_wq_sz[0x5];
2078
2079         u8         dbr_umem_valid[0x1];
2080         u8         wq_umem_valid[0x1];
2081         u8         reserved_at_122[0x1];
2082         u8         log_hairpin_num_packets[0x5];
2083         u8         reserved_at_128[0x3];
2084         u8         log_hairpin_data_sz[0x5];
2085
2086         u8         reserved_at_130[0x4];
2087         u8         log_wqe_num_of_strides[0x4];
2088         u8         two_byte_shift_en[0x1];
2089         u8         reserved_at_139[0x4];
2090         u8         log_wqe_stride_size[0x3];
2091
2092         u8         reserved_at_140[0x80];
2093
2094         u8         headers_mkey[0x20];
2095
2096         u8         shampo_enable[0x1];
2097         u8         reserved_at_1e1[0x4];
2098         u8         log_reservation_size[0x3];
2099         u8         reserved_at_1e8[0x5];
2100         u8         log_max_num_of_packets_per_reservation[0x3];
2101         u8         reserved_at_1f0[0x6];
2102         u8         log_headers_entry_size[0x2];
2103         u8         reserved_at_1f8[0x4];
2104         u8         log_headers_buffer_entry_num[0x4];
2105
2106         u8         reserved_at_200[0x400];
2107
2108         struct mlx5_ifc_cmd_pas_bits pas[];
2109 };
2110
2111 struct mlx5_ifc_rq_num_bits {
2112         u8         reserved_at_0[0x8];
2113         u8         rq_num[0x18];
2114 };
2115
2116 struct mlx5_ifc_mac_address_layout_bits {
2117         u8         reserved_at_0[0x10];
2118         u8         mac_addr_47_32[0x10];
2119
2120         u8         mac_addr_31_0[0x20];
2121 };
2122
2123 struct mlx5_ifc_vlan_layout_bits {
2124         u8         reserved_at_0[0x14];
2125         u8         vlan[0x0c];
2126
2127         u8         reserved_at_20[0x20];
2128 };
2129
2130 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
2131         u8         reserved_at_0[0xa0];
2132
2133         u8         min_time_between_cnps[0x20];
2134
2135         u8         reserved_at_c0[0x12];
2136         u8         cnp_dscp[0x6];
2137         u8         reserved_at_d8[0x4];
2138         u8         cnp_prio_mode[0x1];
2139         u8         cnp_802p_prio[0x3];
2140
2141         u8         reserved_at_e0[0x720];
2142 };
2143
2144 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
2145         u8         reserved_at_0[0x60];
2146
2147         u8         reserved_at_60[0x4];
2148         u8         clamp_tgt_rate[0x1];
2149         u8         reserved_at_65[0x3];
2150         u8         clamp_tgt_rate_after_time_inc[0x1];
2151         u8         reserved_at_69[0x17];
2152
2153         u8         reserved_at_80[0x20];
2154
2155         u8         rpg_time_reset[0x20];
2156
2157         u8         rpg_byte_reset[0x20];
2158
2159         u8         rpg_threshold[0x20];
2160
2161         u8         rpg_max_rate[0x20];
2162
2163         u8         rpg_ai_rate[0x20];
2164
2165         u8         rpg_hai_rate[0x20];
2166
2167         u8         rpg_gd[0x20];
2168
2169         u8         rpg_min_dec_fac[0x20];
2170
2171         u8         rpg_min_rate[0x20];
2172
2173         u8         reserved_at_1c0[0xe0];
2174
2175         u8         rate_to_set_on_first_cnp[0x20];
2176
2177         u8         dce_tcp_g[0x20];
2178
2179         u8         dce_tcp_rtt[0x20];
2180
2181         u8         rate_reduce_monitor_period[0x20];
2182
2183         u8         reserved_at_320[0x20];
2184
2185         u8         initial_alpha_value[0x20];
2186
2187         u8         reserved_at_360[0x4a0];
2188 };
2189
2190 struct mlx5_ifc_cong_control_r_roce_general_bits {
2191         u8         reserved_at_0[0x80];
2192
2193         u8         reserved_at_80[0x10];
2194         u8         rtt_resp_dscp_valid[0x1];
2195         u8         reserved_at_91[0x9];
2196         u8         rtt_resp_dscp[0x6];
2197
2198         u8         reserved_at_a0[0x760];
2199 };
2200
2201 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
2202         u8         reserved_at_0[0x80];
2203
2204         u8         rppp_max_rps[0x20];
2205
2206         u8         rpg_time_reset[0x20];
2207
2208         u8         rpg_byte_reset[0x20];
2209
2210         u8         rpg_threshold[0x20];
2211
2212         u8         rpg_max_rate[0x20];
2213
2214         u8         rpg_ai_rate[0x20];
2215
2216         u8         rpg_hai_rate[0x20];
2217
2218         u8         rpg_gd[0x20];
2219
2220         u8         rpg_min_dec_fac[0x20];
2221
2222         u8         rpg_min_rate[0x20];
2223
2224         u8         reserved_at_1c0[0x640];
2225 };
2226
2227 enum {
2228         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
2229         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
2230         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
2231 };
2232
2233 struct mlx5_ifc_resize_field_select_bits {
2234         u8         resize_field_select[0x20];
2235 };
2236
2237 struct mlx5_ifc_resource_dump_bits {
2238         u8         more_dump[0x1];
2239         u8         inline_dump[0x1];
2240         u8         reserved_at_2[0xa];
2241         u8         seq_num[0x4];
2242         u8         segment_type[0x10];
2243
2244         u8         reserved_at_20[0x10];
2245         u8         vhca_id[0x10];
2246
2247         u8         index1[0x20];
2248
2249         u8         index2[0x20];
2250
2251         u8         num_of_obj1[0x10];
2252         u8         num_of_obj2[0x10];
2253
2254         u8         reserved_at_a0[0x20];
2255
2256         u8         device_opaque[0x40];
2257
2258         u8         mkey[0x20];
2259
2260         u8         size[0x20];
2261
2262         u8         address[0x40];
2263
2264         u8         inline_data[52][0x20];
2265 };
2266
2267 struct mlx5_ifc_resource_dump_menu_record_bits {
2268         u8         reserved_at_0[0x4];
2269         u8         num_of_obj2_supports_active[0x1];
2270         u8         num_of_obj2_supports_all[0x1];
2271         u8         must_have_num_of_obj2[0x1];
2272         u8         support_num_of_obj2[0x1];
2273         u8         num_of_obj1_supports_active[0x1];
2274         u8         num_of_obj1_supports_all[0x1];
2275         u8         must_have_num_of_obj1[0x1];
2276         u8         support_num_of_obj1[0x1];
2277         u8         must_have_index2[0x1];
2278         u8         support_index2[0x1];
2279         u8         must_have_index1[0x1];
2280         u8         support_index1[0x1];
2281         u8         segment_type[0x10];
2282
2283         u8         segment_name[4][0x20];
2284
2285         u8         index1_name[4][0x20];
2286
2287         u8         index2_name[4][0x20];
2288 };
2289
2290 struct mlx5_ifc_resource_dump_segment_header_bits {
2291         u8         length_dw[0x10];
2292         u8         segment_type[0x10];
2293 };
2294
2295 struct mlx5_ifc_resource_dump_command_segment_bits {
2296         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2297
2298         u8         segment_called[0x10];
2299         u8         vhca_id[0x10];
2300
2301         u8         index1[0x20];
2302
2303         u8         index2[0x20];
2304
2305         u8         num_of_obj1[0x10];
2306         u8         num_of_obj2[0x10];
2307 };
2308
2309 struct mlx5_ifc_resource_dump_error_segment_bits {
2310         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2311
2312         u8         reserved_at_20[0x10];
2313         u8         syndrome_id[0x10];
2314
2315         u8         reserved_at_40[0x40];
2316
2317         u8         error[8][0x20];
2318 };
2319
2320 struct mlx5_ifc_resource_dump_info_segment_bits {
2321         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2322
2323         u8         reserved_at_20[0x18];
2324         u8         dump_version[0x8];
2325
2326         u8         hw_version[0x20];
2327
2328         u8         fw_version[0x20];
2329 };
2330
2331 struct mlx5_ifc_resource_dump_menu_segment_bits {
2332         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2333
2334         u8         reserved_at_20[0x10];
2335         u8         num_of_records[0x10];
2336
2337         struct mlx5_ifc_resource_dump_menu_record_bits record[];
2338 };
2339
2340 struct mlx5_ifc_resource_dump_resource_segment_bits {
2341         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2342
2343         u8         reserved_at_20[0x20];
2344
2345         u8         index1[0x20];
2346
2347         u8         index2[0x20];
2348
2349         u8         payload[][0x20];
2350 };
2351
2352 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2353         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2354 };
2355
2356 struct mlx5_ifc_menu_resource_dump_response_bits {
2357         struct mlx5_ifc_resource_dump_info_segment_bits info;
2358         struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2359         struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2360         struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2361 };
2362
2363 enum {
2364         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
2365         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
2366         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
2367         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
2368 };
2369
2370 struct mlx5_ifc_modify_field_select_bits {
2371         u8         modify_field_select[0x20];
2372 };
2373
2374 struct mlx5_ifc_field_select_r_roce_np_bits {
2375         u8         field_select_r_roce_np[0x20];
2376 };
2377
2378 struct mlx5_ifc_field_select_r_roce_rp_bits {
2379         u8         field_select_r_roce_rp[0x20];
2380 };
2381
2382 enum {
2383         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2384         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2385         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2386         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2387         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2388         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2389         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2390         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2391         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2392         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2393 };
2394
2395 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2396         u8         field_select_8021qaurp[0x20];
2397 };
2398
2399 struct mlx5_ifc_phys_layer_cntrs_bits {
2400         u8         time_since_last_clear_high[0x20];
2401
2402         u8         time_since_last_clear_low[0x20];
2403
2404         u8         symbol_errors_high[0x20];
2405
2406         u8         symbol_errors_low[0x20];
2407
2408         u8         sync_headers_errors_high[0x20];
2409
2410         u8         sync_headers_errors_low[0x20];
2411
2412         u8         edpl_bip_errors_lane0_high[0x20];
2413
2414         u8         edpl_bip_errors_lane0_low[0x20];
2415
2416         u8         edpl_bip_errors_lane1_high[0x20];
2417
2418         u8         edpl_bip_errors_lane1_low[0x20];
2419
2420         u8         edpl_bip_errors_lane2_high[0x20];
2421
2422         u8         edpl_bip_errors_lane2_low[0x20];
2423
2424         u8         edpl_bip_errors_lane3_high[0x20];
2425
2426         u8         edpl_bip_errors_lane3_low[0x20];
2427
2428         u8         fc_fec_corrected_blocks_lane0_high[0x20];
2429
2430         u8         fc_fec_corrected_blocks_lane0_low[0x20];
2431
2432         u8         fc_fec_corrected_blocks_lane1_high[0x20];
2433
2434         u8         fc_fec_corrected_blocks_lane1_low[0x20];
2435
2436         u8         fc_fec_corrected_blocks_lane2_high[0x20];
2437
2438         u8         fc_fec_corrected_blocks_lane2_low[0x20];
2439
2440         u8         fc_fec_corrected_blocks_lane3_high[0x20];
2441
2442         u8         fc_fec_corrected_blocks_lane3_low[0x20];
2443
2444         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2445
2446         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2447
2448         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2449
2450         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2451
2452         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2453
2454         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2455
2456         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2457
2458         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2459
2460         u8         rs_fec_corrected_blocks_high[0x20];
2461
2462         u8         rs_fec_corrected_blocks_low[0x20];
2463
2464         u8         rs_fec_uncorrectable_blocks_high[0x20];
2465
2466         u8         rs_fec_uncorrectable_blocks_low[0x20];
2467
2468         u8         rs_fec_no_errors_blocks_high[0x20];
2469
2470         u8         rs_fec_no_errors_blocks_low[0x20];
2471
2472         u8         rs_fec_single_error_blocks_high[0x20];
2473
2474         u8         rs_fec_single_error_blocks_low[0x20];
2475
2476         u8         rs_fec_corrected_symbols_total_high[0x20];
2477
2478         u8         rs_fec_corrected_symbols_total_low[0x20];
2479
2480         u8         rs_fec_corrected_symbols_lane0_high[0x20];
2481
2482         u8         rs_fec_corrected_symbols_lane0_low[0x20];
2483
2484         u8         rs_fec_corrected_symbols_lane1_high[0x20];
2485
2486         u8         rs_fec_corrected_symbols_lane1_low[0x20];
2487
2488         u8         rs_fec_corrected_symbols_lane2_high[0x20];
2489
2490         u8         rs_fec_corrected_symbols_lane2_low[0x20];
2491
2492         u8         rs_fec_corrected_symbols_lane3_high[0x20];
2493
2494         u8         rs_fec_corrected_symbols_lane3_low[0x20];
2495
2496         u8         link_down_events[0x20];
2497
2498         u8         successful_recovery_events[0x20];
2499
2500         u8         reserved_at_640[0x180];
2501 };
2502
2503 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2504         u8         time_since_last_clear_high[0x20];
2505
2506         u8         time_since_last_clear_low[0x20];
2507
2508         u8         phy_received_bits_high[0x20];
2509
2510         u8         phy_received_bits_low[0x20];
2511
2512         u8         phy_symbol_errors_high[0x20];
2513
2514         u8         phy_symbol_errors_low[0x20];
2515
2516         u8         phy_corrected_bits_high[0x20];
2517
2518         u8         phy_corrected_bits_low[0x20];
2519
2520         u8         phy_corrected_bits_lane0_high[0x20];
2521
2522         u8         phy_corrected_bits_lane0_low[0x20];
2523
2524         u8         phy_corrected_bits_lane1_high[0x20];
2525
2526         u8         phy_corrected_bits_lane1_low[0x20];
2527
2528         u8         phy_corrected_bits_lane2_high[0x20];
2529
2530         u8         phy_corrected_bits_lane2_low[0x20];
2531
2532         u8         phy_corrected_bits_lane3_high[0x20];
2533
2534         u8         phy_corrected_bits_lane3_low[0x20];
2535
2536         u8         reserved_at_200[0x5c0];
2537 };
2538
2539 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2540         u8         symbol_error_counter[0x10];
2541
2542         u8         link_error_recovery_counter[0x8];
2543
2544         u8         link_downed_counter[0x8];
2545
2546         u8         port_rcv_errors[0x10];
2547
2548         u8         port_rcv_remote_physical_errors[0x10];
2549
2550         u8         port_rcv_switch_relay_errors[0x10];
2551
2552         u8         port_xmit_discards[0x10];
2553
2554         u8         port_xmit_constraint_errors[0x8];
2555
2556         u8         port_rcv_constraint_errors[0x8];
2557
2558         u8         reserved_at_70[0x8];
2559
2560         u8         link_overrun_errors[0x8];
2561
2562         u8         reserved_at_80[0x10];
2563
2564         u8         vl_15_dropped[0x10];
2565
2566         u8         reserved_at_a0[0x80];
2567
2568         u8         port_xmit_wait[0x20];
2569 };
2570
2571 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2572         u8         transmit_queue_high[0x20];
2573
2574         u8         transmit_queue_low[0x20];
2575
2576         u8         no_buffer_discard_uc_high[0x20];
2577
2578         u8         no_buffer_discard_uc_low[0x20];
2579
2580         u8         reserved_at_80[0x740];
2581 };
2582
2583 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2584         u8         wred_discard_high[0x20];
2585
2586         u8         wred_discard_low[0x20];
2587
2588         u8         ecn_marked_tc_high[0x20];
2589
2590         u8         ecn_marked_tc_low[0x20];
2591
2592         u8         reserved_at_80[0x740];
2593 };
2594
2595 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2596         u8         rx_octets_high[0x20];
2597
2598         u8         rx_octets_low[0x20];
2599
2600         u8         reserved_at_40[0xc0];
2601
2602         u8         rx_frames_high[0x20];
2603
2604         u8         rx_frames_low[0x20];
2605
2606         u8         tx_octets_high[0x20];
2607
2608         u8         tx_octets_low[0x20];
2609
2610         u8         reserved_at_180[0xc0];
2611
2612         u8         tx_frames_high[0x20];
2613
2614         u8         tx_frames_low[0x20];
2615
2616         u8         rx_pause_high[0x20];
2617
2618         u8         rx_pause_low[0x20];
2619
2620         u8         rx_pause_duration_high[0x20];
2621
2622         u8         rx_pause_duration_low[0x20];
2623
2624         u8         tx_pause_high[0x20];
2625
2626         u8         tx_pause_low[0x20];
2627
2628         u8         tx_pause_duration_high[0x20];
2629
2630         u8         tx_pause_duration_low[0x20];
2631
2632         u8         rx_pause_transition_high[0x20];
2633
2634         u8         rx_pause_transition_low[0x20];
2635
2636         u8         rx_discards_high[0x20];
2637
2638         u8         rx_discards_low[0x20];
2639
2640         u8         device_stall_minor_watermark_cnt_high[0x20];
2641
2642         u8         device_stall_minor_watermark_cnt_low[0x20];
2643
2644         u8         device_stall_critical_watermark_cnt_high[0x20];
2645
2646         u8         device_stall_critical_watermark_cnt_low[0x20];
2647
2648         u8         reserved_at_480[0x340];
2649 };
2650
2651 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2652         u8         port_transmit_wait_high[0x20];
2653
2654         u8         port_transmit_wait_low[0x20];
2655
2656         u8         reserved_at_40[0x100];
2657
2658         u8         rx_buffer_almost_full_high[0x20];
2659
2660         u8         rx_buffer_almost_full_low[0x20];
2661
2662         u8         rx_buffer_full_high[0x20];
2663
2664         u8         rx_buffer_full_low[0x20];
2665
2666         u8         rx_icrc_encapsulated_high[0x20];
2667
2668         u8         rx_icrc_encapsulated_low[0x20];
2669
2670         u8         reserved_at_200[0x5c0];
2671 };
2672
2673 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2674         u8         dot3stats_alignment_errors_high[0x20];
2675
2676         u8         dot3stats_alignment_errors_low[0x20];
2677
2678         u8         dot3stats_fcs_errors_high[0x20];
2679
2680         u8         dot3stats_fcs_errors_low[0x20];
2681
2682         u8         dot3stats_single_collision_frames_high[0x20];
2683
2684         u8         dot3stats_single_collision_frames_low[0x20];
2685
2686         u8         dot3stats_multiple_collision_frames_high[0x20];
2687
2688         u8         dot3stats_multiple_collision_frames_low[0x20];
2689
2690         u8         dot3stats_sqe_test_errors_high[0x20];
2691
2692         u8         dot3stats_sqe_test_errors_low[0x20];
2693
2694         u8         dot3stats_deferred_transmissions_high[0x20];
2695
2696         u8         dot3stats_deferred_transmissions_low[0x20];
2697
2698         u8         dot3stats_late_collisions_high[0x20];
2699
2700         u8         dot3stats_late_collisions_low[0x20];
2701
2702         u8         dot3stats_excessive_collisions_high[0x20];
2703
2704         u8         dot3stats_excessive_collisions_low[0x20];
2705
2706         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2707
2708         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2709
2710         u8         dot3stats_carrier_sense_errors_high[0x20];
2711
2712         u8         dot3stats_carrier_sense_errors_low[0x20];
2713
2714         u8         dot3stats_frame_too_longs_high[0x20];
2715
2716         u8         dot3stats_frame_too_longs_low[0x20];
2717
2718         u8         dot3stats_internal_mac_receive_errors_high[0x20];
2719
2720         u8         dot3stats_internal_mac_receive_errors_low[0x20];
2721
2722         u8         dot3stats_symbol_errors_high[0x20];
2723
2724         u8         dot3stats_symbol_errors_low[0x20];
2725
2726         u8         dot3control_in_unknown_opcodes_high[0x20];
2727
2728         u8         dot3control_in_unknown_opcodes_low[0x20];
2729
2730         u8         dot3in_pause_frames_high[0x20];
2731
2732         u8         dot3in_pause_frames_low[0x20];
2733
2734         u8         dot3out_pause_frames_high[0x20];
2735
2736         u8         dot3out_pause_frames_low[0x20];
2737
2738         u8         reserved_at_400[0x3c0];
2739 };
2740
2741 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2742         u8         ether_stats_drop_events_high[0x20];
2743
2744         u8         ether_stats_drop_events_low[0x20];
2745
2746         u8         ether_stats_octets_high[0x20];
2747
2748         u8         ether_stats_octets_low[0x20];
2749
2750         u8         ether_stats_pkts_high[0x20];
2751
2752         u8         ether_stats_pkts_low[0x20];
2753
2754         u8         ether_stats_broadcast_pkts_high[0x20];
2755
2756         u8         ether_stats_broadcast_pkts_low[0x20];
2757
2758         u8         ether_stats_multicast_pkts_high[0x20];
2759
2760         u8         ether_stats_multicast_pkts_low[0x20];
2761
2762         u8         ether_stats_crc_align_errors_high[0x20];
2763
2764         u8         ether_stats_crc_align_errors_low[0x20];
2765
2766         u8         ether_stats_undersize_pkts_high[0x20];
2767
2768         u8         ether_stats_undersize_pkts_low[0x20];
2769
2770         u8         ether_stats_oversize_pkts_high[0x20];
2771
2772         u8         ether_stats_oversize_pkts_low[0x20];
2773
2774         u8         ether_stats_fragments_high[0x20];
2775
2776         u8         ether_stats_fragments_low[0x20];
2777
2778         u8         ether_stats_jabbers_high[0x20];
2779
2780         u8         ether_stats_jabbers_low[0x20];
2781
2782         u8         ether_stats_collisions_high[0x20];
2783
2784         u8         ether_stats_collisions_low[0x20];
2785
2786         u8         ether_stats_pkts64octets_high[0x20];
2787
2788         u8         ether_stats_pkts64octets_low[0x20];
2789
2790         u8         ether_stats_pkts65to127octets_high[0x20];
2791
2792         u8         ether_stats_pkts65to127octets_low[0x20];
2793
2794         u8         ether_stats_pkts128to255octets_high[0x20];
2795
2796         u8         ether_stats_pkts128to255octets_low[0x20];
2797
2798         u8         ether_stats_pkts256to511octets_high[0x20];
2799
2800         u8         ether_stats_pkts256to511octets_low[0x20];
2801
2802         u8         ether_stats_pkts512to1023octets_high[0x20];
2803
2804         u8         ether_stats_pkts512to1023octets_low[0x20];
2805
2806         u8         ether_stats_pkts1024to1518octets_high[0x20];
2807
2808         u8         ether_stats_pkts1024to1518octets_low[0x20];
2809
2810         u8         ether_stats_pkts1519to2047octets_high[0x20];
2811
2812         u8         ether_stats_pkts1519to2047octets_low[0x20];
2813
2814         u8         ether_stats_pkts2048to4095octets_high[0x20];
2815
2816         u8         ether_stats_pkts2048to4095octets_low[0x20];
2817
2818         u8         ether_stats_pkts4096to8191octets_high[0x20];
2819
2820         u8         ether_stats_pkts4096to8191octets_low[0x20];
2821
2822         u8         ether_stats_pkts8192to10239octets_high[0x20];
2823
2824         u8         ether_stats_pkts8192to10239octets_low[0x20];
2825
2826         u8         reserved_at_540[0x280];
2827 };
2828
2829 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2830         u8         if_in_octets_high[0x20];
2831
2832         u8         if_in_octets_low[0x20];
2833
2834         u8         if_in_ucast_pkts_high[0x20];
2835
2836         u8         if_in_ucast_pkts_low[0x20];
2837
2838         u8         if_in_discards_high[0x20];
2839
2840         u8         if_in_discards_low[0x20];
2841
2842         u8         if_in_errors_high[0x20];
2843
2844         u8         if_in_errors_low[0x20];
2845
2846         u8         if_in_unknown_protos_high[0x20];
2847
2848         u8         if_in_unknown_protos_low[0x20];
2849
2850         u8         if_out_octets_high[0x20];
2851
2852         u8         if_out_octets_low[0x20];
2853
2854         u8         if_out_ucast_pkts_high[0x20];
2855
2856         u8         if_out_ucast_pkts_low[0x20];
2857
2858         u8         if_out_discards_high[0x20];
2859
2860         u8         if_out_discards_low[0x20];
2861
2862         u8         if_out_errors_high[0x20];
2863
2864         u8         if_out_errors_low[0x20];
2865
2866         u8         if_in_multicast_pkts_high[0x20];
2867
2868         u8         if_in_multicast_pkts_low[0x20];
2869
2870         u8         if_in_broadcast_pkts_high[0x20];
2871
2872         u8         if_in_broadcast_pkts_low[0x20];
2873
2874         u8         if_out_multicast_pkts_high[0x20];
2875
2876         u8         if_out_multicast_pkts_low[0x20];
2877
2878         u8         if_out_broadcast_pkts_high[0x20];
2879
2880         u8         if_out_broadcast_pkts_low[0x20];
2881
2882         u8         reserved_at_340[0x480];
2883 };
2884
2885 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2886         u8         a_frames_transmitted_ok_high[0x20];
2887
2888         u8         a_frames_transmitted_ok_low[0x20];
2889
2890         u8         a_frames_received_ok_high[0x20];
2891
2892         u8         a_frames_received_ok_low[0x20];
2893
2894         u8         a_frame_check_sequence_errors_high[0x20];
2895
2896         u8         a_frame_check_sequence_errors_low[0x20];
2897
2898         u8         a_alignment_errors_high[0x20];
2899
2900         u8         a_alignment_errors_low[0x20];
2901
2902         u8         a_octets_transmitted_ok_high[0x20];
2903
2904         u8         a_octets_transmitted_ok_low[0x20];
2905
2906         u8         a_octets_received_ok_high[0x20];
2907
2908         u8         a_octets_received_ok_low[0x20];
2909
2910         u8         a_multicast_frames_xmitted_ok_high[0x20];
2911
2912         u8         a_multicast_frames_xmitted_ok_low[0x20];
2913
2914         u8         a_broadcast_frames_xmitted_ok_high[0x20];
2915
2916         u8         a_broadcast_frames_xmitted_ok_low[0x20];
2917
2918         u8         a_multicast_frames_received_ok_high[0x20];
2919
2920         u8         a_multicast_frames_received_ok_low[0x20];
2921
2922         u8         a_broadcast_frames_received_ok_high[0x20];
2923
2924         u8         a_broadcast_frames_received_ok_low[0x20];
2925
2926         u8         a_in_range_length_errors_high[0x20];
2927
2928         u8         a_in_range_length_errors_low[0x20];
2929
2930         u8         a_out_of_range_length_field_high[0x20];
2931
2932         u8         a_out_of_range_length_field_low[0x20];
2933
2934         u8         a_frame_too_long_errors_high[0x20];
2935
2936         u8         a_frame_too_long_errors_low[0x20];
2937
2938         u8         a_symbol_error_during_carrier_high[0x20];
2939
2940         u8         a_symbol_error_during_carrier_low[0x20];
2941
2942         u8         a_mac_control_frames_transmitted_high[0x20];
2943
2944         u8         a_mac_control_frames_transmitted_low[0x20];
2945
2946         u8         a_mac_control_frames_received_high[0x20];
2947
2948         u8         a_mac_control_frames_received_low[0x20];
2949
2950         u8         a_unsupported_opcodes_received_high[0x20];
2951
2952         u8         a_unsupported_opcodes_received_low[0x20];
2953
2954         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2955
2956         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2957
2958         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2959
2960         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2961
2962         u8         reserved_at_4c0[0x300];
2963 };
2964
2965 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2966         u8         life_time_counter_high[0x20];
2967
2968         u8         life_time_counter_low[0x20];
2969
2970         u8         rx_errors[0x20];
2971
2972         u8         tx_errors[0x20];
2973
2974         u8         l0_to_recovery_eieos[0x20];
2975
2976         u8         l0_to_recovery_ts[0x20];
2977
2978         u8         l0_to_recovery_framing[0x20];
2979
2980         u8         l0_to_recovery_retrain[0x20];
2981
2982         u8         crc_error_dllp[0x20];
2983
2984         u8         crc_error_tlp[0x20];
2985
2986         u8         tx_overflow_buffer_pkt_high[0x20];
2987
2988         u8         tx_overflow_buffer_pkt_low[0x20];
2989
2990         u8         outbound_stalled_reads[0x20];
2991
2992         u8         outbound_stalled_writes[0x20];
2993
2994         u8         outbound_stalled_reads_events[0x20];
2995
2996         u8         outbound_stalled_writes_events[0x20];
2997
2998         u8         reserved_at_200[0x5c0];
2999 };
3000
3001 struct mlx5_ifc_cmd_inter_comp_event_bits {
3002         u8         command_completion_vector[0x20];
3003
3004         u8         reserved_at_20[0xc0];
3005 };
3006
3007 struct mlx5_ifc_stall_vl_event_bits {
3008         u8         reserved_at_0[0x18];
3009         u8         port_num[0x1];
3010         u8         reserved_at_19[0x3];
3011         u8         vl[0x4];
3012
3013         u8         reserved_at_20[0xa0];
3014 };
3015
3016 struct mlx5_ifc_db_bf_congestion_event_bits {
3017         u8         event_subtype[0x8];
3018         u8         reserved_at_8[0x8];
3019         u8         congestion_level[0x8];
3020         u8         reserved_at_18[0x8];
3021
3022         u8         reserved_at_20[0xa0];
3023 };
3024
3025 struct mlx5_ifc_gpio_event_bits {
3026         u8         reserved_at_0[0x60];
3027
3028         u8         gpio_event_hi[0x20];
3029
3030         u8         gpio_event_lo[0x20];
3031
3032         u8         reserved_at_a0[0x40];
3033 };
3034
3035 struct mlx5_ifc_port_state_change_event_bits {
3036         u8         reserved_at_0[0x40];
3037
3038         u8         port_num[0x4];
3039         u8         reserved_at_44[0x1c];
3040
3041         u8         reserved_at_60[0x80];
3042 };
3043
3044 struct mlx5_ifc_dropped_packet_logged_bits {
3045         u8         reserved_at_0[0xe0];
3046 };
3047
3048 struct mlx5_ifc_default_timeout_bits {
3049         u8         to_multiplier[0x3];
3050         u8         reserved_at_3[0x9];
3051         u8         to_value[0x14];
3052 };
3053
3054 struct mlx5_ifc_dtor_reg_bits {
3055         u8         reserved_at_0[0x20];
3056
3057         struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
3058
3059         u8         reserved_at_40[0x60];
3060
3061         struct mlx5_ifc_default_timeout_bits health_poll_to;
3062
3063         struct mlx5_ifc_default_timeout_bits full_crdump_to;
3064
3065         struct mlx5_ifc_default_timeout_bits fw_reset_to;
3066
3067         struct mlx5_ifc_default_timeout_bits flush_on_err_to;
3068
3069         struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
3070
3071         struct mlx5_ifc_default_timeout_bits tear_down_to;
3072
3073         struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
3074
3075         struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
3076
3077         struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
3078
3079         u8         reserved_at_1c0[0x40];
3080 };
3081
3082 enum {
3083         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
3084         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
3085 };
3086
3087 struct mlx5_ifc_cq_error_bits {
3088         u8         reserved_at_0[0x8];
3089         u8         cqn[0x18];
3090
3091         u8         reserved_at_20[0x20];
3092
3093         u8         reserved_at_40[0x18];
3094         u8         syndrome[0x8];
3095
3096         u8         reserved_at_60[0x80];
3097 };
3098
3099 struct mlx5_ifc_rdma_page_fault_event_bits {
3100         u8         bytes_committed[0x20];
3101
3102         u8         r_key[0x20];
3103
3104         u8         reserved_at_40[0x10];
3105         u8         packet_len[0x10];
3106
3107         u8         rdma_op_len[0x20];
3108
3109         u8         rdma_va[0x40];
3110
3111         u8         reserved_at_c0[0x5];
3112         u8         rdma[0x1];
3113         u8         write[0x1];
3114         u8         requestor[0x1];
3115         u8         qp_number[0x18];
3116 };
3117
3118 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
3119         u8         bytes_committed[0x20];
3120
3121         u8         reserved_at_20[0x10];
3122         u8         wqe_index[0x10];
3123
3124         u8         reserved_at_40[0x10];
3125         u8         len[0x10];
3126
3127         u8         reserved_at_60[0x60];
3128
3129         u8         reserved_at_c0[0x5];
3130         u8         rdma[0x1];
3131         u8         write_read[0x1];
3132         u8         requestor[0x1];
3133         u8         qpn[0x18];
3134 };
3135
3136 struct mlx5_ifc_qp_events_bits {
3137         u8         reserved_at_0[0xa0];
3138
3139         u8         type[0x8];
3140         u8         reserved_at_a8[0x18];
3141
3142         u8         reserved_at_c0[0x8];
3143         u8         qpn_rqn_sqn[0x18];
3144 };
3145
3146 struct mlx5_ifc_dct_events_bits {
3147         u8         reserved_at_0[0xc0];
3148
3149         u8         reserved_at_c0[0x8];
3150         u8         dct_number[0x18];
3151 };
3152
3153 struct mlx5_ifc_comp_event_bits {
3154         u8         reserved_at_0[0xc0];
3155
3156         u8         reserved_at_c0[0x8];
3157         u8         cq_number[0x18];
3158 };
3159
3160 enum {
3161         MLX5_QPC_STATE_RST        = 0x0,
3162         MLX5_QPC_STATE_INIT       = 0x1,
3163         MLX5_QPC_STATE_RTR        = 0x2,
3164         MLX5_QPC_STATE_RTS        = 0x3,
3165         MLX5_QPC_STATE_SQER       = 0x4,
3166         MLX5_QPC_STATE_ERR        = 0x6,
3167         MLX5_QPC_STATE_SQD        = 0x7,
3168         MLX5_QPC_STATE_SUSPENDED  = 0x9,
3169 };
3170
3171 enum {
3172         MLX5_QPC_ST_RC            = 0x0,
3173         MLX5_QPC_ST_UC            = 0x1,
3174         MLX5_QPC_ST_UD            = 0x2,
3175         MLX5_QPC_ST_XRC           = 0x3,
3176         MLX5_QPC_ST_DCI           = 0x5,
3177         MLX5_QPC_ST_QP0           = 0x7,
3178         MLX5_QPC_ST_QP1           = 0x8,
3179         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
3180         MLX5_QPC_ST_REG_UMR       = 0xc,
3181 };
3182
3183 enum {
3184         MLX5_QPC_PM_STATE_ARMED     = 0x0,
3185         MLX5_QPC_PM_STATE_REARM     = 0x1,
3186         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
3187         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
3188 };
3189
3190 enum {
3191         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
3192 };
3193
3194 enum {
3195         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
3196         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
3197 };
3198
3199 enum {
3200         MLX5_QPC_MTU_256_BYTES        = 0x1,
3201         MLX5_QPC_MTU_512_BYTES        = 0x2,
3202         MLX5_QPC_MTU_1K_BYTES         = 0x3,
3203         MLX5_QPC_MTU_2K_BYTES         = 0x4,
3204         MLX5_QPC_MTU_4K_BYTES         = 0x5,
3205         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
3206 };
3207
3208 enum {
3209         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
3210         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
3211         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
3212         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
3213         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
3214         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
3215         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
3216         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
3217 };
3218
3219 enum {
3220         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
3221         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
3222         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
3223 };
3224
3225 enum {
3226         MLX5_QPC_CS_RES_DISABLE    = 0x0,
3227         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
3228         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
3229 };
3230
3231 enum {
3232         MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3233         MLX5_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
3234         MLX5_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
3235 };
3236
3237 struct mlx5_ifc_qpc_bits {
3238         u8         state[0x4];
3239         u8         lag_tx_port_affinity[0x4];
3240         u8         st[0x8];
3241         u8         reserved_at_10[0x2];
3242         u8         isolate_vl_tc[0x1];
3243         u8         pm_state[0x2];
3244         u8         reserved_at_15[0x1];
3245         u8         req_e2e_credit_mode[0x2];
3246         u8         offload_type[0x4];
3247         u8         end_padding_mode[0x2];
3248         u8         reserved_at_1e[0x2];
3249
3250         u8         wq_signature[0x1];
3251         u8         block_lb_mc[0x1];
3252         u8         atomic_like_write_en[0x1];
3253         u8         latency_sensitive[0x1];
3254         u8         reserved_at_24[0x1];
3255         u8         drain_sigerr[0x1];
3256         u8         reserved_at_26[0x2];
3257         u8         pd[0x18];
3258
3259         u8         mtu[0x3];
3260         u8         log_msg_max[0x5];
3261         u8         reserved_at_48[0x1];
3262         u8         log_rq_size[0x4];
3263         u8         log_rq_stride[0x3];
3264         u8         no_sq[0x1];
3265         u8         log_sq_size[0x4];
3266         u8         reserved_at_55[0x3];
3267         u8         ts_format[0x2];
3268         u8         reserved_at_5a[0x1];
3269         u8         rlky[0x1];
3270         u8         ulp_stateless_offload_mode[0x4];
3271
3272         u8         counter_set_id[0x8];
3273         u8         uar_page[0x18];
3274
3275         u8         reserved_at_80[0x8];
3276         u8         user_index[0x18];
3277
3278         u8         reserved_at_a0[0x3];
3279         u8         log_page_size[0x5];
3280         u8         remote_qpn[0x18];
3281
3282         struct mlx5_ifc_ads_bits primary_address_path;
3283
3284         struct mlx5_ifc_ads_bits secondary_address_path;
3285
3286         u8         log_ack_req_freq[0x4];
3287         u8         reserved_at_384[0x4];
3288         u8         log_sra_max[0x3];
3289         u8         reserved_at_38b[0x2];
3290         u8         retry_count[0x3];
3291         u8         rnr_retry[0x3];
3292         u8         reserved_at_393[0x1];
3293         u8         fre[0x1];
3294         u8         cur_rnr_retry[0x3];
3295         u8         cur_retry_count[0x3];
3296         u8         reserved_at_39b[0x5];
3297
3298         u8         reserved_at_3a0[0x20];
3299
3300         u8         reserved_at_3c0[0x8];
3301         u8         next_send_psn[0x18];
3302
3303         u8         reserved_at_3e0[0x3];
3304         u8         log_num_dci_stream_channels[0x5];
3305         u8         cqn_snd[0x18];
3306
3307         u8         reserved_at_400[0x3];
3308         u8         log_num_dci_errored_streams[0x5];
3309         u8         deth_sqpn[0x18];
3310
3311         u8         reserved_at_420[0x20];
3312
3313         u8         reserved_at_440[0x8];
3314         u8         last_acked_psn[0x18];
3315
3316         u8         reserved_at_460[0x8];
3317         u8         ssn[0x18];
3318
3319         u8         reserved_at_480[0x8];
3320         u8         log_rra_max[0x3];
3321         u8         reserved_at_48b[0x1];
3322         u8         atomic_mode[0x4];
3323         u8         rre[0x1];
3324         u8         rwe[0x1];
3325         u8         rae[0x1];
3326         u8         reserved_at_493[0x1];
3327         u8         page_offset[0x6];
3328         u8         reserved_at_49a[0x3];
3329         u8         cd_slave_receive[0x1];
3330         u8         cd_slave_send[0x1];
3331         u8         cd_master[0x1];
3332
3333         u8         reserved_at_4a0[0x3];
3334         u8         min_rnr_nak[0x5];
3335         u8         next_rcv_psn[0x18];
3336
3337         u8         reserved_at_4c0[0x8];
3338         u8         xrcd[0x18];
3339
3340         u8         reserved_at_4e0[0x8];
3341         u8         cqn_rcv[0x18];
3342
3343         u8         dbr_addr[0x40];
3344
3345         u8         q_key[0x20];
3346
3347         u8         reserved_at_560[0x5];
3348         u8         rq_type[0x3];
3349         u8         srqn_rmpn_xrqn[0x18];
3350
3351         u8         reserved_at_580[0x8];
3352         u8         rmsn[0x18];
3353
3354         u8         hw_sq_wqebb_counter[0x10];
3355         u8         sw_sq_wqebb_counter[0x10];
3356
3357         u8         hw_rq_counter[0x20];
3358
3359         u8         sw_rq_counter[0x20];
3360
3361         u8         reserved_at_600[0x20];
3362
3363         u8         reserved_at_620[0xf];
3364         u8         cgs[0x1];
3365         u8         cs_req[0x8];
3366         u8         cs_res[0x8];
3367
3368         u8         dc_access_key[0x40];
3369
3370         u8         reserved_at_680[0x3];
3371         u8         dbr_umem_valid[0x1];
3372
3373         u8         reserved_at_684[0xbc];
3374 };
3375
3376 struct mlx5_ifc_roce_addr_layout_bits {
3377         u8         source_l3_address[16][0x8];
3378
3379         u8         reserved_at_80[0x3];
3380         u8         vlan_valid[0x1];
3381         u8         vlan_id[0xc];
3382         u8         source_mac_47_32[0x10];
3383
3384         u8         source_mac_31_0[0x20];
3385
3386         u8         reserved_at_c0[0x14];
3387         u8         roce_l3_type[0x4];
3388         u8         roce_version[0x8];
3389
3390         u8         reserved_at_e0[0x20];
3391 };
3392
3393 struct mlx5_ifc_shampo_cap_bits {
3394         u8    reserved_at_0[0x3];
3395         u8    shampo_log_max_reservation_size[0x5];
3396         u8    reserved_at_8[0x3];
3397         u8    shampo_log_min_reservation_size[0x5];
3398         u8    shampo_min_mss_size[0x10];
3399
3400         u8    reserved_at_20[0x3];
3401         u8    shampo_max_log_headers_entry_size[0x5];
3402         u8    reserved_at_28[0x18];
3403
3404         u8    reserved_at_40[0x7c0];
3405 };
3406
3407 struct mlx5_ifc_crypto_cap_bits {
3408         u8    reserved_at_0[0x3];
3409         u8    synchronize_dek[0x1];
3410         u8    int_kek_manual[0x1];
3411         u8    int_kek_auto[0x1];
3412         u8    reserved_at_6[0x1a];
3413
3414         u8    reserved_at_20[0x3];
3415         u8    log_dek_max_alloc[0x5];
3416         u8    reserved_at_28[0x3];
3417         u8    log_max_num_deks[0x5];
3418         u8    reserved_at_30[0x10];
3419
3420         u8    reserved_at_40[0x20];
3421
3422         u8    reserved_at_60[0x3];
3423         u8    log_dek_granularity[0x5];
3424         u8    reserved_at_68[0x3];
3425         u8    log_max_num_int_kek[0x5];
3426         u8    sw_wrapped_dek[0x10];
3427
3428         u8    reserved_at_80[0x780];
3429 };
3430
3431 union mlx5_ifc_hca_cap_union_bits {
3432         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3433         struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3434         struct mlx5_ifc_odp_cap_bits odp_cap;
3435         struct mlx5_ifc_atomic_caps_bits atomic_caps;
3436         struct mlx5_ifc_roce_cap_bits roce_cap;
3437         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3438         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3439         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3440         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3441         struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3442         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
3443         struct mlx5_ifc_qos_cap_bits qos_cap;
3444         struct mlx5_ifc_debug_cap_bits debug_cap;
3445         struct mlx5_ifc_fpga_cap_bits fpga_cap;
3446         struct mlx5_ifc_tls_cap_bits tls_cap;
3447         struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3448         struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3449         struct mlx5_ifc_shampo_cap_bits shampo_cap;
3450         struct mlx5_ifc_macsec_cap_bits macsec_cap;
3451         struct mlx5_ifc_crypto_cap_bits crypto_cap;
3452         u8         reserved_at_0[0x8000];
3453 };
3454
3455 enum {
3456         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
3457         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
3458         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
3459         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
3460         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3461         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3462         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3463         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3464         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3465         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3466         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3467         MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
3468         MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
3469         MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
3470 };
3471
3472 enum {
3473         MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3474         MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3475         MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3476 };
3477
3478 enum {
3479         MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC   = 0x0,
3480         MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC  = 0x1,
3481 };
3482
3483 struct mlx5_ifc_vlan_bits {
3484         u8         ethtype[0x10];
3485         u8         prio[0x3];
3486         u8         cfi[0x1];
3487         u8         vid[0xc];
3488 };
3489
3490 enum {
3491         MLX5_FLOW_METER_COLOR_RED       = 0x0,
3492         MLX5_FLOW_METER_COLOR_YELLOW    = 0x1,
3493         MLX5_FLOW_METER_COLOR_GREEN     = 0x2,
3494         MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3,
3495 };
3496
3497 enum {
3498         MLX5_EXE_ASO_FLOW_METER         = 0x2,
3499 };
3500
3501 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
3502         u8        return_reg_id[0x4];
3503         u8        aso_type[0x4];
3504         u8        reserved_at_8[0x14];
3505         u8        action[0x1];
3506         u8        init_color[0x2];
3507         u8        meter_id[0x1];
3508 };
3509
3510 union mlx5_ifc_exe_aso_ctrl {
3511         struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
3512 };
3513
3514 struct mlx5_ifc_execute_aso_bits {
3515         u8        valid[0x1];
3516         u8        reserved_at_1[0x7];
3517         u8        aso_object_id[0x18];
3518
3519         union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
3520 };
3521
3522 struct mlx5_ifc_flow_context_bits {
3523         struct mlx5_ifc_vlan_bits push_vlan;
3524
3525         u8         group_id[0x20];
3526
3527         u8         reserved_at_40[0x8];
3528         u8         flow_tag[0x18];
3529
3530         u8         reserved_at_60[0x10];
3531         u8         action[0x10];
3532
3533         u8         extended_destination[0x1];
3534         u8         reserved_at_81[0x1];
3535         u8         flow_source[0x2];
3536         u8         encrypt_decrypt_type[0x4];
3537         u8         destination_list_size[0x18];
3538
3539         u8         reserved_at_a0[0x8];
3540         u8         flow_counter_list_size[0x18];
3541
3542         u8         packet_reformat_id[0x20];
3543
3544         u8         modify_header_id[0x20];
3545
3546         struct mlx5_ifc_vlan_bits push_vlan_2;
3547
3548         u8         encrypt_decrypt_obj_id[0x20];
3549         u8         reserved_at_140[0xc0];
3550
3551         struct mlx5_ifc_fte_match_param_bits match_value;
3552
3553         struct mlx5_ifc_execute_aso_bits execute_aso[4];
3554
3555         u8         reserved_at_1300[0x500];
3556
3557         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3558 };
3559
3560 enum {
3561         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3562         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3563 };
3564
3565 struct mlx5_ifc_xrc_srqc_bits {
3566         u8         state[0x4];
3567         u8         log_xrc_srq_size[0x4];
3568         u8         reserved_at_8[0x18];
3569
3570         u8         wq_signature[0x1];
3571         u8         cont_srq[0x1];
3572         u8         reserved_at_22[0x1];
3573         u8         rlky[0x1];
3574         u8         basic_cyclic_rcv_wqe[0x1];
3575         u8         log_rq_stride[0x3];
3576         u8         xrcd[0x18];
3577
3578         u8         page_offset[0x6];
3579         u8         reserved_at_46[0x1];
3580         u8         dbr_umem_valid[0x1];
3581         u8         cqn[0x18];
3582
3583         u8         reserved_at_60[0x20];
3584
3585         u8         user_index_equal_xrc_srqn[0x1];
3586         u8         reserved_at_81[0x1];
3587         u8         log_page_size[0x6];
3588         u8         user_index[0x18];
3589
3590         u8         reserved_at_a0[0x20];
3591
3592         u8         reserved_at_c0[0x8];
3593         u8         pd[0x18];
3594
3595         u8         lwm[0x10];
3596         u8         wqe_cnt[0x10];
3597
3598         u8         reserved_at_100[0x40];
3599
3600         u8         db_record_addr_h[0x20];
3601
3602         u8         db_record_addr_l[0x1e];
3603         u8         reserved_at_17e[0x2];
3604
3605         u8         reserved_at_180[0x80];
3606 };
3607
3608 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3609         u8         counter_error_queues[0x20];
3610
3611         u8         total_error_queues[0x20];
3612
3613         u8         send_queue_priority_update_flow[0x20];
3614
3615         u8         reserved_at_60[0x20];
3616
3617         u8         nic_receive_steering_discard[0x40];
3618
3619         u8         receive_discard_vport_down[0x40];
3620
3621         u8         transmit_discard_vport_down[0x40];
3622
3623         u8         async_eq_overrun[0x20];
3624
3625         u8         comp_eq_overrun[0x20];
3626
3627         u8         reserved_at_180[0x20];
3628
3629         u8         invalid_command[0x20];
3630
3631         u8         quota_exceeded_command[0x20];
3632
3633         u8         internal_rq_out_of_buffer[0x20];
3634
3635         u8         cq_overrun[0x20];
3636
3637         u8         eth_wqe_too_small[0x20];
3638
3639         u8         reserved_at_220[0xdc0];
3640 };
3641
3642 struct mlx5_ifc_traffic_counter_bits {
3643         u8         packets[0x40];
3644
3645         u8         octets[0x40];
3646 };
3647
3648 struct mlx5_ifc_tisc_bits {
3649         u8         strict_lag_tx_port_affinity[0x1];
3650         u8         tls_en[0x1];
3651         u8         reserved_at_2[0x2];
3652         u8         lag_tx_port_affinity[0x04];
3653
3654         u8         reserved_at_8[0x4];
3655         u8         prio[0x4];
3656         u8         reserved_at_10[0x10];
3657
3658         u8         reserved_at_20[0x100];
3659
3660         u8         reserved_at_120[0x8];
3661         u8         transport_domain[0x18];
3662
3663         u8         reserved_at_140[0x8];
3664         u8         underlay_qpn[0x18];
3665
3666         u8         reserved_at_160[0x8];
3667         u8         pd[0x18];
3668
3669         u8         reserved_at_180[0x380];
3670 };
3671
3672 enum {
3673         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3674         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3675 };
3676
3677 enum {
3678         MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO  = BIT(0),
3679         MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO  = BIT(1),
3680 };
3681
3682 enum {
3683         MLX5_RX_HASH_FN_NONE           = 0x0,
3684         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
3685         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
3686 };
3687
3688 enum {
3689         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
3690         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
3691 };
3692
3693 struct mlx5_ifc_tirc_bits {
3694         u8         reserved_at_0[0x20];
3695
3696         u8         disp_type[0x4];
3697         u8         tls_en[0x1];
3698         u8         reserved_at_25[0x1b];
3699
3700         u8         reserved_at_40[0x40];
3701
3702         u8         reserved_at_80[0x4];
3703         u8         lro_timeout_period_usecs[0x10];
3704         u8         packet_merge_mask[0x4];
3705         u8         lro_max_ip_payload_size[0x8];
3706
3707         u8         reserved_at_a0[0x40];
3708
3709         u8         reserved_at_e0[0x8];
3710         u8         inline_rqn[0x18];
3711
3712         u8         rx_hash_symmetric[0x1];
3713         u8         reserved_at_101[0x1];
3714         u8         tunneled_offload_en[0x1];
3715         u8         reserved_at_103[0x5];
3716         u8         indirect_table[0x18];
3717
3718         u8         rx_hash_fn[0x4];
3719         u8         reserved_at_124[0x2];
3720         u8         self_lb_block[0x2];
3721         u8         transport_domain[0x18];
3722
3723         u8         rx_hash_toeplitz_key[10][0x20];
3724
3725         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3726
3727         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3728
3729         u8         reserved_at_2c0[0x4c0];
3730 };
3731
3732 enum {
3733         MLX5_SRQC_STATE_GOOD   = 0x0,
3734         MLX5_SRQC_STATE_ERROR  = 0x1,
3735 };
3736
3737 struct mlx5_ifc_srqc_bits {
3738         u8         state[0x4];
3739         u8         log_srq_size[0x4];
3740         u8         reserved_at_8[0x18];
3741
3742         u8         wq_signature[0x1];
3743         u8         cont_srq[0x1];
3744         u8         reserved_at_22[0x1];
3745         u8         rlky[0x1];
3746         u8         reserved_at_24[0x1];
3747         u8         log_rq_stride[0x3];
3748         u8         xrcd[0x18];
3749
3750         u8         page_offset[0x6];
3751         u8         reserved_at_46[0x2];
3752         u8         cqn[0x18];
3753
3754         u8         reserved_at_60[0x20];
3755
3756         u8         reserved_at_80[0x2];
3757         u8         log_page_size[0x6];
3758         u8         reserved_at_88[0x18];
3759
3760         u8         reserved_at_a0[0x20];
3761
3762         u8         reserved_at_c0[0x8];
3763         u8         pd[0x18];
3764
3765         u8         lwm[0x10];
3766         u8         wqe_cnt[0x10];
3767
3768         u8         reserved_at_100[0x40];
3769
3770         u8         dbr_addr[0x40];
3771
3772         u8         reserved_at_180[0x80];
3773 };
3774
3775 enum {
3776         MLX5_SQC_STATE_RST  = 0x0,
3777         MLX5_SQC_STATE_RDY  = 0x1,
3778         MLX5_SQC_STATE_ERR  = 0x3,
3779 };
3780
3781 struct mlx5_ifc_sqc_bits {
3782         u8         rlky[0x1];
3783         u8         cd_master[0x1];
3784         u8         fre[0x1];
3785         u8         flush_in_error_en[0x1];
3786         u8         allow_multi_pkt_send_wqe[0x1];
3787         u8         min_wqe_inline_mode[0x3];
3788         u8         state[0x4];
3789         u8         reg_umr[0x1];
3790         u8         allow_swp[0x1];
3791         u8         hairpin[0x1];
3792         u8         reserved_at_f[0xb];
3793         u8         ts_format[0x2];
3794         u8         reserved_at_1c[0x4];
3795
3796         u8         reserved_at_20[0x8];
3797         u8         user_index[0x18];
3798
3799         u8         reserved_at_40[0x8];
3800         u8         cqn[0x18];
3801
3802         u8         reserved_at_60[0x8];
3803         u8         hairpin_peer_rq[0x18];
3804
3805         u8         reserved_at_80[0x10];
3806         u8         hairpin_peer_vhca[0x10];
3807
3808         u8         reserved_at_a0[0x20];
3809
3810         u8         reserved_at_c0[0x8];
3811         u8         ts_cqe_to_dest_cqn[0x18];
3812
3813         u8         reserved_at_e0[0x10];
3814         u8         packet_pacing_rate_limit_index[0x10];
3815         u8         tis_lst_sz[0x10];
3816         u8         qos_queue_group_id[0x10];
3817
3818         u8         reserved_at_120[0x40];
3819
3820         u8         reserved_at_160[0x8];
3821         u8         tis_num_0[0x18];
3822
3823         struct mlx5_ifc_wq_bits wq;
3824 };
3825
3826 enum {
3827         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3828         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3829         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3830         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3831         SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
3832 };
3833
3834 enum {
3835         ELEMENT_TYPE_CAP_MASK_TASR              = 1 << 0,
3836         ELEMENT_TYPE_CAP_MASK_VPORT             = 1 << 1,
3837         ELEMENT_TYPE_CAP_MASK_VPORT_TC          = 1 << 2,
3838         ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC     = 1 << 3,
3839 };
3840
3841 struct mlx5_ifc_scheduling_context_bits {
3842         u8         element_type[0x8];
3843         u8         reserved_at_8[0x18];
3844
3845         u8         element_attributes[0x20];
3846
3847         u8         parent_element_id[0x20];
3848
3849         u8         reserved_at_60[0x40];
3850
3851         u8         bw_share[0x20];
3852
3853         u8         max_average_bw[0x20];
3854
3855         u8         reserved_at_e0[0x120];
3856 };
3857
3858 struct mlx5_ifc_rqtc_bits {
3859         u8    reserved_at_0[0xa0];
3860
3861         u8    reserved_at_a0[0x5];
3862         u8    list_q_type[0x3];
3863         u8    reserved_at_a8[0x8];
3864         u8    rqt_max_size[0x10];
3865
3866         u8    rq_vhca_id_format[0x1];
3867         u8    reserved_at_c1[0xf];
3868         u8    rqt_actual_size[0x10];
3869
3870         u8    reserved_at_e0[0x6a0];
3871
3872         struct mlx5_ifc_rq_num_bits rq_num[];
3873 };
3874
3875 enum {
3876         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3877         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3878 };
3879
3880 enum {
3881         MLX5_RQC_STATE_RST  = 0x0,
3882         MLX5_RQC_STATE_RDY  = 0x1,
3883         MLX5_RQC_STATE_ERR  = 0x3,
3884 };
3885
3886 enum {
3887         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE    = 0x0,
3888         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE  = 0x1,
3889         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE    = 0x2,
3890 };
3891
3892 enum {
3893         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH    = 0x0,
3894         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED    = 0x1,
3895         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE  = 0x2,
3896 };
3897
3898 struct mlx5_ifc_rqc_bits {
3899         u8         rlky[0x1];
3900         u8         delay_drop_en[0x1];
3901         u8         scatter_fcs[0x1];
3902         u8         vsd[0x1];
3903         u8         mem_rq_type[0x4];
3904         u8         state[0x4];
3905         u8         reserved_at_c[0x1];
3906         u8         flush_in_error_en[0x1];
3907         u8         hairpin[0x1];
3908         u8         reserved_at_f[0xb];
3909         u8         ts_format[0x2];
3910         u8         reserved_at_1c[0x4];
3911
3912         u8         reserved_at_20[0x8];
3913         u8         user_index[0x18];
3914
3915         u8         reserved_at_40[0x8];
3916         u8         cqn[0x18];
3917
3918         u8         counter_set_id[0x8];
3919         u8         reserved_at_68[0x18];
3920
3921         u8         reserved_at_80[0x8];
3922         u8         rmpn[0x18];
3923
3924         u8         reserved_at_a0[0x8];
3925         u8         hairpin_peer_sq[0x18];
3926
3927         u8         reserved_at_c0[0x10];
3928         u8         hairpin_peer_vhca[0x10];
3929
3930         u8         reserved_at_e0[0x46];
3931         u8         shampo_no_match_alignment_granularity[0x2];
3932         u8         reserved_at_128[0x6];
3933         u8         shampo_match_criteria_type[0x2];
3934         u8         reservation_timeout[0x10];
3935
3936         u8         reserved_at_140[0x40];
3937
3938         struct mlx5_ifc_wq_bits wq;
3939 };
3940
3941 enum {
3942         MLX5_RMPC_STATE_RDY  = 0x1,
3943         MLX5_RMPC_STATE_ERR  = 0x3,
3944 };
3945
3946 struct mlx5_ifc_rmpc_bits {
3947         u8         reserved_at_0[0x8];
3948         u8         state[0x4];
3949         u8         reserved_at_c[0x14];
3950
3951         u8         basic_cyclic_rcv_wqe[0x1];
3952         u8         reserved_at_21[0x1f];
3953
3954         u8         reserved_at_40[0x140];
3955
3956         struct mlx5_ifc_wq_bits wq;
3957 };
3958
3959 enum {
3960         VHCA_ID_TYPE_HW = 0,
3961         VHCA_ID_TYPE_SW = 1,
3962 };
3963
3964 struct mlx5_ifc_nic_vport_context_bits {
3965         u8         reserved_at_0[0x5];
3966         u8         min_wqe_inline_mode[0x3];
3967         u8         reserved_at_8[0x15];
3968         u8         disable_mc_local_lb[0x1];
3969         u8         disable_uc_local_lb[0x1];
3970         u8         roce_en[0x1];
3971
3972         u8         arm_change_event[0x1];
3973         u8         reserved_at_21[0x1a];
3974         u8         event_on_mtu[0x1];
3975         u8         event_on_promisc_change[0x1];
3976         u8         event_on_vlan_change[0x1];
3977         u8         event_on_mc_address_change[0x1];
3978         u8         event_on_uc_address_change[0x1];
3979
3980         u8         vhca_id_type[0x1];
3981         u8         reserved_at_41[0xb];
3982         u8         affiliation_criteria[0x4];
3983         u8         affiliated_vhca_id[0x10];
3984
3985         u8         reserved_at_60[0xd0];
3986
3987         u8         mtu[0x10];
3988
3989         u8         system_image_guid[0x40];
3990         u8         port_guid[0x40];
3991         u8         node_guid[0x40];
3992
3993         u8         reserved_at_200[0x140];
3994         u8         qkey_violation_counter[0x10];
3995         u8         reserved_at_350[0x430];
3996
3997         u8         promisc_uc[0x1];
3998         u8         promisc_mc[0x1];
3999         u8         promisc_all[0x1];
4000         u8         reserved_at_783[0x2];
4001         u8         allowed_list_type[0x3];
4002         u8         reserved_at_788[0xc];
4003         u8         allowed_list_size[0xc];
4004
4005         struct mlx5_ifc_mac_address_layout_bits permanent_address;
4006
4007         u8         reserved_at_7e0[0x20];
4008
4009         u8         current_uc_mac_address[][0x40];
4010 };
4011
4012 enum {
4013         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
4014         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
4015         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
4016         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
4017         MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
4018         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
4019 };
4020
4021 struct mlx5_ifc_mkc_bits {
4022         u8         reserved_at_0[0x1];
4023         u8         free[0x1];
4024         u8         reserved_at_2[0x1];
4025         u8         access_mode_4_2[0x3];
4026         u8         reserved_at_6[0x7];
4027         u8         relaxed_ordering_write[0x1];
4028         u8         reserved_at_e[0x1];
4029         u8         small_fence_on_rdma_read_response[0x1];
4030         u8         umr_en[0x1];
4031         u8         a[0x1];
4032         u8         rw[0x1];
4033         u8         rr[0x1];
4034         u8         lw[0x1];
4035         u8         lr[0x1];
4036         u8         access_mode_1_0[0x2];
4037         u8         reserved_at_18[0x2];
4038         u8         ma_translation_mode[0x2];
4039         u8         reserved_at_1c[0x4];
4040
4041         u8         qpn[0x18];
4042         u8         mkey_7_0[0x8];
4043
4044         u8         reserved_at_40[0x20];
4045
4046         u8         length64[0x1];
4047         u8         bsf_en[0x1];
4048         u8         sync_umr[0x1];
4049         u8         reserved_at_63[0x2];
4050         u8         expected_sigerr_count[0x1];
4051         u8         reserved_at_66[0x1];
4052         u8         en_rinval[0x1];
4053         u8         pd[0x18];
4054
4055         u8         start_addr[0x40];
4056
4057         u8         len[0x40];
4058
4059         u8         bsf_octword_size[0x20];
4060
4061         u8         reserved_at_120[0x80];
4062
4063         u8         translations_octword_size[0x20];
4064
4065         u8         reserved_at_1c0[0x19];
4066         u8         relaxed_ordering_read[0x1];
4067         u8         reserved_at_1d9[0x1];
4068         u8         log_page_size[0x5];
4069
4070         u8         reserved_at_1e0[0x20];
4071 };
4072
4073 struct mlx5_ifc_pkey_bits {
4074         u8         reserved_at_0[0x10];
4075         u8         pkey[0x10];
4076 };
4077
4078 struct mlx5_ifc_array128_auto_bits {
4079         u8         array128_auto[16][0x8];
4080 };
4081
4082 struct mlx5_ifc_hca_vport_context_bits {
4083         u8         field_select[0x20];
4084
4085         u8         reserved_at_20[0xe0];
4086
4087         u8         sm_virt_aware[0x1];
4088         u8         has_smi[0x1];
4089         u8         has_raw[0x1];
4090         u8         grh_required[0x1];
4091         u8         reserved_at_104[0xc];
4092         u8         port_physical_state[0x4];
4093         u8         vport_state_policy[0x4];
4094         u8         port_state[0x4];
4095         u8         vport_state[0x4];
4096
4097         u8         reserved_at_120[0x20];
4098
4099         u8         system_image_guid[0x40];
4100
4101         u8         port_guid[0x40];
4102
4103         u8         node_guid[0x40];
4104
4105         u8         cap_mask1[0x20];
4106
4107         u8         cap_mask1_field_select[0x20];
4108
4109         u8         cap_mask2[0x20];
4110
4111         u8         cap_mask2_field_select[0x20];
4112
4113         u8         reserved_at_280[0x80];
4114
4115         u8         lid[0x10];
4116         u8         reserved_at_310[0x4];
4117         u8         init_type_reply[0x4];
4118         u8         lmc[0x3];
4119         u8         subnet_timeout[0x5];
4120
4121         u8         sm_lid[0x10];
4122         u8         sm_sl[0x4];
4123         u8         reserved_at_334[0xc];
4124
4125         u8         qkey_violation_counter[0x10];
4126         u8         pkey_violation_counter[0x10];
4127
4128         u8         reserved_at_360[0xca0];
4129 };
4130
4131 struct mlx5_ifc_esw_vport_context_bits {
4132         u8         fdb_to_vport_reg_c[0x1];
4133         u8         reserved_at_1[0x2];
4134         u8         vport_svlan_strip[0x1];
4135         u8         vport_cvlan_strip[0x1];
4136         u8         vport_svlan_insert[0x1];
4137         u8         vport_cvlan_insert[0x2];
4138         u8         fdb_to_vport_reg_c_id[0x8];
4139         u8         reserved_at_10[0x10];
4140
4141         u8         reserved_at_20[0x20];
4142
4143         u8         svlan_cfi[0x1];
4144         u8         svlan_pcp[0x3];
4145         u8         svlan_id[0xc];
4146         u8         cvlan_cfi[0x1];
4147         u8         cvlan_pcp[0x3];
4148         u8         cvlan_id[0xc];
4149
4150         u8         reserved_at_60[0x720];
4151
4152         u8         sw_steering_vport_icm_address_rx[0x40];
4153
4154         u8         sw_steering_vport_icm_address_tx[0x40];
4155 };
4156
4157 enum {
4158         MLX5_EQC_STATUS_OK                = 0x0,
4159         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
4160 };
4161
4162 enum {
4163         MLX5_EQC_ST_ARMED  = 0x9,
4164         MLX5_EQC_ST_FIRED  = 0xa,
4165 };
4166
4167 struct mlx5_ifc_eqc_bits {
4168         u8         status[0x4];
4169         u8         reserved_at_4[0x9];
4170         u8         ec[0x1];
4171         u8         oi[0x1];
4172         u8         reserved_at_f[0x5];
4173         u8         st[0x4];
4174         u8         reserved_at_18[0x8];
4175
4176         u8         reserved_at_20[0x20];
4177
4178         u8         reserved_at_40[0x14];
4179         u8         page_offset[0x6];
4180         u8         reserved_at_5a[0x6];
4181
4182         u8         reserved_at_60[0x3];
4183         u8         log_eq_size[0x5];
4184         u8         uar_page[0x18];
4185
4186         u8         reserved_at_80[0x20];
4187
4188         u8         reserved_at_a0[0x14];
4189         u8         intr[0xc];
4190
4191         u8         reserved_at_c0[0x3];
4192         u8         log_page_size[0x5];
4193         u8         reserved_at_c8[0x18];
4194
4195         u8         reserved_at_e0[0x60];
4196
4197         u8         reserved_at_140[0x8];
4198         u8         consumer_counter[0x18];
4199
4200         u8         reserved_at_160[0x8];
4201         u8         producer_counter[0x18];
4202
4203         u8         reserved_at_180[0x80];
4204 };
4205
4206 enum {
4207         MLX5_DCTC_STATE_ACTIVE    = 0x0,
4208         MLX5_DCTC_STATE_DRAINING  = 0x1,
4209         MLX5_DCTC_STATE_DRAINED   = 0x2,
4210 };
4211
4212 enum {
4213         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
4214         MLX5_DCTC_CS_RES_NA         = 0x1,
4215         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
4216 };
4217
4218 enum {
4219         MLX5_DCTC_MTU_256_BYTES  = 0x1,
4220         MLX5_DCTC_MTU_512_BYTES  = 0x2,
4221         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
4222         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
4223         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
4224 };
4225
4226 struct mlx5_ifc_dctc_bits {
4227         u8         reserved_at_0[0x4];
4228         u8         state[0x4];
4229         u8         reserved_at_8[0x18];
4230
4231         u8         reserved_at_20[0x8];
4232         u8         user_index[0x18];
4233
4234         u8         reserved_at_40[0x8];
4235         u8         cqn[0x18];
4236
4237         u8         counter_set_id[0x8];
4238         u8         atomic_mode[0x4];
4239         u8         rre[0x1];
4240         u8         rwe[0x1];
4241         u8         rae[0x1];
4242         u8         atomic_like_write_en[0x1];
4243         u8         latency_sensitive[0x1];
4244         u8         rlky[0x1];
4245         u8         free_ar[0x1];
4246         u8         reserved_at_73[0xd];
4247
4248         u8         reserved_at_80[0x8];
4249         u8         cs_res[0x8];
4250         u8         reserved_at_90[0x3];
4251         u8         min_rnr_nak[0x5];
4252         u8         reserved_at_98[0x8];
4253
4254         u8         reserved_at_a0[0x8];
4255         u8         srqn_xrqn[0x18];
4256
4257         u8         reserved_at_c0[0x8];
4258         u8         pd[0x18];
4259
4260         u8         tclass[0x8];
4261         u8         reserved_at_e8[0x4];
4262         u8         flow_label[0x14];
4263
4264         u8         dc_access_key[0x40];
4265
4266         u8         reserved_at_140[0x5];
4267         u8         mtu[0x3];
4268         u8         port[0x8];
4269         u8         pkey_index[0x10];
4270
4271         u8         reserved_at_160[0x8];
4272         u8         my_addr_index[0x8];
4273         u8         reserved_at_170[0x8];
4274         u8         hop_limit[0x8];
4275
4276         u8         dc_access_key_violation_count[0x20];
4277
4278         u8         reserved_at_1a0[0x14];
4279         u8         dei_cfi[0x1];
4280         u8         eth_prio[0x3];
4281         u8         ecn[0x2];
4282         u8         dscp[0x6];
4283
4284         u8         reserved_at_1c0[0x20];
4285         u8         ece[0x20];
4286 };
4287
4288 enum {
4289         MLX5_CQC_STATUS_OK             = 0x0,
4290         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
4291         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
4292 };
4293
4294 enum {
4295         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
4296         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
4297 };
4298
4299 enum {
4300         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
4301         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
4302         MLX5_CQC_ST_FIRED                                 = 0xa,
4303 };
4304
4305 enum {
4306         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4307         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4308         MLX5_CQ_PERIOD_NUM_MODES
4309 };
4310
4311 struct mlx5_ifc_cqc_bits {
4312         u8         status[0x4];
4313         u8         reserved_at_4[0x2];
4314         u8         dbr_umem_valid[0x1];
4315         u8         apu_cq[0x1];
4316         u8         cqe_sz[0x3];
4317         u8         cc[0x1];
4318         u8         reserved_at_c[0x1];
4319         u8         scqe_break_moderation_en[0x1];
4320         u8         oi[0x1];
4321         u8         cq_period_mode[0x2];
4322         u8         cqe_comp_en[0x1];
4323         u8         mini_cqe_res_format[0x2];
4324         u8         st[0x4];
4325         u8         reserved_at_18[0x6];
4326         u8         cqe_compression_layout[0x2];
4327
4328         u8         reserved_at_20[0x20];
4329
4330         u8         reserved_at_40[0x14];
4331         u8         page_offset[0x6];
4332         u8         reserved_at_5a[0x6];
4333
4334         u8         reserved_at_60[0x3];
4335         u8         log_cq_size[0x5];
4336         u8         uar_page[0x18];
4337
4338         u8         reserved_at_80[0x4];
4339         u8         cq_period[0xc];
4340         u8         cq_max_count[0x10];
4341
4342         u8         c_eqn_or_apu_element[0x20];
4343
4344         u8         reserved_at_c0[0x3];
4345         u8         log_page_size[0x5];
4346         u8         reserved_at_c8[0x18];
4347
4348         u8         reserved_at_e0[0x20];
4349
4350         u8         reserved_at_100[0x8];
4351         u8         last_notified_index[0x18];
4352
4353         u8         reserved_at_120[0x8];
4354         u8         last_solicit_index[0x18];
4355
4356         u8         reserved_at_140[0x8];
4357         u8         consumer_counter[0x18];
4358
4359         u8         reserved_at_160[0x8];
4360         u8         producer_counter[0x18];
4361
4362         u8         reserved_at_180[0x40];
4363
4364         u8         dbr_addr[0x40];
4365 };
4366
4367 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4368         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4369         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4370         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4371         struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general;
4372         u8         reserved_at_0[0x800];
4373 };
4374
4375 struct mlx5_ifc_query_adapter_param_block_bits {
4376         u8         reserved_at_0[0xc0];
4377
4378         u8         reserved_at_c0[0x8];
4379         u8         ieee_vendor_id[0x18];
4380
4381         u8         reserved_at_e0[0x10];
4382         u8         vsd_vendor_id[0x10];
4383
4384         u8         vsd[208][0x8];
4385
4386         u8         vsd_contd_psid[16][0x8];
4387 };
4388
4389 enum {
4390         MLX5_XRQC_STATE_GOOD   = 0x0,
4391         MLX5_XRQC_STATE_ERROR  = 0x1,
4392 };
4393
4394 enum {
4395         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4396         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
4397 };
4398
4399 enum {
4400         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4401 };
4402
4403 struct mlx5_ifc_tag_matching_topology_context_bits {
4404         u8         log_matching_list_sz[0x4];
4405         u8         reserved_at_4[0xc];
4406         u8         append_next_index[0x10];
4407
4408         u8         sw_phase_cnt[0x10];
4409         u8         hw_phase_cnt[0x10];
4410
4411         u8         reserved_at_40[0x40];
4412 };
4413
4414 struct mlx5_ifc_xrqc_bits {
4415         u8         state[0x4];
4416         u8         rlkey[0x1];
4417         u8         reserved_at_5[0xf];
4418         u8         topology[0x4];
4419         u8         reserved_at_18[0x4];
4420         u8         offload[0x4];
4421
4422         u8         reserved_at_20[0x8];
4423         u8         user_index[0x18];
4424
4425         u8         reserved_at_40[0x8];
4426         u8         cqn[0x18];
4427
4428         u8         reserved_at_60[0xa0];
4429
4430         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4431
4432         u8         reserved_at_180[0x280];
4433
4434         struct mlx5_ifc_wq_bits wq;
4435 };
4436
4437 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4438         struct mlx5_ifc_modify_field_select_bits modify_field_select;
4439         struct mlx5_ifc_resize_field_select_bits resize_field_select;
4440         u8         reserved_at_0[0x20];
4441 };
4442
4443 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4444         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4445         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4446         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4447         u8         reserved_at_0[0x20];
4448 };
4449
4450 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4451         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4452         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4453         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4454         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4455         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4456         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4457         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4458         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4459         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4460         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4461         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4462         u8         reserved_at_0[0x7c0];
4463 };
4464
4465 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4466         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4467         u8         reserved_at_0[0x7c0];
4468 };
4469
4470 union mlx5_ifc_event_auto_bits {
4471         struct mlx5_ifc_comp_event_bits comp_event;
4472         struct mlx5_ifc_dct_events_bits dct_events;
4473         struct mlx5_ifc_qp_events_bits qp_events;
4474         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4475         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4476         struct mlx5_ifc_cq_error_bits cq_error;
4477         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4478         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4479         struct mlx5_ifc_gpio_event_bits gpio_event;
4480         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4481         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4482         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4483         u8         reserved_at_0[0xe0];
4484 };
4485
4486 struct mlx5_ifc_health_buffer_bits {
4487         u8         reserved_at_0[0x100];
4488
4489         u8         assert_existptr[0x20];
4490
4491         u8         assert_callra[0x20];
4492
4493         u8         reserved_at_140[0x20];
4494
4495         u8         time[0x20];
4496
4497         u8         fw_version[0x20];
4498
4499         u8         hw_id[0x20];
4500
4501         u8         rfr[0x1];
4502         u8         reserved_at_1c1[0x3];
4503         u8         valid[0x1];
4504         u8         severity[0x3];
4505         u8         reserved_at_1c8[0x18];
4506
4507         u8         irisc_index[0x8];
4508         u8         synd[0x8];
4509         u8         ext_synd[0x10];
4510 };
4511
4512 struct mlx5_ifc_register_loopback_control_bits {
4513         u8         no_lb[0x1];
4514         u8         reserved_at_1[0x7];
4515         u8         port[0x8];
4516         u8         reserved_at_10[0x10];
4517
4518         u8         reserved_at_20[0x60];
4519 };
4520
4521 struct mlx5_ifc_vport_tc_element_bits {
4522         u8         traffic_class[0x4];
4523         u8         reserved_at_4[0xc];
4524         u8         vport_number[0x10];
4525 };
4526
4527 struct mlx5_ifc_vport_element_bits {
4528         u8         reserved_at_0[0x10];
4529         u8         vport_number[0x10];
4530 };
4531
4532 enum {
4533         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4534         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4535         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4536 };
4537
4538 struct mlx5_ifc_tsar_element_bits {
4539         u8         reserved_at_0[0x8];
4540         u8         tsar_type[0x8];
4541         u8         reserved_at_10[0x10];
4542 };
4543
4544 enum {
4545         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4546         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4547 };
4548
4549 struct mlx5_ifc_teardown_hca_out_bits {
4550         u8         status[0x8];
4551         u8         reserved_at_8[0x18];
4552
4553         u8         syndrome[0x20];
4554
4555         u8         reserved_at_40[0x3f];
4556
4557         u8         state[0x1];
4558 };
4559
4560 enum {
4561         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
4562         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
4563         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4564 };
4565
4566 struct mlx5_ifc_teardown_hca_in_bits {
4567         u8         opcode[0x10];
4568         u8         reserved_at_10[0x10];
4569
4570         u8         reserved_at_20[0x10];
4571         u8         op_mod[0x10];
4572
4573         u8         reserved_at_40[0x10];
4574         u8         profile[0x10];
4575
4576         u8         reserved_at_60[0x20];
4577 };
4578
4579 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4580         u8         status[0x8];
4581         u8         reserved_at_8[0x18];
4582
4583         u8         syndrome[0x20];
4584
4585         u8         reserved_at_40[0x40];
4586 };
4587
4588 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4589         u8         opcode[0x10];
4590         u8         uid[0x10];
4591
4592         u8         reserved_at_20[0x10];
4593         u8         op_mod[0x10];
4594
4595         u8         reserved_at_40[0x8];
4596         u8         qpn[0x18];
4597
4598         u8         reserved_at_60[0x20];
4599
4600         u8         opt_param_mask[0x20];
4601
4602         u8         reserved_at_a0[0x20];
4603
4604         struct mlx5_ifc_qpc_bits qpc;
4605
4606         u8         reserved_at_800[0x80];
4607 };
4608
4609 struct mlx5_ifc_sqd2rts_qp_out_bits {
4610         u8         status[0x8];
4611         u8         reserved_at_8[0x18];
4612
4613         u8         syndrome[0x20];
4614
4615         u8         reserved_at_40[0x40];
4616 };
4617
4618 struct mlx5_ifc_sqd2rts_qp_in_bits {
4619         u8         opcode[0x10];
4620         u8         uid[0x10];
4621
4622         u8         reserved_at_20[0x10];
4623         u8         op_mod[0x10];
4624
4625         u8         reserved_at_40[0x8];
4626         u8         qpn[0x18];
4627
4628         u8         reserved_at_60[0x20];
4629
4630         u8         opt_param_mask[0x20];
4631
4632         u8         reserved_at_a0[0x20];
4633
4634         struct mlx5_ifc_qpc_bits qpc;
4635
4636         u8         reserved_at_800[0x80];
4637 };
4638
4639 struct mlx5_ifc_set_roce_address_out_bits {
4640         u8         status[0x8];
4641         u8         reserved_at_8[0x18];
4642
4643         u8         syndrome[0x20];
4644
4645         u8         reserved_at_40[0x40];
4646 };
4647
4648 struct mlx5_ifc_set_roce_address_in_bits {
4649         u8         opcode[0x10];
4650         u8         reserved_at_10[0x10];
4651
4652         u8         reserved_at_20[0x10];
4653         u8         op_mod[0x10];
4654
4655         u8         roce_address_index[0x10];
4656         u8         reserved_at_50[0xc];
4657         u8         vhca_port_num[0x4];
4658
4659         u8         reserved_at_60[0x20];
4660
4661         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4662 };
4663
4664 struct mlx5_ifc_set_mad_demux_out_bits {
4665         u8         status[0x8];
4666         u8         reserved_at_8[0x18];
4667
4668         u8         syndrome[0x20];
4669
4670         u8         reserved_at_40[0x40];
4671 };
4672
4673 enum {
4674         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4675         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4676 };
4677
4678 struct mlx5_ifc_set_mad_demux_in_bits {
4679         u8         opcode[0x10];
4680         u8         reserved_at_10[0x10];
4681
4682         u8         reserved_at_20[0x10];
4683         u8         op_mod[0x10];
4684
4685         u8         reserved_at_40[0x20];
4686
4687         u8         reserved_at_60[0x6];
4688         u8         demux_mode[0x2];
4689         u8         reserved_at_68[0x18];
4690 };
4691
4692 struct mlx5_ifc_set_l2_table_entry_out_bits {
4693         u8         status[0x8];
4694         u8         reserved_at_8[0x18];
4695
4696         u8         syndrome[0x20];
4697
4698         u8         reserved_at_40[0x40];
4699 };
4700
4701 struct mlx5_ifc_set_l2_table_entry_in_bits {
4702         u8         opcode[0x10];
4703         u8         reserved_at_10[0x10];
4704
4705         u8         reserved_at_20[0x10];
4706         u8         op_mod[0x10];
4707
4708         u8         reserved_at_40[0x60];
4709
4710         u8         reserved_at_a0[0x8];
4711         u8         table_index[0x18];
4712
4713         u8         reserved_at_c0[0x20];
4714
4715         u8         reserved_at_e0[0x13];
4716         u8         vlan_valid[0x1];
4717         u8         vlan[0xc];
4718
4719         struct mlx5_ifc_mac_address_layout_bits mac_address;
4720
4721         u8         reserved_at_140[0xc0];
4722 };
4723
4724 struct mlx5_ifc_set_issi_out_bits {
4725         u8         status[0x8];
4726         u8         reserved_at_8[0x18];
4727
4728         u8         syndrome[0x20];
4729
4730         u8         reserved_at_40[0x40];
4731 };
4732
4733 struct mlx5_ifc_set_issi_in_bits {
4734         u8         opcode[0x10];
4735         u8         reserved_at_10[0x10];
4736
4737         u8         reserved_at_20[0x10];
4738         u8         op_mod[0x10];
4739
4740         u8         reserved_at_40[0x10];
4741         u8         current_issi[0x10];
4742
4743         u8         reserved_at_60[0x20];
4744 };
4745
4746 struct mlx5_ifc_set_hca_cap_out_bits {
4747         u8         status[0x8];
4748         u8         reserved_at_8[0x18];
4749
4750         u8         syndrome[0x20];
4751
4752         u8         reserved_at_40[0x40];
4753 };
4754
4755 struct mlx5_ifc_set_hca_cap_in_bits {
4756         u8         opcode[0x10];
4757         u8         reserved_at_10[0x10];
4758
4759         u8         reserved_at_20[0x10];
4760         u8         op_mod[0x10];
4761
4762         u8         other_function[0x1];
4763         u8         reserved_at_41[0xf];
4764         u8         function_id[0x10];
4765
4766         u8         reserved_at_60[0x20];
4767
4768         union mlx5_ifc_hca_cap_union_bits capability;
4769 };
4770
4771 enum {
4772         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
4773         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
4774         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
4775         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
4776         MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
4777 };
4778
4779 struct mlx5_ifc_set_fte_out_bits {
4780         u8         status[0x8];
4781         u8         reserved_at_8[0x18];
4782
4783         u8         syndrome[0x20];
4784
4785         u8         reserved_at_40[0x40];
4786 };
4787
4788 struct mlx5_ifc_set_fte_in_bits {
4789         u8         opcode[0x10];
4790         u8         reserved_at_10[0x10];
4791
4792         u8         reserved_at_20[0x10];
4793         u8         op_mod[0x10];
4794
4795         u8         other_vport[0x1];
4796         u8         reserved_at_41[0xf];
4797         u8         vport_number[0x10];
4798
4799         u8         reserved_at_60[0x20];
4800
4801         u8         table_type[0x8];
4802         u8         reserved_at_88[0x18];
4803
4804         u8         reserved_at_a0[0x8];
4805         u8         table_id[0x18];
4806
4807         u8         ignore_flow_level[0x1];
4808         u8         reserved_at_c1[0x17];
4809         u8         modify_enable_mask[0x8];
4810
4811         u8         reserved_at_e0[0x20];
4812
4813         u8         flow_index[0x20];
4814
4815         u8         reserved_at_120[0xe0];
4816
4817         struct mlx5_ifc_flow_context_bits flow_context;
4818 };
4819
4820 struct mlx5_ifc_rts2rts_qp_out_bits {
4821         u8         status[0x8];
4822         u8         reserved_at_8[0x18];
4823
4824         u8         syndrome[0x20];
4825
4826         u8         reserved_at_40[0x20];
4827         u8         ece[0x20];
4828 };
4829
4830 struct mlx5_ifc_rts2rts_qp_in_bits {
4831         u8         opcode[0x10];
4832         u8         uid[0x10];
4833
4834         u8         reserved_at_20[0x10];
4835         u8         op_mod[0x10];
4836
4837         u8         reserved_at_40[0x8];
4838         u8         qpn[0x18];
4839
4840         u8         reserved_at_60[0x20];
4841
4842         u8         opt_param_mask[0x20];
4843
4844         u8         ece[0x20];
4845
4846         struct mlx5_ifc_qpc_bits qpc;
4847
4848         u8         reserved_at_800[0x80];
4849 };
4850
4851 struct mlx5_ifc_rtr2rts_qp_out_bits {
4852         u8         status[0x8];
4853         u8         reserved_at_8[0x18];
4854
4855         u8         syndrome[0x20];
4856
4857         u8         reserved_at_40[0x20];
4858         u8         ece[0x20];
4859 };
4860
4861 struct mlx5_ifc_rtr2rts_qp_in_bits {
4862         u8         opcode[0x10];
4863         u8         uid[0x10];
4864
4865         u8         reserved_at_20[0x10];
4866         u8         op_mod[0x10];
4867
4868         u8         reserved_at_40[0x8];
4869         u8         qpn[0x18];
4870
4871         u8         reserved_at_60[0x20];
4872
4873         u8         opt_param_mask[0x20];
4874
4875         u8         ece[0x20];
4876
4877         struct mlx5_ifc_qpc_bits qpc;
4878
4879         u8         reserved_at_800[0x80];
4880 };
4881
4882 struct mlx5_ifc_rst2init_qp_out_bits {
4883         u8         status[0x8];
4884         u8         reserved_at_8[0x18];
4885
4886         u8         syndrome[0x20];
4887
4888         u8         reserved_at_40[0x20];
4889         u8         ece[0x20];
4890 };
4891
4892 struct mlx5_ifc_rst2init_qp_in_bits {
4893         u8         opcode[0x10];
4894         u8         uid[0x10];
4895
4896         u8         reserved_at_20[0x10];
4897         u8         op_mod[0x10];
4898
4899         u8         reserved_at_40[0x8];
4900         u8         qpn[0x18];
4901
4902         u8         reserved_at_60[0x20];
4903
4904         u8         opt_param_mask[0x20];
4905
4906         u8         ece[0x20];
4907
4908         struct mlx5_ifc_qpc_bits qpc;
4909
4910         u8         reserved_at_800[0x80];
4911 };
4912
4913 struct mlx5_ifc_query_xrq_out_bits {
4914         u8         status[0x8];
4915         u8         reserved_at_8[0x18];
4916
4917         u8         syndrome[0x20];
4918
4919         u8         reserved_at_40[0x40];
4920
4921         struct mlx5_ifc_xrqc_bits xrq_context;
4922 };
4923
4924 struct mlx5_ifc_query_xrq_in_bits {
4925         u8         opcode[0x10];
4926         u8         reserved_at_10[0x10];
4927
4928         u8         reserved_at_20[0x10];
4929         u8         op_mod[0x10];
4930
4931         u8         reserved_at_40[0x8];
4932         u8         xrqn[0x18];
4933
4934         u8         reserved_at_60[0x20];
4935 };
4936
4937 struct mlx5_ifc_query_xrc_srq_out_bits {
4938         u8         status[0x8];
4939         u8         reserved_at_8[0x18];
4940
4941         u8         syndrome[0x20];
4942
4943         u8         reserved_at_40[0x40];
4944
4945         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4946
4947         u8         reserved_at_280[0x600];
4948
4949         u8         pas[][0x40];
4950 };
4951
4952 struct mlx5_ifc_query_xrc_srq_in_bits {
4953         u8         opcode[0x10];
4954         u8         reserved_at_10[0x10];
4955
4956         u8         reserved_at_20[0x10];
4957         u8         op_mod[0x10];
4958
4959         u8         reserved_at_40[0x8];
4960         u8         xrc_srqn[0x18];
4961
4962         u8         reserved_at_60[0x20];
4963 };
4964
4965 enum {
4966         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4967         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4968 };
4969
4970 struct mlx5_ifc_query_vport_state_out_bits {
4971         u8         status[0x8];
4972         u8         reserved_at_8[0x18];
4973
4974         u8         syndrome[0x20];
4975
4976         u8         reserved_at_40[0x20];
4977
4978         u8         reserved_at_60[0x18];
4979         u8         admin_state[0x4];
4980         u8         state[0x4];
4981 };
4982
4983 enum {
4984         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
4985         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
4986         MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
4987 };
4988
4989 struct mlx5_ifc_arm_monitor_counter_in_bits {
4990         u8         opcode[0x10];
4991         u8         uid[0x10];
4992
4993         u8         reserved_at_20[0x10];
4994         u8         op_mod[0x10];
4995
4996         u8         reserved_at_40[0x20];
4997
4998         u8         reserved_at_60[0x20];
4999 };
5000
5001 struct mlx5_ifc_arm_monitor_counter_out_bits {
5002         u8         status[0x8];
5003         u8         reserved_at_8[0x18];
5004
5005         u8         syndrome[0x20];
5006
5007         u8         reserved_at_40[0x40];
5008 };
5009
5010 enum {
5011         MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
5012         MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
5013 };
5014
5015 enum mlx5_monitor_counter_ppcnt {
5016         MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
5017         MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
5018         MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
5019         MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
5020         MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
5021         MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
5022 };
5023
5024 enum {
5025         MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
5026 };
5027
5028 struct mlx5_ifc_monitor_counter_output_bits {
5029         u8         reserved_at_0[0x4];
5030         u8         type[0x4];
5031         u8         reserved_at_8[0x8];
5032         u8         counter[0x10];
5033
5034         u8         counter_group_id[0x20];
5035 };
5036
5037 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
5038 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
5039 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
5040                                           MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
5041
5042 struct mlx5_ifc_set_monitor_counter_in_bits {
5043         u8         opcode[0x10];
5044         u8         uid[0x10];
5045
5046         u8         reserved_at_20[0x10];
5047         u8         op_mod[0x10];
5048
5049         u8         reserved_at_40[0x10];
5050         u8         num_of_counters[0x10];
5051
5052         u8         reserved_at_60[0x20];
5053
5054         struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
5055 };
5056
5057 struct mlx5_ifc_set_monitor_counter_out_bits {
5058         u8         status[0x8];
5059         u8         reserved_at_8[0x18];
5060
5061         u8         syndrome[0x20];
5062
5063         u8         reserved_at_40[0x40];
5064 };
5065
5066 struct mlx5_ifc_query_vport_state_in_bits {
5067         u8         opcode[0x10];
5068         u8         reserved_at_10[0x10];
5069
5070         u8         reserved_at_20[0x10];
5071         u8         op_mod[0x10];
5072
5073         u8         other_vport[0x1];
5074         u8         reserved_at_41[0xf];
5075         u8         vport_number[0x10];
5076
5077         u8         reserved_at_60[0x20];
5078 };
5079
5080 struct mlx5_ifc_query_vnic_env_out_bits {
5081         u8         status[0x8];
5082         u8         reserved_at_8[0x18];
5083
5084         u8         syndrome[0x20];
5085
5086         u8         reserved_at_40[0x40];
5087
5088         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
5089 };
5090
5091 enum {
5092         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
5093 };
5094
5095 struct mlx5_ifc_query_vnic_env_in_bits {
5096         u8         opcode[0x10];
5097         u8         reserved_at_10[0x10];
5098
5099         u8         reserved_at_20[0x10];
5100         u8         op_mod[0x10];
5101
5102         u8         other_vport[0x1];
5103         u8         reserved_at_41[0xf];
5104         u8         vport_number[0x10];
5105
5106         u8         reserved_at_60[0x20];
5107 };
5108
5109 struct mlx5_ifc_query_vport_counter_out_bits {
5110         u8         status[0x8];
5111         u8         reserved_at_8[0x18];
5112
5113         u8         syndrome[0x20];
5114
5115         u8         reserved_at_40[0x40];
5116
5117         struct mlx5_ifc_traffic_counter_bits received_errors;
5118
5119         struct mlx5_ifc_traffic_counter_bits transmit_errors;
5120
5121         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
5122
5123         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
5124
5125         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
5126
5127         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
5128
5129         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
5130
5131         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
5132
5133         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
5134
5135         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
5136
5137         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
5138
5139         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
5140
5141         u8         reserved_at_680[0xa00];
5142 };
5143
5144 enum {
5145         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
5146 };
5147
5148 struct mlx5_ifc_query_vport_counter_in_bits {
5149         u8         opcode[0x10];
5150         u8         reserved_at_10[0x10];
5151
5152         u8         reserved_at_20[0x10];
5153         u8         op_mod[0x10];
5154
5155         u8         other_vport[0x1];
5156         u8         reserved_at_41[0xb];
5157         u8         port_num[0x4];
5158         u8         vport_number[0x10];
5159
5160         u8         reserved_at_60[0x60];
5161
5162         u8         clear[0x1];
5163         u8         reserved_at_c1[0x1f];
5164
5165         u8         reserved_at_e0[0x20];
5166 };
5167
5168 struct mlx5_ifc_query_tis_out_bits {
5169         u8         status[0x8];
5170         u8         reserved_at_8[0x18];
5171
5172         u8         syndrome[0x20];
5173
5174         u8         reserved_at_40[0x40];
5175
5176         struct mlx5_ifc_tisc_bits tis_context;
5177 };
5178
5179 struct mlx5_ifc_query_tis_in_bits {
5180         u8         opcode[0x10];
5181         u8         reserved_at_10[0x10];
5182
5183         u8         reserved_at_20[0x10];
5184         u8         op_mod[0x10];
5185
5186         u8         reserved_at_40[0x8];
5187         u8         tisn[0x18];
5188
5189         u8         reserved_at_60[0x20];
5190 };
5191
5192 struct mlx5_ifc_query_tir_out_bits {
5193         u8         status[0x8];
5194         u8         reserved_at_8[0x18];
5195
5196         u8         syndrome[0x20];
5197
5198         u8         reserved_at_40[0xc0];
5199
5200         struct mlx5_ifc_tirc_bits tir_context;
5201 };
5202
5203 struct mlx5_ifc_query_tir_in_bits {
5204         u8         opcode[0x10];
5205         u8         reserved_at_10[0x10];
5206
5207         u8         reserved_at_20[0x10];
5208         u8         op_mod[0x10];
5209
5210         u8         reserved_at_40[0x8];
5211         u8         tirn[0x18];
5212
5213         u8         reserved_at_60[0x20];
5214 };
5215
5216 struct mlx5_ifc_query_srq_out_bits {
5217         u8         status[0x8];
5218         u8         reserved_at_8[0x18];
5219
5220         u8         syndrome[0x20];
5221
5222         u8         reserved_at_40[0x40];
5223
5224         struct mlx5_ifc_srqc_bits srq_context_entry;
5225
5226         u8         reserved_at_280[0x600];
5227
5228         u8         pas[][0x40];
5229 };
5230
5231 struct mlx5_ifc_query_srq_in_bits {
5232         u8         opcode[0x10];
5233         u8         reserved_at_10[0x10];
5234
5235         u8         reserved_at_20[0x10];
5236         u8         op_mod[0x10];
5237
5238         u8         reserved_at_40[0x8];
5239         u8         srqn[0x18];
5240
5241         u8         reserved_at_60[0x20];
5242 };
5243
5244 struct mlx5_ifc_query_sq_out_bits {
5245         u8         status[0x8];
5246         u8         reserved_at_8[0x18];
5247
5248         u8         syndrome[0x20];
5249
5250         u8         reserved_at_40[0xc0];
5251
5252         struct mlx5_ifc_sqc_bits sq_context;
5253 };
5254
5255 struct mlx5_ifc_query_sq_in_bits {
5256         u8         opcode[0x10];
5257         u8         reserved_at_10[0x10];
5258
5259         u8         reserved_at_20[0x10];
5260         u8         op_mod[0x10];
5261
5262         u8         reserved_at_40[0x8];
5263         u8         sqn[0x18];
5264
5265         u8         reserved_at_60[0x20];
5266 };
5267
5268 struct mlx5_ifc_query_special_contexts_out_bits {
5269         u8         status[0x8];
5270         u8         reserved_at_8[0x18];
5271
5272         u8         syndrome[0x20];
5273
5274         u8         dump_fill_mkey[0x20];
5275
5276         u8         resd_lkey[0x20];
5277
5278         u8         null_mkey[0x20];
5279
5280         u8         terminate_scatter_list_mkey[0x20];
5281
5282         u8         repeated_mkey[0x20];
5283
5284         u8         reserved_at_a0[0x20];
5285 };
5286
5287 struct mlx5_ifc_query_special_contexts_in_bits {
5288         u8         opcode[0x10];
5289         u8         reserved_at_10[0x10];
5290
5291         u8         reserved_at_20[0x10];
5292         u8         op_mod[0x10];
5293
5294         u8         reserved_at_40[0x40];
5295 };
5296
5297 struct mlx5_ifc_query_scheduling_element_out_bits {
5298         u8         opcode[0x10];
5299         u8         reserved_at_10[0x10];
5300
5301         u8         reserved_at_20[0x10];
5302         u8         op_mod[0x10];
5303
5304         u8         reserved_at_40[0xc0];
5305
5306         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5307
5308         u8         reserved_at_300[0x100];
5309 };
5310
5311 enum {
5312         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5313         SCHEDULING_HIERARCHY_NIC = 0x3,
5314 };
5315
5316 struct mlx5_ifc_query_scheduling_element_in_bits {
5317         u8         opcode[0x10];
5318         u8         reserved_at_10[0x10];
5319
5320         u8         reserved_at_20[0x10];
5321         u8         op_mod[0x10];
5322
5323         u8         scheduling_hierarchy[0x8];
5324         u8         reserved_at_48[0x18];
5325
5326         u8         scheduling_element_id[0x20];
5327
5328         u8         reserved_at_80[0x180];
5329 };
5330
5331 struct mlx5_ifc_query_rqt_out_bits {
5332         u8         status[0x8];
5333         u8         reserved_at_8[0x18];
5334
5335         u8         syndrome[0x20];
5336
5337         u8         reserved_at_40[0xc0];
5338
5339         struct mlx5_ifc_rqtc_bits rqt_context;
5340 };
5341
5342 struct mlx5_ifc_query_rqt_in_bits {
5343         u8         opcode[0x10];
5344         u8         reserved_at_10[0x10];
5345
5346         u8         reserved_at_20[0x10];
5347         u8         op_mod[0x10];
5348
5349         u8         reserved_at_40[0x8];
5350         u8         rqtn[0x18];
5351
5352         u8         reserved_at_60[0x20];
5353 };
5354
5355 struct mlx5_ifc_query_rq_out_bits {
5356         u8         status[0x8];
5357         u8         reserved_at_8[0x18];
5358
5359         u8         syndrome[0x20];
5360
5361         u8         reserved_at_40[0xc0];
5362
5363         struct mlx5_ifc_rqc_bits rq_context;
5364 };
5365
5366 struct mlx5_ifc_query_rq_in_bits {
5367         u8         opcode[0x10];
5368         u8         reserved_at_10[0x10];
5369
5370         u8         reserved_at_20[0x10];
5371         u8         op_mod[0x10];
5372
5373         u8         reserved_at_40[0x8];
5374         u8         rqn[0x18];
5375
5376         u8         reserved_at_60[0x20];
5377 };
5378
5379 struct mlx5_ifc_query_roce_address_out_bits {
5380         u8         status[0x8];
5381         u8         reserved_at_8[0x18];
5382
5383         u8         syndrome[0x20];
5384
5385         u8         reserved_at_40[0x40];
5386
5387         struct mlx5_ifc_roce_addr_layout_bits roce_address;
5388 };
5389
5390 struct mlx5_ifc_query_roce_address_in_bits {
5391         u8         opcode[0x10];
5392         u8         reserved_at_10[0x10];
5393
5394         u8         reserved_at_20[0x10];
5395         u8         op_mod[0x10];
5396
5397         u8         roce_address_index[0x10];
5398         u8         reserved_at_50[0xc];
5399         u8         vhca_port_num[0x4];
5400
5401         u8         reserved_at_60[0x20];
5402 };
5403
5404 struct mlx5_ifc_query_rmp_out_bits {
5405         u8         status[0x8];
5406         u8         reserved_at_8[0x18];
5407
5408         u8         syndrome[0x20];
5409
5410         u8         reserved_at_40[0xc0];
5411
5412         struct mlx5_ifc_rmpc_bits rmp_context;
5413 };
5414
5415 struct mlx5_ifc_query_rmp_in_bits {
5416         u8         opcode[0x10];
5417         u8         reserved_at_10[0x10];
5418
5419         u8         reserved_at_20[0x10];
5420         u8         op_mod[0x10];
5421
5422         u8         reserved_at_40[0x8];
5423         u8         rmpn[0x18];
5424
5425         u8         reserved_at_60[0x20];
5426 };
5427
5428 struct mlx5_ifc_cqe_error_syndrome_bits {
5429         u8         hw_error_syndrome[0x8];
5430         u8         hw_syndrome_type[0x4];
5431         u8         reserved_at_c[0x4];
5432         u8         vendor_error_syndrome[0x8];
5433         u8         syndrome[0x8];
5434 };
5435
5436 struct mlx5_ifc_qp_context_extension_bits {
5437         u8         reserved_at_0[0x60];
5438
5439         struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome;
5440
5441         u8         reserved_at_80[0x580];
5442 };
5443
5444 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits {
5445         struct mlx5_ifc_qp_context_extension_bits qpc_data_extension;
5446
5447         u8         pas[0][0x40];
5448 };
5449
5450 struct mlx5_ifc_qp_pas_list_in_bits {
5451         struct mlx5_ifc_cmd_pas_bits pas[0];
5452 };
5453
5454 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits {
5455         struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list;
5456         struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list;
5457 };
5458
5459 struct mlx5_ifc_query_qp_out_bits {
5460         u8         status[0x8];
5461         u8         reserved_at_8[0x18];
5462
5463         u8         syndrome[0x20];
5464
5465         u8         reserved_at_40[0x40];
5466
5467         u8         opt_param_mask[0x20];
5468
5469         u8         ece[0x20];
5470
5471         struct mlx5_ifc_qpc_bits qpc;
5472
5473         u8         reserved_at_800[0x80];
5474
5475         union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas;
5476 };
5477
5478 struct mlx5_ifc_query_qp_in_bits {
5479         u8         opcode[0x10];
5480         u8         reserved_at_10[0x10];
5481
5482         u8         reserved_at_20[0x10];
5483         u8         op_mod[0x10];
5484
5485         u8         qpc_ext[0x1];
5486         u8         reserved_at_41[0x7];
5487         u8         qpn[0x18];
5488
5489         u8         reserved_at_60[0x20];
5490 };
5491
5492 struct mlx5_ifc_query_q_counter_out_bits {
5493         u8         status[0x8];
5494         u8         reserved_at_8[0x18];
5495
5496         u8         syndrome[0x20];
5497
5498         u8         reserved_at_40[0x40];
5499
5500         u8         rx_write_requests[0x20];
5501
5502         u8         reserved_at_a0[0x20];
5503
5504         u8         rx_read_requests[0x20];
5505
5506         u8         reserved_at_e0[0x20];
5507
5508         u8         rx_atomic_requests[0x20];
5509
5510         u8         reserved_at_120[0x20];
5511
5512         u8         rx_dct_connect[0x20];
5513
5514         u8         reserved_at_160[0x20];
5515
5516         u8         out_of_buffer[0x20];
5517
5518         u8         reserved_at_1a0[0x20];
5519
5520         u8         out_of_sequence[0x20];
5521
5522         u8         reserved_at_1e0[0x20];
5523
5524         u8         duplicate_request[0x20];
5525
5526         u8         reserved_at_220[0x20];
5527
5528         u8         rnr_nak_retry_err[0x20];
5529
5530         u8         reserved_at_260[0x20];
5531
5532         u8         packet_seq_err[0x20];
5533
5534         u8         reserved_at_2a0[0x20];
5535
5536         u8         implied_nak_seq_err[0x20];
5537
5538         u8         reserved_at_2e0[0x20];
5539
5540         u8         local_ack_timeout_err[0x20];
5541
5542         u8         reserved_at_320[0xa0];
5543
5544         u8         resp_local_length_error[0x20];
5545
5546         u8         req_local_length_error[0x20];
5547
5548         u8         resp_local_qp_error[0x20];
5549
5550         u8         local_operation_error[0x20];
5551
5552         u8         resp_local_protection[0x20];
5553
5554         u8         req_local_protection[0x20];
5555
5556         u8         resp_cqe_error[0x20];
5557
5558         u8         req_cqe_error[0x20];
5559
5560         u8         req_mw_binding[0x20];
5561
5562         u8         req_bad_response[0x20];
5563
5564         u8         req_remote_invalid_request[0x20];
5565
5566         u8         resp_remote_invalid_request[0x20];
5567
5568         u8         req_remote_access_errors[0x20];
5569
5570         u8         resp_remote_access_errors[0x20];
5571
5572         u8         req_remote_operation_errors[0x20];
5573
5574         u8         req_transport_retries_exceeded[0x20];
5575
5576         u8         cq_overflow[0x20];
5577
5578         u8         resp_cqe_flush_error[0x20];
5579
5580         u8         req_cqe_flush_error[0x20];
5581
5582         u8         reserved_at_620[0x20];
5583
5584         u8         roce_adp_retrans[0x20];
5585
5586         u8         roce_adp_retrans_to[0x20];
5587
5588         u8         roce_slow_restart[0x20];
5589
5590         u8         roce_slow_restart_cnps[0x20];
5591
5592         u8         roce_slow_restart_trans[0x20];
5593
5594         u8         reserved_at_6e0[0x120];
5595 };
5596
5597 struct mlx5_ifc_query_q_counter_in_bits {
5598         u8         opcode[0x10];
5599         u8         reserved_at_10[0x10];
5600
5601         u8         reserved_at_20[0x10];
5602         u8         op_mod[0x10];
5603
5604         u8         reserved_at_40[0x80];
5605
5606         u8         clear[0x1];
5607         u8         reserved_at_c1[0x1f];
5608
5609         u8         reserved_at_e0[0x18];
5610         u8         counter_set_id[0x8];
5611 };
5612
5613 struct mlx5_ifc_query_pages_out_bits {
5614         u8         status[0x8];
5615         u8         reserved_at_8[0x18];
5616
5617         u8         syndrome[0x20];
5618
5619         u8         embedded_cpu_function[0x1];
5620         u8         reserved_at_41[0xf];
5621         u8         function_id[0x10];
5622
5623         u8         num_pages[0x20];
5624 };
5625
5626 enum {
5627         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
5628         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
5629         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
5630 };
5631
5632 struct mlx5_ifc_query_pages_in_bits {
5633         u8         opcode[0x10];
5634         u8         reserved_at_10[0x10];
5635
5636         u8         reserved_at_20[0x10];
5637         u8         op_mod[0x10];
5638
5639         u8         embedded_cpu_function[0x1];
5640         u8         reserved_at_41[0xf];
5641         u8         function_id[0x10];
5642
5643         u8         reserved_at_60[0x20];
5644 };
5645
5646 struct mlx5_ifc_query_nic_vport_context_out_bits {
5647         u8         status[0x8];
5648         u8         reserved_at_8[0x18];
5649
5650         u8         syndrome[0x20];
5651
5652         u8         reserved_at_40[0x40];
5653
5654         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5655 };
5656
5657 struct mlx5_ifc_query_nic_vport_context_in_bits {
5658         u8         opcode[0x10];
5659         u8         reserved_at_10[0x10];
5660
5661         u8         reserved_at_20[0x10];
5662         u8         op_mod[0x10];
5663
5664         u8         other_vport[0x1];
5665         u8         reserved_at_41[0xf];
5666         u8         vport_number[0x10];
5667
5668         u8         reserved_at_60[0x5];
5669         u8         allowed_list_type[0x3];
5670         u8         reserved_at_68[0x18];
5671 };
5672
5673 struct mlx5_ifc_query_mkey_out_bits {
5674         u8         status[0x8];
5675         u8         reserved_at_8[0x18];
5676
5677         u8         syndrome[0x20];
5678
5679         u8         reserved_at_40[0x40];
5680
5681         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5682
5683         u8         reserved_at_280[0x600];
5684
5685         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
5686
5687         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
5688 };
5689
5690 struct mlx5_ifc_query_mkey_in_bits {
5691         u8         opcode[0x10];
5692         u8         reserved_at_10[0x10];
5693
5694         u8         reserved_at_20[0x10];
5695         u8         op_mod[0x10];
5696
5697         u8         reserved_at_40[0x8];
5698         u8         mkey_index[0x18];
5699
5700         u8         pg_access[0x1];
5701         u8         reserved_at_61[0x1f];
5702 };
5703
5704 struct mlx5_ifc_query_mad_demux_out_bits {
5705         u8         status[0x8];
5706         u8         reserved_at_8[0x18];
5707
5708         u8         syndrome[0x20];
5709
5710         u8         reserved_at_40[0x40];
5711
5712         u8         mad_dumux_parameters_block[0x20];
5713 };
5714
5715 struct mlx5_ifc_query_mad_demux_in_bits {
5716         u8         opcode[0x10];
5717         u8         reserved_at_10[0x10];
5718
5719         u8         reserved_at_20[0x10];
5720         u8         op_mod[0x10];
5721
5722         u8         reserved_at_40[0x40];
5723 };
5724
5725 struct mlx5_ifc_query_l2_table_entry_out_bits {
5726         u8         status[0x8];
5727         u8         reserved_at_8[0x18];
5728
5729         u8         syndrome[0x20];
5730
5731         u8         reserved_at_40[0xa0];
5732
5733         u8         reserved_at_e0[0x13];
5734         u8         vlan_valid[0x1];
5735         u8         vlan[0xc];
5736
5737         struct mlx5_ifc_mac_address_layout_bits mac_address;
5738
5739         u8         reserved_at_140[0xc0];
5740 };
5741
5742 struct mlx5_ifc_query_l2_table_entry_in_bits {
5743         u8         opcode[0x10];
5744         u8         reserved_at_10[0x10];
5745
5746         u8         reserved_at_20[0x10];
5747         u8         op_mod[0x10];
5748
5749         u8         reserved_at_40[0x60];
5750
5751         u8         reserved_at_a0[0x8];
5752         u8         table_index[0x18];
5753
5754         u8         reserved_at_c0[0x140];
5755 };
5756
5757 struct mlx5_ifc_query_issi_out_bits {
5758         u8         status[0x8];
5759         u8         reserved_at_8[0x18];
5760
5761         u8         syndrome[0x20];
5762
5763         u8         reserved_at_40[0x10];
5764         u8         current_issi[0x10];
5765
5766         u8         reserved_at_60[0xa0];
5767
5768         u8         reserved_at_100[76][0x8];
5769         u8         supported_issi_dw0[0x20];
5770 };
5771
5772 struct mlx5_ifc_query_issi_in_bits {
5773         u8         opcode[0x10];
5774         u8         reserved_at_10[0x10];
5775
5776         u8         reserved_at_20[0x10];
5777         u8         op_mod[0x10];
5778
5779         u8         reserved_at_40[0x40];
5780 };
5781
5782 struct mlx5_ifc_set_driver_version_out_bits {
5783         u8         status[0x8];
5784         u8         reserved_0[0x18];
5785
5786         u8         syndrome[0x20];
5787         u8         reserved_1[0x40];
5788 };
5789
5790 struct mlx5_ifc_set_driver_version_in_bits {
5791         u8         opcode[0x10];
5792         u8         reserved_0[0x10];
5793
5794         u8         reserved_1[0x10];
5795         u8         op_mod[0x10];
5796
5797         u8         reserved_2[0x40];
5798         u8         driver_version[64][0x8];
5799 };
5800
5801 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5802         u8         status[0x8];
5803         u8         reserved_at_8[0x18];
5804
5805         u8         syndrome[0x20];
5806
5807         u8         reserved_at_40[0x40];
5808
5809         struct mlx5_ifc_pkey_bits pkey[];
5810 };
5811
5812 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5813         u8         opcode[0x10];
5814         u8         reserved_at_10[0x10];
5815
5816         u8         reserved_at_20[0x10];
5817         u8         op_mod[0x10];
5818
5819         u8         other_vport[0x1];
5820         u8         reserved_at_41[0xb];
5821         u8         port_num[0x4];
5822         u8         vport_number[0x10];
5823
5824         u8         reserved_at_60[0x10];
5825         u8         pkey_index[0x10];
5826 };
5827
5828 enum {
5829         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
5830         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
5831         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5832 };
5833
5834 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5835         u8         status[0x8];
5836         u8         reserved_at_8[0x18];
5837
5838         u8         syndrome[0x20];
5839
5840         u8         reserved_at_40[0x20];
5841
5842         u8         gids_num[0x10];
5843         u8         reserved_at_70[0x10];
5844
5845         struct mlx5_ifc_array128_auto_bits gid[];
5846 };
5847
5848 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5849         u8         opcode[0x10];
5850         u8         reserved_at_10[0x10];
5851
5852         u8         reserved_at_20[0x10];
5853         u8         op_mod[0x10];
5854
5855         u8         other_vport[0x1];
5856         u8         reserved_at_41[0xb];
5857         u8         port_num[0x4];
5858         u8         vport_number[0x10];
5859
5860         u8         reserved_at_60[0x10];
5861         u8         gid_index[0x10];
5862 };
5863
5864 struct mlx5_ifc_query_hca_vport_context_out_bits {
5865         u8         status[0x8];
5866         u8         reserved_at_8[0x18];
5867
5868         u8         syndrome[0x20];
5869
5870         u8         reserved_at_40[0x40];
5871
5872         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5873 };
5874
5875 struct mlx5_ifc_query_hca_vport_context_in_bits {
5876         u8         opcode[0x10];
5877         u8         reserved_at_10[0x10];
5878
5879         u8         reserved_at_20[0x10];
5880         u8         op_mod[0x10];
5881
5882         u8         other_vport[0x1];
5883         u8         reserved_at_41[0xb];
5884         u8         port_num[0x4];
5885         u8         vport_number[0x10];
5886
5887         u8         reserved_at_60[0x20];
5888 };
5889
5890 struct mlx5_ifc_query_hca_cap_out_bits {
5891         u8         status[0x8];
5892         u8         reserved_at_8[0x18];
5893
5894         u8         syndrome[0x20];
5895
5896         u8         reserved_at_40[0x40];
5897
5898         union mlx5_ifc_hca_cap_union_bits capability;
5899 };
5900
5901 struct mlx5_ifc_query_hca_cap_in_bits {
5902         u8         opcode[0x10];
5903         u8         reserved_at_10[0x10];
5904
5905         u8         reserved_at_20[0x10];
5906         u8         op_mod[0x10];
5907
5908         u8         other_function[0x1];
5909         u8         reserved_at_41[0xf];
5910         u8         function_id[0x10];
5911
5912         u8         reserved_at_60[0x20];
5913 };
5914
5915 struct mlx5_ifc_other_hca_cap_bits {
5916         u8         roce[0x1];
5917         u8         reserved_at_1[0x27f];
5918 };
5919
5920 struct mlx5_ifc_query_other_hca_cap_out_bits {
5921         u8         status[0x8];
5922         u8         reserved_at_8[0x18];
5923
5924         u8         syndrome[0x20];
5925
5926         u8         reserved_at_40[0x40];
5927
5928         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5929 };
5930
5931 struct mlx5_ifc_query_other_hca_cap_in_bits {
5932         u8         opcode[0x10];
5933         u8         reserved_at_10[0x10];
5934
5935         u8         reserved_at_20[0x10];
5936         u8         op_mod[0x10];
5937
5938         u8         reserved_at_40[0x10];
5939         u8         function_id[0x10];
5940
5941         u8         reserved_at_60[0x20];
5942 };
5943
5944 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5945         u8         status[0x8];
5946         u8         reserved_at_8[0x18];
5947
5948         u8         syndrome[0x20];
5949
5950         u8         reserved_at_40[0x40];
5951 };
5952
5953 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5954         u8         opcode[0x10];
5955         u8         reserved_at_10[0x10];
5956
5957         u8         reserved_at_20[0x10];
5958         u8         op_mod[0x10];
5959
5960         u8         reserved_at_40[0x10];
5961         u8         function_id[0x10];
5962         u8         field_select[0x20];
5963
5964         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5965 };
5966
5967 struct mlx5_ifc_flow_table_context_bits {
5968         u8         reformat_en[0x1];
5969         u8         decap_en[0x1];
5970         u8         sw_owner[0x1];
5971         u8         termination_table[0x1];
5972         u8         table_miss_action[0x4];
5973         u8         level[0x8];
5974         u8         reserved_at_10[0x8];
5975         u8         log_size[0x8];
5976
5977         u8         reserved_at_20[0x8];
5978         u8         table_miss_id[0x18];
5979
5980         u8         reserved_at_40[0x8];
5981         u8         lag_master_next_table_id[0x18];
5982
5983         u8         reserved_at_60[0x60];
5984
5985         u8         sw_owner_icm_root_1[0x40];
5986
5987         u8         sw_owner_icm_root_0[0x40];
5988
5989 };
5990
5991 struct mlx5_ifc_query_flow_table_out_bits {
5992         u8         status[0x8];
5993         u8         reserved_at_8[0x18];
5994
5995         u8         syndrome[0x20];
5996
5997         u8         reserved_at_40[0x80];
5998
5999         struct mlx5_ifc_flow_table_context_bits flow_table_context;
6000 };
6001
6002 struct mlx5_ifc_query_flow_table_in_bits {
6003         u8         opcode[0x10];
6004         u8         reserved_at_10[0x10];
6005
6006         u8         reserved_at_20[0x10];
6007         u8         op_mod[0x10];
6008
6009         u8         reserved_at_40[0x40];
6010
6011         u8         table_type[0x8];
6012         u8         reserved_at_88[0x18];
6013
6014         u8         reserved_at_a0[0x8];
6015         u8         table_id[0x18];
6016
6017         u8         reserved_at_c0[0x140];
6018 };
6019
6020 struct mlx5_ifc_query_fte_out_bits {
6021         u8         status[0x8];
6022         u8         reserved_at_8[0x18];
6023
6024         u8         syndrome[0x20];
6025
6026         u8         reserved_at_40[0x1c0];
6027
6028         struct mlx5_ifc_flow_context_bits flow_context;
6029 };
6030
6031 struct mlx5_ifc_query_fte_in_bits {
6032         u8         opcode[0x10];
6033         u8         reserved_at_10[0x10];
6034
6035         u8         reserved_at_20[0x10];
6036         u8         op_mod[0x10];
6037
6038         u8         reserved_at_40[0x40];
6039
6040         u8         table_type[0x8];
6041         u8         reserved_at_88[0x18];
6042
6043         u8         reserved_at_a0[0x8];
6044         u8         table_id[0x18];
6045
6046         u8         reserved_at_c0[0x40];
6047
6048         u8         flow_index[0x20];
6049
6050         u8         reserved_at_120[0xe0];
6051 };
6052
6053 struct mlx5_ifc_match_definer_format_0_bits {
6054         u8         reserved_at_0[0x100];
6055
6056         u8         metadata_reg_c_0[0x20];
6057
6058         u8         metadata_reg_c_1[0x20];
6059
6060         u8         outer_dmac_47_16[0x20];
6061
6062         u8         outer_dmac_15_0[0x10];
6063         u8         outer_ethertype[0x10];
6064
6065         u8         reserved_at_180[0x1];
6066         u8         sx_sniffer[0x1];
6067         u8         functional_lb[0x1];
6068         u8         outer_ip_frag[0x1];
6069         u8         outer_qp_type[0x2];
6070         u8         outer_encap_type[0x2];
6071         u8         port_number[0x2];
6072         u8         outer_l3_type[0x2];
6073         u8         outer_l4_type[0x2];
6074         u8         outer_first_vlan_type[0x2];
6075         u8         outer_first_vlan_prio[0x3];
6076         u8         outer_first_vlan_cfi[0x1];
6077         u8         outer_first_vlan_vid[0xc];
6078
6079         u8         outer_l4_type_ext[0x4];
6080         u8         reserved_at_1a4[0x2];
6081         u8         outer_ipsec_layer[0x2];
6082         u8         outer_l2_type[0x2];
6083         u8         force_lb[0x1];
6084         u8         outer_l2_ok[0x1];
6085         u8         outer_l3_ok[0x1];
6086         u8         outer_l4_ok[0x1];
6087         u8         outer_second_vlan_type[0x2];
6088         u8         outer_second_vlan_prio[0x3];
6089         u8         outer_second_vlan_cfi[0x1];
6090         u8         outer_second_vlan_vid[0xc];
6091
6092         u8         outer_smac_47_16[0x20];
6093
6094         u8         outer_smac_15_0[0x10];
6095         u8         inner_ipv4_checksum_ok[0x1];
6096         u8         inner_l4_checksum_ok[0x1];
6097         u8         outer_ipv4_checksum_ok[0x1];
6098         u8         outer_l4_checksum_ok[0x1];
6099         u8         inner_l3_ok[0x1];
6100         u8         inner_l4_ok[0x1];
6101         u8         outer_l3_ok_duplicate[0x1];
6102         u8         outer_l4_ok_duplicate[0x1];
6103         u8         outer_tcp_cwr[0x1];
6104         u8         outer_tcp_ece[0x1];
6105         u8         outer_tcp_urg[0x1];
6106         u8         outer_tcp_ack[0x1];
6107         u8         outer_tcp_psh[0x1];
6108         u8         outer_tcp_rst[0x1];
6109         u8         outer_tcp_syn[0x1];
6110         u8         outer_tcp_fin[0x1];
6111 };
6112
6113 struct mlx5_ifc_match_definer_format_22_bits {
6114         u8         reserved_at_0[0x100];
6115
6116         u8         outer_ip_src_addr[0x20];
6117
6118         u8         outer_ip_dest_addr[0x20];
6119
6120         u8         outer_l4_sport[0x10];
6121         u8         outer_l4_dport[0x10];
6122
6123         u8         reserved_at_160[0x1];
6124         u8         sx_sniffer[0x1];
6125         u8         functional_lb[0x1];
6126         u8         outer_ip_frag[0x1];
6127         u8         outer_qp_type[0x2];
6128         u8         outer_encap_type[0x2];
6129         u8         port_number[0x2];
6130         u8         outer_l3_type[0x2];
6131         u8         outer_l4_type[0x2];
6132         u8         outer_first_vlan_type[0x2];
6133         u8         outer_first_vlan_prio[0x3];
6134         u8         outer_first_vlan_cfi[0x1];
6135         u8         outer_first_vlan_vid[0xc];
6136
6137         u8         metadata_reg_c_0[0x20];
6138
6139         u8         outer_dmac_47_16[0x20];
6140
6141         u8         outer_smac_47_16[0x20];
6142
6143         u8         outer_smac_15_0[0x10];
6144         u8         outer_dmac_15_0[0x10];
6145 };
6146
6147 struct mlx5_ifc_match_definer_format_23_bits {
6148         u8         reserved_at_0[0x100];
6149
6150         u8         inner_ip_src_addr[0x20];
6151
6152         u8         inner_ip_dest_addr[0x20];
6153
6154         u8         inner_l4_sport[0x10];
6155         u8         inner_l4_dport[0x10];
6156
6157         u8         reserved_at_160[0x1];
6158         u8         sx_sniffer[0x1];
6159         u8         functional_lb[0x1];
6160         u8         inner_ip_frag[0x1];
6161         u8         inner_qp_type[0x2];
6162         u8         inner_encap_type[0x2];
6163         u8         port_number[0x2];
6164         u8         inner_l3_type[0x2];
6165         u8         inner_l4_type[0x2];
6166         u8         inner_first_vlan_type[0x2];
6167         u8         inner_first_vlan_prio[0x3];
6168         u8         inner_first_vlan_cfi[0x1];
6169         u8         inner_first_vlan_vid[0xc];
6170
6171         u8         tunnel_header_0[0x20];
6172
6173         u8         inner_dmac_47_16[0x20];
6174
6175         u8         inner_smac_47_16[0x20];
6176
6177         u8         inner_smac_15_0[0x10];
6178         u8         inner_dmac_15_0[0x10];
6179 };
6180
6181 struct mlx5_ifc_match_definer_format_29_bits {
6182         u8         reserved_at_0[0xc0];
6183
6184         u8         outer_ip_dest_addr[0x80];
6185
6186         u8         outer_ip_src_addr[0x80];
6187
6188         u8         outer_l4_sport[0x10];
6189         u8         outer_l4_dport[0x10];
6190
6191         u8         reserved_at_1e0[0x20];
6192 };
6193
6194 struct mlx5_ifc_match_definer_format_30_bits {
6195         u8         reserved_at_0[0xa0];
6196
6197         u8         outer_ip_dest_addr[0x80];
6198
6199         u8         outer_ip_src_addr[0x80];
6200
6201         u8         outer_dmac_47_16[0x20];
6202
6203         u8         outer_smac_47_16[0x20];
6204
6205         u8         outer_smac_15_0[0x10];
6206         u8         outer_dmac_15_0[0x10];
6207 };
6208
6209 struct mlx5_ifc_match_definer_format_31_bits {
6210         u8         reserved_at_0[0xc0];
6211
6212         u8         inner_ip_dest_addr[0x80];
6213
6214         u8         inner_ip_src_addr[0x80];
6215
6216         u8         inner_l4_sport[0x10];
6217         u8         inner_l4_dport[0x10];
6218
6219         u8         reserved_at_1e0[0x20];
6220 };
6221
6222 struct mlx5_ifc_match_definer_format_32_bits {
6223         u8         reserved_at_0[0xa0];
6224
6225         u8         inner_ip_dest_addr[0x80];
6226
6227         u8         inner_ip_src_addr[0x80];
6228
6229         u8         inner_dmac_47_16[0x20];
6230
6231         u8         inner_smac_47_16[0x20];
6232
6233         u8         inner_smac_15_0[0x10];
6234         u8         inner_dmac_15_0[0x10];
6235 };
6236
6237 enum {
6238         MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61,
6239 };
6240
6241 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0
6242 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48
6243 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9
6244 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8
6245
6246 struct mlx5_ifc_match_definer_match_mask_bits {
6247         u8         reserved_at_1c0[5][0x20];
6248         u8         match_dw_8[0x20];
6249         u8         match_dw_7[0x20];
6250         u8         match_dw_6[0x20];
6251         u8         match_dw_5[0x20];
6252         u8         match_dw_4[0x20];
6253         u8         match_dw_3[0x20];
6254         u8         match_dw_2[0x20];
6255         u8         match_dw_1[0x20];
6256         u8         match_dw_0[0x20];
6257
6258         u8         match_byte_7[0x8];
6259         u8         match_byte_6[0x8];
6260         u8         match_byte_5[0x8];
6261         u8         match_byte_4[0x8];
6262
6263         u8         match_byte_3[0x8];
6264         u8         match_byte_2[0x8];
6265         u8         match_byte_1[0x8];
6266         u8         match_byte_0[0x8];
6267 };
6268
6269 struct mlx5_ifc_match_definer_bits {
6270         u8         modify_field_select[0x40];
6271
6272         u8         reserved_at_40[0x40];
6273
6274         u8         reserved_at_80[0x10];
6275         u8         format_id[0x10];
6276
6277         u8         reserved_at_a0[0x60];
6278
6279         u8         format_select_dw3[0x8];
6280         u8         format_select_dw2[0x8];
6281         u8         format_select_dw1[0x8];
6282         u8         format_select_dw0[0x8];
6283
6284         u8         format_select_dw7[0x8];
6285         u8         format_select_dw6[0x8];
6286         u8         format_select_dw5[0x8];
6287         u8         format_select_dw4[0x8];
6288
6289         u8         reserved_at_100[0x18];
6290         u8         format_select_dw8[0x8];
6291
6292         u8         reserved_at_120[0x20];
6293
6294         u8         format_select_byte3[0x8];
6295         u8         format_select_byte2[0x8];
6296         u8         format_select_byte1[0x8];
6297         u8         format_select_byte0[0x8];
6298
6299         u8         format_select_byte7[0x8];
6300         u8         format_select_byte6[0x8];
6301         u8         format_select_byte5[0x8];
6302         u8         format_select_byte4[0x8];
6303
6304         u8         reserved_at_180[0x40];
6305
6306         union {
6307                 struct {
6308                         u8         match_mask[16][0x20];
6309                 };
6310                 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format;
6311         };
6312 };
6313
6314 struct mlx5_ifc_general_obj_create_param_bits {
6315         u8         alias_object[0x1];
6316         u8         reserved_at_1[0x2];
6317         u8         log_obj_range[0x5];
6318         u8         reserved_at_8[0x18];
6319 };
6320
6321 struct mlx5_ifc_general_obj_query_param_bits {
6322         u8         alias_object[0x1];
6323         u8         obj_offset[0x1f];
6324 };
6325
6326 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
6327         u8         opcode[0x10];
6328         u8         uid[0x10];
6329
6330         u8         vhca_tunnel_id[0x10];
6331         u8         obj_type[0x10];
6332
6333         u8         obj_id[0x20];
6334
6335         union {
6336                 struct mlx5_ifc_general_obj_create_param_bits create;
6337                 struct mlx5_ifc_general_obj_query_param_bits query;
6338         } op_param;
6339 };
6340
6341 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
6342         u8         status[0x8];
6343         u8         reserved_at_8[0x18];
6344
6345         u8         syndrome[0x20];
6346
6347         u8         obj_id[0x20];
6348
6349         u8         reserved_at_60[0x20];
6350 };
6351
6352 struct mlx5_ifc_create_match_definer_in_bits {
6353         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
6354
6355         struct mlx5_ifc_match_definer_bits obj_context;
6356 };
6357
6358 struct mlx5_ifc_create_match_definer_out_bits {
6359         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
6360 };
6361
6362 enum {
6363         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6364         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6365         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6366         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6367         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6368         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6369         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6370 };
6371
6372 struct mlx5_ifc_query_flow_group_out_bits {
6373         u8         status[0x8];
6374         u8         reserved_at_8[0x18];
6375
6376         u8         syndrome[0x20];
6377
6378         u8         reserved_at_40[0xa0];
6379
6380         u8         start_flow_index[0x20];
6381
6382         u8         reserved_at_100[0x20];
6383
6384         u8         end_flow_index[0x20];
6385
6386         u8         reserved_at_140[0xa0];
6387
6388         u8         reserved_at_1e0[0x18];
6389         u8         match_criteria_enable[0x8];
6390
6391         struct mlx5_ifc_fte_match_param_bits match_criteria;
6392
6393         u8         reserved_at_1200[0xe00];
6394 };
6395
6396 struct mlx5_ifc_query_flow_group_in_bits {
6397         u8         opcode[0x10];
6398         u8         reserved_at_10[0x10];
6399
6400         u8         reserved_at_20[0x10];
6401         u8         op_mod[0x10];
6402
6403         u8         reserved_at_40[0x40];
6404
6405         u8         table_type[0x8];
6406         u8         reserved_at_88[0x18];
6407
6408         u8         reserved_at_a0[0x8];
6409         u8         table_id[0x18];
6410
6411         u8         group_id[0x20];
6412
6413         u8         reserved_at_e0[0x120];
6414 };
6415
6416 struct mlx5_ifc_query_flow_counter_out_bits {
6417         u8         status[0x8];
6418         u8         reserved_at_8[0x18];
6419
6420         u8         syndrome[0x20];
6421
6422         u8         reserved_at_40[0x40];
6423
6424         struct mlx5_ifc_traffic_counter_bits flow_statistics[];
6425 };
6426
6427 struct mlx5_ifc_query_flow_counter_in_bits {
6428         u8         opcode[0x10];
6429         u8         reserved_at_10[0x10];
6430
6431         u8         reserved_at_20[0x10];
6432         u8         op_mod[0x10];
6433
6434         u8         reserved_at_40[0x80];
6435
6436         u8         clear[0x1];
6437         u8         reserved_at_c1[0xf];
6438         u8         num_of_counters[0x10];
6439
6440         u8         flow_counter_id[0x20];
6441 };
6442
6443 struct mlx5_ifc_query_esw_vport_context_out_bits {
6444         u8         status[0x8];
6445         u8         reserved_at_8[0x18];
6446
6447         u8         syndrome[0x20];
6448
6449         u8         reserved_at_40[0x40];
6450
6451         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6452 };
6453
6454 struct mlx5_ifc_query_esw_vport_context_in_bits {
6455         u8         opcode[0x10];
6456         u8         reserved_at_10[0x10];
6457
6458         u8         reserved_at_20[0x10];
6459         u8         op_mod[0x10];
6460
6461         u8         other_vport[0x1];
6462         u8         reserved_at_41[0xf];
6463         u8         vport_number[0x10];
6464
6465         u8         reserved_at_60[0x20];
6466 };
6467
6468 struct mlx5_ifc_modify_esw_vport_context_out_bits {
6469         u8         status[0x8];
6470         u8         reserved_at_8[0x18];
6471
6472         u8         syndrome[0x20];
6473
6474         u8         reserved_at_40[0x40];
6475 };
6476
6477 struct mlx5_ifc_esw_vport_context_fields_select_bits {
6478         u8         reserved_at_0[0x1b];
6479         u8         fdb_to_vport_reg_c_id[0x1];
6480         u8         vport_cvlan_insert[0x1];
6481         u8         vport_svlan_insert[0x1];
6482         u8         vport_cvlan_strip[0x1];
6483         u8         vport_svlan_strip[0x1];
6484 };
6485
6486 struct mlx5_ifc_modify_esw_vport_context_in_bits {
6487         u8         opcode[0x10];
6488         u8         reserved_at_10[0x10];
6489
6490         u8         reserved_at_20[0x10];
6491         u8         op_mod[0x10];
6492
6493         u8         other_vport[0x1];
6494         u8         reserved_at_41[0xf];
6495         u8         vport_number[0x10];
6496
6497         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6498
6499         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6500 };
6501
6502 struct mlx5_ifc_query_eq_out_bits {
6503         u8         status[0x8];
6504         u8         reserved_at_8[0x18];
6505
6506         u8         syndrome[0x20];
6507
6508         u8         reserved_at_40[0x40];
6509
6510         struct mlx5_ifc_eqc_bits eq_context_entry;
6511
6512         u8         reserved_at_280[0x40];
6513
6514         u8         event_bitmask[0x40];
6515
6516         u8         reserved_at_300[0x580];
6517
6518         u8         pas[][0x40];
6519 };
6520
6521 struct mlx5_ifc_query_eq_in_bits {
6522         u8         opcode[0x10];
6523         u8         reserved_at_10[0x10];
6524
6525         u8         reserved_at_20[0x10];
6526         u8         op_mod[0x10];
6527
6528         u8         reserved_at_40[0x18];
6529         u8         eq_number[0x8];
6530
6531         u8         reserved_at_60[0x20];
6532 };
6533
6534 struct mlx5_ifc_packet_reformat_context_in_bits {
6535         u8         reformat_type[0x8];
6536         u8         reserved_at_8[0x4];
6537         u8         reformat_param_0[0x4];
6538         u8         reserved_at_10[0x6];
6539         u8         reformat_data_size[0xa];
6540
6541         u8         reformat_param_1[0x8];
6542         u8         reserved_at_28[0x8];
6543         u8         reformat_data[2][0x8];
6544
6545         u8         more_reformat_data[][0x8];
6546 };
6547
6548 struct mlx5_ifc_query_packet_reformat_context_out_bits {
6549         u8         status[0x8];
6550         u8         reserved_at_8[0x18];
6551
6552         u8         syndrome[0x20];
6553
6554         u8         reserved_at_40[0xa0];
6555
6556         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
6557 };
6558
6559 struct mlx5_ifc_query_packet_reformat_context_in_bits {
6560         u8         opcode[0x10];
6561         u8         reserved_at_10[0x10];
6562
6563         u8         reserved_at_20[0x10];
6564         u8         op_mod[0x10];
6565
6566         u8         packet_reformat_id[0x20];
6567
6568         u8         reserved_at_60[0xa0];
6569 };
6570
6571 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
6572         u8         status[0x8];
6573         u8         reserved_at_8[0x18];
6574
6575         u8         syndrome[0x20];
6576
6577         u8         packet_reformat_id[0x20];
6578
6579         u8         reserved_at_60[0x20];
6580 };
6581
6582 enum {
6583         MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
6584         MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
6585         MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
6586 };
6587
6588 enum mlx5_reformat_ctx_type {
6589         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
6590         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
6591         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
6592         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
6593         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
6594         MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
6595         MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
6596         MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
6597         MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
6598         MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
6599         MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
6600         MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12,
6601 };
6602
6603 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
6604         u8         opcode[0x10];
6605         u8         reserved_at_10[0x10];
6606
6607         u8         reserved_at_20[0x10];
6608         u8         op_mod[0x10];
6609
6610         u8         reserved_at_40[0xa0];
6611
6612         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
6613 };
6614
6615 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
6616         u8         status[0x8];
6617         u8         reserved_at_8[0x18];
6618
6619         u8         syndrome[0x20];
6620
6621         u8         reserved_at_40[0x40];
6622 };
6623
6624 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
6625         u8         opcode[0x10];
6626         u8         reserved_at_10[0x10];
6627
6628         u8         reserved_20[0x10];
6629         u8         op_mod[0x10];
6630
6631         u8         packet_reformat_id[0x20];
6632
6633         u8         reserved_60[0x20];
6634 };
6635
6636 struct mlx5_ifc_set_action_in_bits {
6637         u8         action_type[0x4];
6638         u8         field[0xc];
6639         u8         reserved_at_10[0x3];
6640         u8         offset[0x5];
6641         u8         reserved_at_18[0x3];
6642         u8         length[0x5];
6643
6644         u8         data[0x20];
6645 };
6646
6647 struct mlx5_ifc_add_action_in_bits {
6648         u8         action_type[0x4];
6649         u8         field[0xc];
6650         u8         reserved_at_10[0x10];
6651
6652         u8         data[0x20];
6653 };
6654
6655 struct mlx5_ifc_copy_action_in_bits {
6656         u8         action_type[0x4];
6657         u8         src_field[0xc];
6658         u8         reserved_at_10[0x3];
6659         u8         src_offset[0x5];
6660         u8         reserved_at_18[0x3];
6661         u8         length[0x5];
6662
6663         u8         reserved_at_20[0x4];
6664         u8         dst_field[0xc];
6665         u8         reserved_at_30[0x3];
6666         u8         dst_offset[0x5];
6667         u8         reserved_at_38[0x8];
6668 };
6669
6670 union mlx5_ifc_set_add_copy_action_in_auto_bits {
6671         struct mlx5_ifc_set_action_in_bits  set_action_in;
6672         struct mlx5_ifc_add_action_in_bits  add_action_in;
6673         struct mlx5_ifc_copy_action_in_bits copy_action_in;
6674         u8         reserved_at_0[0x40];
6675 };
6676
6677 enum {
6678         MLX5_ACTION_TYPE_SET   = 0x1,
6679         MLX5_ACTION_TYPE_ADD   = 0x2,
6680         MLX5_ACTION_TYPE_COPY  = 0x3,
6681 };
6682
6683 enum {
6684         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
6685         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
6686         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
6687         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
6688         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
6689         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
6690         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
6691         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
6692         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
6693         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
6694         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
6695         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
6696         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
6697         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
6698         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
6699         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
6700         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
6701         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
6702         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
6703         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
6704         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
6705         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
6706         MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
6707         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
6708         MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
6709         MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
6710         MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
6711         MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
6712         MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
6713         MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
6714         MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
6715         MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
6716         MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
6717         MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
6718         MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
6719         MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
6720         MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
6721         MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
6722         MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
6723 };
6724
6725 struct mlx5_ifc_alloc_modify_header_context_out_bits {
6726         u8         status[0x8];
6727         u8         reserved_at_8[0x18];
6728
6729         u8         syndrome[0x20];
6730
6731         u8         modify_header_id[0x20];
6732
6733         u8         reserved_at_60[0x20];
6734 };
6735
6736 struct mlx5_ifc_alloc_modify_header_context_in_bits {
6737         u8         opcode[0x10];
6738         u8         reserved_at_10[0x10];
6739
6740         u8         reserved_at_20[0x10];
6741         u8         op_mod[0x10];
6742
6743         u8         reserved_at_40[0x20];
6744
6745         u8         table_type[0x8];
6746         u8         reserved_at_68[0x10];
6747         u8         num_of_actions[0x8];
6748
6749         union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
6750 };
6751
6752 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
6753         u8         status[0x8];
6754         u8         reserved_at_8[0x18];
6755
6756         u8         syndrome[0x20];
6757
6758         u8         reserved_at_40[0x40];
6759 };
6760
6761 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
6762         u8         opcode[0x10];
6763         u8         reserved_at_10[0x10];
6764
6765         u8         reserved_at_20[0x10];
6766         u8         op_mod[0x10];
6767
6768         u8         modify_header_id[0x20];
6769
6770         u8         reserved_at_60[0x20];
6771 };
6772
6773 struct mlx5_ifc_query_modify_header_context_in_bits {
6774         u8         opcode[0x10];
6775         u8         uid[0x10];
6776
6777         u8         reserved_at_20[0x10];
6778         u8         op_mod[0x10];
6779
6780         u8         modify_header_id[0x20];
6781
6782         u8         reserved_at_60[0xa0];
6783 };
6784
6785 struct mlx5_ifc_query_dct_out_bits {
6786         u8         status[0x8];
6787         u8         reserved_at_8[0x18];
6788
6789         u8         syndrome[0x20];
6790
6791         u8         reserved_at_40[0x40];
6792
6793         struct mlx5_ifc_dctc_bits dct_context_entry;
6794
6795         u8         reserved_at_280[0x180];
6796 };
6797
6798 struct mlx5_ifc_query_dct_in_bits {
6799         u8         opcode[0x10];
6800         u8         reserved_at_10[0x10];
6801
6802         u8         reserved_at_20[0x10];
6803         u8         op_mod[0x10];
6804
6805         u8         reserved_at_40[0x8];
6806         u8         dctn[0x18];
6807
6808         u8         reserved_at_60[0x20];
6809 };
6810
6811 struct mlx5_ifc_query_cq_out_bits {
6812         u8         status[0x8];
6813         u8         reserved_at_8[0x18];
6814
6815         u8         syndrome[0x20];
6816
6817         u8         reserved_at_40[0x40];
6818
6819         struct mlx5_ifc_cqc_bits cq_context;
6820
6821         u8         reserved_at_280[0x600];
6822
6823         u8         pas[][0x40];
6824 };
6825
6826 struct mlx5_ifc_query_cq_in_bits {
6827         u8         opcode[0x10];
6828         u8         reserved_at_10[0x10];
6829
6830         u8         reserved_at_20[0x10];
6831         u8         op_mod[0x10];
6832
6833         u8         reserved_at_40[0x8];
6834         u8         cqn[0x18];
6835
6836         u8         reserved_at_60[0x20];
6837 };
6838
6839 struct mlx5_ifc_query_cong_status_out_bits {
6840         u8         status[0x8];
6841         u8         reserved_at_8[0x18];
6842
6843         u8         syndrome[0x20];
6844
6845         u8         reserved_at_40[0x20];
6846
6847         u8         enable[0x1];
6848         u8         tag_enable[0x1];
6849         u8         reserved_at_62[0x1e];
6850 };
6851
6852 struct mlx5_ifc_query_cong_status_in_bits {
6853         u8         opcode[0x10];
6854         u8         reserved_at_10[0x10];
6855
6856         u8         reserved_at_20[0x10];
6857         u8         op_mod[0x10];
6858
6859         u8         reserved_at_40[0x18];
6860         u8         priority[0x4];
6861         u8         cong_protocol[0x4];
6862
6863         u8         reserved_at_60[0x20];
6864 };
6865
6866 struct mlx5_ifc_query_cong_statistics_out_bits {
6867         u8         status[0x8];
6868         u8         reserved_at_8[0x18];
6869
6870         u8         syndrome[0x20];
6871
6872         u8         reserved_at_40[0x40];
6873
6874         u8         rp_cur_flows[0x20];
6875
6876         u8         sum_flows[0x20];
6877
6878         u8         rp_cnp_ignored_high[0x20];
6879
6880         u8         rp_cnp_ignored_low[0x20];
6881
6882         u8         rp_cnp_handled_high[0x20];
6883
6884         u8         rp_cnp_handled_low[0x20];
6885
6886         u8         reserved_at_140[0x100];
6887
6888         u8         time_stamp_high[0x20];
6889
6890         u8         time_stamp_low[0x20];
6891
6892         u8         accumulators_period[0x20];
6893
6894         u8         np_ecn_marked_roce_packets_high[0x20];
6895
6896         u8         np_ecn_marked_roce_packets_low[0x20];
6897
6898         u8         np_cnp_sent_high[0x20];
6899
6900         u8         np_cnp_sent_low[0x20];
6901
6902         u8         reserved_at_320[0x560];
6903 };
6904
6905 struct mlx5_ifc_query_cong_statistics_in_bits {
6906         u8         opcode[0x10];
6907         u8         reserved_at_10[0x10];
6908
6909         u8         reserved_at_20[0x10];
6910         u8         op_mod[0x10];
6911
6912         u8         clear[0x1];
6913         u8         reserved_at_41[0x1f];
6914
6915         u8         reserved_at_60[0x20];
6916 };
6917
6918 struct mlx5_ifc_query_cong_params_out_bits {
6919         u8         status[0x8];
6920         u8         reserved_at_8[0x18];
6921
6922         u8         syndrome[0x20];
6923
6924         u8         reserved_at_40[0x40];
6925
6926         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6927 };
6928
6929 struct mlx5_ifc_query_cong_params_in_bits {
6930         u8         opcode[0x10];
6931         u8         reserved_at_10[0x10];
6932
6933         u8         reserved_at_20[0x10];
6934         u8         op_mod[0x10];
6935
6936         u8         reserved_at_40[0x1c];
6937         u8         cong_protocol[0x4];
6938
6939         u8         reserved_at_60[0x20];
6940 };
6941
6942 struct mlx5_ifc_query_adapter_out_bits {
6943         u8         status[0x8];
6944         u8         reserved_at_8[0x18];
6945
6946         u8         syndrome[0x20];
6947
6948         u8         reserved_at_40[0x40];
6949
6950         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6951 };
6952
6953 struct mlx5_ifc_query_adapter_in_bits {
6954         u8         opcode[0x10];
6955         u8         reserved_at_10[0x10];
6956
6957         u8         reserved_at_20[0x10];
6958         u8         op_mod[0x10];
6959
6960         u8         reserved_at_40[0x40];
6961 };
6962
6963 struct mlx5_ifc_qp_2rst_out_bits {
6964         u8         status[0x8];
6965         u8         reserved_at_8[0x18];
6966
6967         u8         syndrome[0x20];
6968
6969         u8         reserved_at_40[0x40];
6970 };
6971
6972 struct mlx5_ifc_qp_2rst_in_bits {
6973         u8         opcode[0x10];
6974         u8         uid[0x10];
6975
6976         u8         reserved_at_20[0x10];
6977         u8         op_mod[0x10];
6978
6979         u8         reserved_at_40[0x8];
6980         u8         qpn[0x18];
6981
6982         u8         reserved_at_60[0x20];
6983 };
6984
6985 struct mlx5_ifc_qp_2err_out_bits {
6986         u8         status[0x8];
6987         u8         reserved_at_8[0x18];
6988
6989         u8         syndrome[0x20];
6990
6991         u8         reserved_at_40[0x40];
6992 };
6993
6994 struct mlx5_ifc_qp_2err_in_bits {
6995         u8         opcode[0x10];
6996         u8         uid[0x10];
6997
6998         u8         reserved_at_20[0x10];
6999         u8         op_mod[0x10];
7000
7001         u8         reserved_at_40[0x8];
7002         u8         qpn[0x18];
7003
7004         u8         reserved_at_60[0x20];
7005 };
7006
7007 struct mlx5_ifc_page_fault_resume_out_bits {
7008         u8         status[0x8];
7009         u8         reserved_at_8[0x18];
7010
7011         u8         syndrome[0x20];
7012
7013         u8         reserved_at_40[0x40];
7014 };
7015
7016 struct mlx5_ifc_page_fault_resume_in_bits {
7017         u8         opcode[0x10];
7018         u8         reserved_at_10[0x10];
7019
7020         u8         reserved_at_20[0x10];
7021         u8         op_mod[0x10];
7022
7023         u8         error[0x1];
7024         u8         reserved_at_41[0x4];
7025         u8         page_fault_type[0x3];
7026         u8         wq_number[0x18];
7027
7028         u8         reserved_at_60[0x8];
7029         u8         token[0x18];
7030 };
7031
7032 struct mlx5_ifc_nop_out_bits {
7033         u8         status[0x8];
7034         u8         reserved_at_8[0x18];
7035
7036         u8         syndrome[0x20];
7037
7038         u8         reserved_at_40[0x40];
7039 };
7040
7041 struct mlx5_ifc_nop_in_bits {
7042         u8         opcode[0x10];
7043         u8         reserved_at_10[0x10];
7044
7045         u8         reserved_at_20[0x10];
7046         u8         op_mod[0x10];
7047
7048         u8         reserved_at_40[0x40];
7049 };
7050
7051 struct mlx5_ifc_modify_vport_state_out_bits {
7052         u8         status[0x8];
7053         u8         reserved_at_8[0x18];
7054
7055         u8         syndrome[0x20];
7056
7057         u8         reserved_at_40[0x40];
7058 };
7059
7060 struct mlx5_ifc_modify_vport_state_in_bits {
7061         u8         opcode[0x10];
7062         u8         reserved_at_10[0x10];
7063
7064         u8         reserved_at_20[0x10];
7065         u8         op_mod[0x10];
7066
7067         u8         other_vport[0x1];
7068         u8         reserved_at_41[0xf];
7069         u8         vport_number[0x10];
7070
7071         u8         reserved_at_60[0x18];
7072         u8         admin_state[0x4];
7073         u8         reserved_at_7c[0x4];
7074 };
7075
7076 struct mlx5_ifc_modify_tis_out_bits {
7077         u8         status[0x8];
7078         u8         reserved_at_8[0x18];
7079
7080         u8         syndrome[0x20];
7081
7082         u8         reserved_at_40[0x40];
7083 };
7084
7085 struct mlx5_ifc_modify_tis_bitmask_bits {
7086         u8         reserved_at_0[0x20];
7087
7088         u8         reserved_at_20[0x1d];
7089         u8         lag_tx_port_affinity[0x1];
7090         u8         strict_lag_tx_port_affinity[0x1];
7091         u8         prio[0x1];
7092 };
7093
7094 struct mlx5_ifc_modify_tis_in_bits {
7095         u8         opcode[0x10];
7096         u8         uid[0x10];
7097
7098         u8         reserved_at_20[0x10];
7099         u8         op_mod[0x10];
7100
7101         u8         reserved_at_40[0x8];
7102         u8         tisn[0x18];
7103
7104         u8         reserved_at_60[0x20];
7105
7106         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
7107
7108         u8         reserved_at_c0[0x40];
7109
7110         struct mlx5_ifc_tisc_bits ctx;
7111 };
7112
7113 struct mlx5_ifc_modify_tir_bitmask_bits {
7114         u8         reserved_at_0[0x20];
7115
7116         u8         reserved_at_20[0x1b];
7117         u8         self_lb_en[0x1];
7118         u8         reserved_at_3c[0x1];
7119         u8         hash[0x1];
7120         u8         reserved_at_3e[0x1];
7121         u8         packet_merge[0x1];
7122 };
7123
7124 struct mlx5_ifc_modify_tir_out_bits {
7125         u8         status[0x8];
7126         u8         reserved_at_8[0x18];
7127
7128         u8         syndrome[0x20];
7129
7130         u8         reserved_at_40[0x40];
7131 };
7132
7133 struct mlx5_ifc_modify_tir_in_bits {
7134         u8         opcode[0x10];
7135         u8         uid[0x10];
7136
7137         u8         reserved_at_20[0x10];
7138         u8         op_mod[0x10];
7139
7140         u8         reserved_at_40[0x8];
7141         u8         tirn[0x18];
7142
7143         u8         reserved_at_60[0x20];
7144
7145         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
7146
7147         u8         reserved_at_c0[0x40];
7148
7149         struct mlx5_ifc_tirc_bits ctx;
7150 };
7151
7152 struct mlx5_ifc_modify_sq_out_bits {
7153         u8         status[0x8];
7154         u8         reserved_at_8[0x18];
7155
7156         u8         syndrome[0x20];
7157
7158         u8         reserved_at_40[0x40];
7159 };
7160
7161 struct mlx5_ifc_modify_sq_in_bits {
7162         u8         opcode[0x10];
7163         u8         uid[0x10];
7164
7165         u8         reserved_at_20[0x10];
7166         u8         op_mod[0x10];
7167
7168         u8         sq_state[0x4];
7169         u8         reserved_at_44[0x4];
7170         u8         sqn[0x18];
7171
7172         u8         reserved_at_60[0x20];
7173
7174         u8         modify_bitmask[0x40];
7175
7176         u8         reserved_at_c0[0x40];
7177
7178         struct mlx5_ifc_sqc_bits ctx;
7179 };
7180
7181 struct mlx5_ifc_modify_scheduling_element_out_bits {
7182         u8         status[0x8];
7183         u8         reserved_at_8[0x18];
7184
7185         u8         syndrome[0x20];
7186
7187         u8         reserved_at_40[0x1c0];
7188 };
7189
7190 enum {
7191         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
7192         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
7193 };
7194
7195 struct mlx5_ifc_modify_scheduling_element_in_bits {
7196         u8         opcode[0x10];
7197         u8         reserved_at_10[0x10];
7198
7199         u8         reserved_at_20[0x10];
7200         u8         op_mod[0x10];
7201
7202         u8         scheduling_hierarchy[0x8];
7203         u8         reserved_at_48[0x18];
7204
7205         u8         scheduling_element_id[0x20];
7206
7207         u8         reserved_at_80[0x20];
7208
7209         u8         modify_bitmask[0x20];
7210
7211         u8         reserved_at_c0[0x40];
7212
7213         struct mlx5_ifc_scheduling_context_bits scheduling_context;
7214
7215         u8         reserved_at_300[0x100];
7216 };
7217
7218 struct mlx5_ifc_modify_rqt_out_bits {
7219         u8         status[0x8];
7220         u8         reserved_at_8[0x18];
7221
7222         u8         syndrome[0x20];
7223
7224         u8         reserved_at_40[0x40];
7225 };
7226
7227 struct mlx5_ifc_rqt_bitmask_bits {
7228         u8         reserved_at_0[0x20];
7229
7230         u8         reserved_at_20[0x1f];
7231         u8         rqn_list[0x1];
7232 };
7233
7234 struct mlx5_ifc_modify_rqt_in_bits {
7235         u8         opcode[0x10];
7236         u8         uid[0x10];
7237
7238         u8         reserved_at_20[0x10];
7239         u8         op_mod[0x10];
7240
7241         u8         reserved_at_40[0x8];
7242         u8         rqtn[0x18];
7243
7244         u8         reserved_at_60[0x20];
7245
7246         struct mlx5_ifc_rqt_bitmask_bits bitmask;
7247
7248         u8         reserved_at_c0[0x40];
7249
7250         struct mlx5_ifc_rqtc_bits ctx;
7251 };
7252
7253 struct mlx5_ifc_modify_rq_out_bits {
7254         u8         status[0x8];
7255         u8         reserved_at_8[0x18];
7256
7257         u8         syndrome[0x20];
7258
7259         u8         reserved_at_40[0x40];
7260 };
7261
7262 enum {
7263         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
7264         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
7265         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
7266 };
7267
7268 struct mlx5_ifc_modify_rq_in_bits {
7269         u8         opcode[0x10];
7270         u8         uid[0x10];
7271
7272         u8         reserved_at_20[0x10];
7273         u8         op_mod[0x10];
7274
7275         u8         rq_state[0x4];
7276         u8         reserved_at_44[0x4];
7277         u8         rqn[0x18];
7278
7279         u8         reserved_at_60[0x20];
7280
7281         u8         modify_bitmask[0x40];
7282
7283         u8         reserved_at_c0[0x40];
7284
7285         struct mlx5_ifc_rqc_bits ctx;
7286 };
7287
7288 struct mlx5_ifc_modify_rmp_out_bits {
7289         u8         status[0x8];
7290         u8         reserved_at_8[0x18];
7291
7292         u8         syndrome[0x20];
7293
7294         u8         reserved_at_40[0x40];
7295 };
7296
7297 struct mlx5_ifc_rmp_bitmask_bits {
7298         u8         reserved_at_0[0x20];
7299
7300         u8         reserved_at_20[0x1f];
7301         u8         lwm[0x1];
7302 };
7303
7304 struct mlx5_ifc_modify_rmp_in_bits {
7305         u8         opcode[0x10];
7306         u8         uid[0x10];
7307
7308         u8         reserved_at_20[0x10];
7309         u8         op_mod[0x10];
7310
7311         u8         rmp_state[0x4];
7312         u8         reserved_at_44[0x4];
7313         u8         rmpn[0x18];
7314
7315         u8         reserved_at_60[0x20];
7316
7317         struct mlx5_ifc_rmp_bitmask_bits bitmask;
7318
7319         u8         reserved_at_c0[0x40];
7320
7321         struct mlx5_ifc_rmpc_bits ctx;
7322 };
7323
7324 struct mlx5_ifc_modify_nic_vport_context_out_bits {
7325         u8         status[0x8];
7326         u8         reserved_at_8[0x18];
7327
7328         u8         syndrome[0x20];
7329
7330         u8         reserved_at_40[0x40];
7331 };
7332
7333 struct mlx5_ifc_modify_nic_vport_field_select_bits {
7334         u8         reserved_at_0[0x12];
7335         u8         affiliation[0x1];
7336         u8         reserved_at_13[0x1];
7337         u8         disable_uc_local_lb[0x1];
7338         u8         disable_mc_local_lb[0x1];
7339         u8         node_guid[0x1];
7340         u8         port_guid[0x1];
7341         u8         min_inline[0x1];
7342         u8         mtu[0x1];
7343         u8         change_event[0x1];
7344         u8         promisc[0x1];
7345         u8         permanent_address[0x1];
7346         u8         addresses_list[0x1];
7347         u8         roce_en[0x1];
7348         u8         reserved_at_1f[0x1];
7349 };
7350
7351 struct mlx5_ifc_modify_nic_vport_context_in_bits {
7352         u8         opcode[0x10];
7353         u8         reserved_at_10[0x10];
7354
7355         u8         reserved_at_20[0x10];
7356         u8         op_mod[0x10];
7357
7358         u8         other_vport[0x1];
7359         u8         reserved_at_41[0xf];
7360         u8         vport_number[0x10];
7361
7362         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
7363
7364         u8         reserved_at_80[0x780];
7365
7366         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
7367 };
7368
7369 struct mlx5_ifc_modify_hca_vport_context_out_bits {
7370         u8         status[0x8];
7371         u8         reserved_at_8[0x18];
7372
7373         u8         syndrome[0x20];
7374
7375         u8         reserved_at_40[0x40];
7376 };
7377
7378 struct mlx5_ifc_modify_hca_vport_context_in_bits {
7379         u8         opcode[0x10];
7380         u8         reserved_at_10[0x10];
7381
7382         u8         reserved_at_20[0x10];
7383         u8         op_mod[0x10];
7384
7385         u8         other_vport[0x1];
7386         u8         reserved_at_41[0xb];
7387         u8         port_num[0x4];
7388         u8         vport_number[0x10];
7389
7390         u8         reserved_at_60[0x20];
7391
7392         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
7393 };
7394
7395 struct mlx5_ifc_modify_cq_out_bits {
7396         u8         status[0x8];
7397         u8         reserved_at_8[0x18];
7398
7399         u8         syndrome[0x20];
7400
7401         u8         reserved_at_40[0x40];
7402 };
7403
7404 enum {
7405         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
7406         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
7407 };
7408
7409 struct mlx5_ifc_modify_cq_in_bits {
7410         u8         opcode[0x10];
7411         u8         uid[0x10];
7412
7413         u8         reserved_at_20[0x10];
7414         u8         op_mod[0x10];
7415
7416         u8         reserved_at_40[0x8];
7417         u8         cqn[0x18];
7418
7419         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
7420
7421         struct mlx5_ifc_cqc_bits cq_context;
7422
7423         u8         reserved_at_280[0x60];
7424
7425         u8         cq_umem_valid[0x1];
7426         u8         reserved_at_2e1[0x1f];
7427
7428         u8         reserved_at_300[0x580];
7429
7430         u8         pas[][0x40];
7431 };
7432
7433 struct mlx5_ifc_modify_cong_status_out_bits {
7434         u8         status[0x8];
7435         u8         reserved_at_8[0x18];
7436
7437         u8         syndrome[0x20];
7438
7439         u8         reserved_at_40[0x40];
7440 };
7441
7442 struct mlx5_ifc_modify_cong_status_in_bits {
7443         u8         opcode[0x10];
7444         u8         reserved_at_10[0x10];
7445
7446         u8         reserved_at_20[0x10];
7447         u8         op_mod[0x10];
7448
7449         u8         reserved_at_40[0x18];
7450         u8         priority[0x4];
7451         u8         cong_protocol[0x4];
7452
7453         u8         enable[0x1];
7454         u8         tag_enable[0x1];
7455         u8         reserved_at_62[0x1e];
7456 };
7457
7458 struct mlx5_ifc_modify_cong_params_out_bits {
7459         u8         status[0x8];
7460         u8         reserved_at_8[0x18];
7461
7462         u8         syndrome[0x20];
7463
7464         u8         reserved_at_40[0x40];
7465 };
7466
7467 struct mlx5_ifc_modify_cong_params_in_bits {
7468         u8         opcode[0x10];
7469         u8         reserved_at_10[0x10];
7470
7471         u8         reserved_at_20[0x10];
7472         u8         op_mod[0x10];
7473
7474         u8         reserved_at_40[0x1c];
7475         u8         cong_protocol[0x4];
7476
7477         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
7478
7479         u8         reserved_at_80[0x80];
7480
7481         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7482 };
7483
7484 struct mlx5_ifc_manage_pages_out_bits {
7485         u8         status[0x8];
7486         u8         reserved_at_8[0x18];
7487
7488         u8         syndrome[0x20];
7489
7490         u8         output_num_entries[0x20];
7491
7492         u8         reserved_at_60[0x20];
7493
7494         u8         pas[][0x40];
7495 };
7496
7497 enum {
7498         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
7499         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
7500         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
7501 };
7502
7503 struct mlx5_ifc_manage_pages_in_bits {
7504         u8         opcode[0x10];
7505         u8         reserved_at_10[0x10];
7506
7507         u8         reserved_at_20[0x10];
7508         u8         op_mod[0x10];
7509
7510         u8         embedded_cpu_function[0x1];
7511         u8         reserved_at_41[0xf];
7512         u8         function_id[0x10];
7513
7514         u8         input_num_entries[0x20];
7515
7516         u8         pas[][0x40];
7517 };
7518
7519 struct mlx5_ifc_mad_ifc_out_bits {
7520         u8         status[0x8];
7521         u8         reserved_at_8[0x18];
7522
7523         u8         syndrome[0x20];
7524
7525         u8         reserved_at_40[0x40];
7526
7527         u8         response_mad_packet[256][0x8];
7528 };
7529
7530 struct mlx5_ifc_mad_ifc_in_bits {
7531         u8         opcode[0x10];
7532         u8         reserved_at_10[0x10];
7533
7534         u8         reserved_at_20[0x10];
7535         u8         op_mod[0x10];
7536
7537         u8         remote_lid[0x10];
7538         u8         reserved_at_50[0x8];
7539         u8         port[0x8];
7540
7541         u8         reserved_at_60[0x20];
7542
7543         u8         mad[256][0x8];
7544 };
7545
7546 struct mlx5_ifc_init_hca_out_bits {
7547         u8         status[0x8];
7548         u8         reserved_at_8[0x18];
7549
7550         u8         syndrome[0x20];
7551
7552         u8         reserved_at_40[0x40];
7553 };
7554
7555 struct mlx5_ifc_init_hca_in_bits {
7556         u8         opcode[0x10];
7557         u8         reserved_at_10[0x10];
7558
7559         u8         reserved_at_20[0x10];
7560         u8         op_mod[0x10];
7561
7562         u8         reserved_at_40[0x20];
7563
7564         u8         reserved_at_60[0x2];
7565         u8         sw_vhca_id[0xe];
7566         u8         reserved_at_70[0x10];
7567
7568         u8         sw_owner_id[4][0x20];
7569 };
7570
7571 struct mlx5_ifc_init2rtr_qp_out_bits {
7572         u8         status[0x8];
7573         u8         reserved_at_8[0x18];
7574
7575         u8         syndrome[0x20];
7576
7577         u8         reserved_at_40[0x20];
7578         u8         ece[0x20];
7579 };
7580
7581 struct mlx5_ifc_init2rtr_qp_in_bits {
7582         u8         opcode[0x10];
7583         u8         uid[0x10];
7584
7585         u8         reserved_at_20[0x10];
7586         u8         op_mod[0x10];
7587
7588         u8         reserved_at_40[0x8];
7589         u8         qpn[0x18];
7590
7591         u8         reserved_at_60[0x20];
7592
7593         u8         opt_param_mask[0x20];
7594
7595         u8         ece[0x20];
7596
7597         struct mlx5_ifc_qpc_bits qpc;
7598
7599         u8         reserved_at_800[0x80];
7600 };
7601
7602 struct mlx5_ifc_init2init_qp_out_bits {
7603         u8         status[0x8];
7604         u8         reserved_at_8[0x18];
7605
7606         u8         syndrome[0x20];
7607
7608         u8         reserved_at_40[0x20];
7609         u8         ece[0x20];
7610 };
7611
7612 struct mlx5_ifc_init2init_qp_in_bits {
7613         u8         opcode[0x10];
7614         u8         uid[0x10];
7615
7616         u8         reserved_at_20[0x10];
7617         u8         op_mod[0x10];
7618
7619         u8         reserved_at_40[0x8];
7620         u8         qpn[0x18];
7621
7622         u8         reserved_at_60[0x20];
7623
7624         u8         opt_param_mask[0x20];
7625
7626         u8         ece[0x20];
7627
7628         struct mlx5_ifc_qpc_bits qpc;
7629
7630         u8         reserved_at_800[0x80];
7631 };
7632
7633 struct mlx5_ifc_get_dropped_packet_log_out_bits {
7634         u8         status[0x8];
7635         u8         reserved_at_8[0x18];
7636
7637         u8         syndrome[0x20];
7638
7639         u8         reserved_at_40[0x40];
7640
7641         u8         packet_headers_log[128][0x8];
7642
7643         u8         packet_syndrome[64][0x8];
7644 };
7645
7646 struct mlx5_ifc_get_dropped_packet_log_in_bits {
7647         u8         opcode[0x10];
7648         u8         reserved_at_10[0x10];
7649
7650         u8         reserved_at_20[0x10];
7651         u8         op_mod[0x10];
7652
7653         u8         reserved_at_40[0x40];
7654 };
7655
7656 struct mlx5_ifc_gen_eqe_in_bits {
7657         u8         opcode[0x10];
7658         u8         reserved_at_10[0x10];
7659
7660         u8         reserved_at_20[0x10];
7661         u8         op_mod[0x10];
7662
7663         u8         reserved_at_40[0x18];
7664         u8         eq_number[0x8];
7665
7666         u8         reserved_at_60[0x20];
7667
7668         u8         eqe[64][0x8];
7669 };
7670
7671 struct mlx5_ifc_gen_eq_out_bits {
7672         u8         status[0x8];
7673         u8         reserved_at_8[0x18];
7674
7675         u8         syndrome[0x20];
7676
7677         u8         reserved_at_40[0x40];
7678 };
7679
7680 struct mlx5_ifc_enable_hca_out_bits {
7681         u8         status[0x8];
7682         u8         reserved_at_8[0x18];
7683
7684         u8         syndrome[0x20];
7685
7686         u8         reserved_at_40[0x20];
7687 };
7688
7689 struct mlx5_ifc_enable_hca_in_bits {
7690         u8         opcode[0x10];
7691         u8         reserved_at_10[0x10];
7692
7693         u8         reserved_at_20[0x10];
7694         u8         op_mod[0x10];
7695
7696         u8         embedded_cpu_function[0x1];
7697         u8         reserved_at_41[0xf];
7698         u8         function_id[0x10];
7699
7700         u8         reserved_at_60[0x20];
7701 };
7702
7703 struct mlx5_ifc_drain_dct_out_bits {
7704         u8         status[0x8];
7705         u8         reserved_at_8[0x18];
7706
7707         u8         syndrome[0x20];
7708
7709         u8         reserved_at_40[0x40];
7710 };
7711
7712 struct mlx5_ifc_drain_dct_in_bits {
7713         u8         opcode[0x10];
7714         u8         uid[0x10];
7715
7716         u8         reserved_at_20[0x10];
7717         u8         op_mod[0x10];
7718
7719         u8         reserved_at_40[0x8];
7720         u8         dctn[0x18];
7721
7722         u8         reserved_at_60[0x20];
7723 };
7724
7725 struct mlx5_ifc_disable_hca_out_bits {
7726         u8         status[0x8];
7727         u8         reserved_at_8[0x18];
7728
7729         u8         syndrome[0x20];
7730
7731         u8         reserved_at_40[0x20];
7732 };
7733
7734 struct mlx5_ifc_disable_hca_in_bits {
7735         u8         opcode[0x10];
7736         u8         reserved_at_10[0x10];
7737
7738         u8         reserved_at_20[0x10];
7739         u8         op_mod[0x10];
7740
7741         u8         embedded_cpu_function[0x1];
7742         u8         reserved_at_41[0xf];
7743         u8         function_id[0x10];
7744
7745         u8         reserved_at_60[0x20];
7746 };
7747
7748 struct mlx5_ifc_detach_from_mcg_out_bits {
7749         u8         status[0x8];
7750         u8         reserved_at_8[0x18];
7751
7752         u8         syndrome[0x20];
7753
7754         u8         reserved_at_40[0x40];
7755 };
7756
7757 struct mlx5_ifc_detach_from_mcg_in_bits {
7758         u8         opcode[0x10];
7759         u8         uid[0x10];
7760
7761         u8         reserved_at_20[0x10];
7762         u8         op_mod[0x10];
7763
7764         u8         reserved_at_40[0x8];
7765         u8         qpn[0x18];
7766
7767         u8         reserved_at_60[0x20];
7768
7769         u8         multicast_gid[16][0x8];
7770 };
7771
7772 struct mlx5_ifc_destroy_xrq_out_bits {
7773         u8         status[0x8];
7774         u8         reserved_at_8[0x18];
7775
7776         u8         syndrome[0x20];
7777
7778         u8         reserved_at_40[0x40];
7779 };
7780
7781 struct mlx5_ifc_destroy_xrq_in_bits {
7782         u8         opcode[0x10];
7783         u8         uid[0x10];
7784
7785         u8         reserved_at_20[0x10];
7786         u8         op_mod[0x10];
7787
7788         u8         reserved_at_40[0x8];
7789         u8         xrqn[0x18];
7790
7791         u8         reserved_at_60[0x20];
7792 };
7793
7794 struct mlx5_ifc_destroy_xrc_srq_out_bits {
7795         u8         status[0x8];
7796         u8         reserved_at_8[0x18];
7797
7798         u8         syndrome[0x20];
7799
7800         u8         reserved_at_40[0x40];
7801 };
7802
7803 struct mlx5_ifc_destroy_xrc_srq_in_bits {
7804         u8         opcode[0x10];
7805         u8         uid[0x10];
7806
7807         u8         reserved_at_20[0x10];
7808         u8         op_mod[0x10];
7809
7810         u8         reserved_at_40[0x8];
7811         u8         xrc_srqn[0x18];
7812
7813         u8         reserved_at_60[0x20];
7814 };
7815
7816 struct mlx5_ifc_destroy_tis_out_bits {
7817         u8         status[0x8];
7818         u8         reserved_at_8[0x18];
7819
7820         u8         syndrome[0x20];
7821
7822         u8         reserved_at_40[0x40];
7823 };
7824
7825 struct mlx5_ifc_destroy_tis_in_bits {
7826         u8         opcode[0x10];
7827         u8         uid[0x10];
7828
7829         u8         reserved_at_20[0x10];
7830         u8         op_mod[0x10];
7831
7832         u8         reserved_at_40[0x8];
7833         u8         tisn[0x18];
7834
7835         u8         reserved_at_60[0x20];
7836 };
7837
7838 struct mlx5_ifc_destroy_tir_out_bits {
7839         u8         status[0x8];
7840         u8         reserved_at_8[0x18];
7841
7842         u8         syndrome[0x20];
7843
7844         u8         reserved_at_40[0x40];
7845 };
7846
7847 struct mlx5_ifc_destroy_tir_in_bits {
7848         u8         opcode[0x10];
7849         u8         uid[0x10];
7850
7851         u8         reserved_at_20[0x10];
7852         u8         op_mod[0x10];
7853
7854         u8         reserved_at_40[0x8];
7855         u8         tirn[0x18];
7856
7857         u8         reserved_at_60[0x20];
7858 };
7859
7860 struct mlx5_ifc_destroy_srq_out_bits {
7861         u8         status[0x8];
7862         u8         reserved_at_8[0x18];
7863
7864         u8         syndrome[0x20];
7865
7866         u8         reserved_at_40[0x40];
7867 };
7868
7869 struct mlx5_ifc_destroy_srq_in_bits {
7870         u8         opcode[0x10];
7871         u8         uid[0x10];
7872
7873         u8         reserved_at_20[0x10];
7874         u8         op_mod[0x10];
7875
7876         u8         reserved_at_40[0x8];
7877         u8         srqn[0x18];
7878
7879         u8         reserved_at_60[0x20];
7880 };
7881
7882 struct mlx5_ifc_destroy_sq_out_bits {
7883         u8         status[0x8];
7884         u8         reserved_at_8[0x18];
7885
7886         u8         syndrome[0x20];
7887
7888         u8         reserved_at_40[0x40];
7889 };
7890
7891 struct mlx5_ifc_destroy_sq_in_bits {
7892         u8         opcode[0x10];
7893         u8         uid[0x10];
7894
7895         u8         reserved_at_20[0x10];
7896         u8         op_mod[0x10];
7897
7898         u8         reserved_at_40[0x8];
7899         u8         sqn[0x18];
7900
7901         u8         reserved_at_60[0x20];
7902 };
7903
7904 struct mlx5_ifc_destroy_scheduling_element_out_bits {
7905         u8         status[0x8];
7906         u8         reserved_at_8[0x18];
7907
7908         u8         syndrome[0x20];
7909
7910         u8         reserved_at_40[0x1c0];
7911 };
7912
7913 struct mlx5_ifc_destroy_scheduling_element_in_bits {
7914         u8         opcode[0x10];
7915         u8         reserved_at_10[0x10];
7916
7917         u8         reserved_at_20[0x10];
7918         u8         op_mod[0x10];
7919
7920         u8         scheduling_hierarchy[0x8];
7921         u8         reserved_at_48[0x18];
7922
7923         u8         scheduling_element_id[0x20];
7924
7925         u8         reserved_at_80[0x180];
7926 };
7927
7928 struct mlx5_ifc_destroy_rqt_out_bits {
7929         u8         status[0x8];
7930         u8         reserved_at_8[0x18];
7931
7932         u8         syndrome[0x20];
7933
7934         u8         reserved_at_40[0x40];
7935 };
7936
7937 struct mlx5_ifc_destroy_rqt_in_bits {
7938         u8         opcode[0x10];
7939         u8         uid[0x10];
7940
7941         u8         reserved_at_20[0x10];
7942         u8         op_mod[0x10];
7943
7944         u8         reserved_at_40[0x8];
7945         u8         rqtn[0x18];
7946
7947         u8         reserved_at_60[0x20];
7948 };
7949
7950 struct mlx5_ifc_destroy_rq_out_bits {
7951         u8         status[0x8];
7952         u8         reserved_at_8[0x18];
7953
7954         u8         syndrome[0x20];
7955
7956         u8         reserved_at_40[0x40];
7957 };
7958
7959 struct mlx5_ifc_destroy_rq_in_bits {
7960         u8         opcode[0x10];
7961         u8         uid[0x10];
7962
7963         u8         reserved_at_20[0x10];
7964         u8         op_mod[0x10];
7965
7966         u8         reserved_at_40[0x8];
7967         u8         rqn[0x18];
7968
7969         u8         reserved_at_60[0x20];
7970 };
7971
7972 struct mlx5_ifc_set_delay_drop_params_in_bits {
7973         u8         opcode[0x10];
7974         u8         reserved_at_10[0x10];
7975
7976         u8         reserved_at_20[0x10];
7977         u8         op_mod[0x10];
7978
7979         u8         reserved_at_40[0x20];
7980
7981         u8         reserved_at_60[0x10];
7982         u8         delay_drop_timeout[0x10];
7983 };
7984
7985 struct mlx5_ifc_set_delay_drop_params_out_bits {
7986         u8         status[0x8];
7987         u8         reserved_at_8[0x18];
7988
7989         u8         syndrome[0x20];
7990
7991         u8         reserved_at_40[0x40];
7992 };
7993
7994 struct mlx5_ifc_destroy_rmp_out_bits {
7995         u8         status[0x8];
7996         u8         reserved_at_8[0x18];
7997
7998         u8         syndrome[0x20];
7999
8000         u8         reserved_at_40[0x40];
8001 };
8002
8003 struct mlx5_ifc_destroy_rmp_in_bits {
8004         u8         opcode[0x10];
8005         u8         uid[0x10];
8006
8007         u8         reserved_at_20[0x10];
8008         u8         op_mod[0x10];
8009
8010         u8         reserved_at_40[0x8];
8011         u8         rmpn[0x18];
8012
8013         u8         reserved_at_60[0x20];
8014 };
8015
8016 struct mlx5_ifc_destroy_qp_out_bits {
8017         u8         status[0x8];
8018         u8         reserved_at_8[0x18];
8019
8020         u8         syndrome[0x20];
8021
8022         u8         reserved_at_40[0x40];
8023 };
8024
8025 struct mlx5_ifc_destroy_qp_in_bits {
8026         u8         opcode[0x10];
8027         u8         uid[0x10];
8028
8029         u8         reserved_at_20[0x10];
8030         u8         op_mod[0x10];
8031
8032         u8         reserved_at_40[0x8];
8033         u8         qpn[0x18];
8034
8035         u8         reserved_at_60[0x20];
8036 };
8037
8038 struct mlx5_ifc_destroy_psv_out_bits {
8039         u8         status[0x8];
8040         u8         reserved_at_8[0x18];
8041
8042         u8         syndrome[0x20];
8043
8044         u8         reserved_at_40[0x40];
8045 };
8046
8047 struct mlx5_ifc_destroy_psv_in_bits {
8048         u8         opcode[0x10];
8049         u8         reserved_at_10[0x10];
8050
8051         u8         reserved_at_20[0x10];
8052         u8         op_mod[0x10];
8053
8054         u8         reserved_at_40[0x8];
8055         u8         psvn[0x18];
8056
8057         u8         reserved_at_60[0x20];
8058 };
8059
8060 struct mlx5_ifc_destroy_mkey_out_bits {
8061         u8         status[0x8];
8062         u8         reserved_at_8[0x18];
8063
8064         u8         syndrome[0x20];
8065
8066         u8         reserved_at_40[0x40];
8067 };
8068
8069 struct mlx5_ifc_destroy_mkey_in_bits {
8070         u8         opcode[0x10];
8071         u8         uid[0x10];
8072
8073         u8         reserved_at_20[0x10];
8074         u8         op_mod[0x10];
8075
8076         u8         reserved_at_40[0x8];
8077         u8         mkey_index[0x18];
8078
8079         u8         reserved_at_60[0x20];
8080 };
8081
8082 struct mlx5_ifc_destroy_flow_table_out_bits {
8083         u8         status[0x8];
8084         u8         reserved_at_8[0x18];
8085
8086         u8         syndrome[0x20];
8087
8088         u8         reserved_at_40[0x40];
8089 };
8090
8091 struct mlx5_ifc_destroy_flow_table_in_bits {
8092         u8         opcode[0x10];
8093         u8         reserved_at_10[0x10];
8094
8095         u8         reserved_at_20[0x10];
8096         u8         op_mod[0x10];
8097
8098         u8         other_vport[0x1];
8099         u8         reserved_at_41[0xf];
8100         u8         vport_number[0x10];
8101
8102         u8         reserved_at_60[0x20];
8103
8104         u8         table_type[0x8];
8105         u8         reserved_at_88[0x18];
8106
8107         u8         reserved_at_a0[0x8];
8108         u8         table_id[0x18];
8109
8110         u8         reserved_at_c0[0x140];
8111 };
8112
8113 struct mlx5_ifc_destroy_flow_group_out_bits {
8114         u8         status[0x8];
8115         u8         reserved_at_8[0x18];
8116
8117         u8         syndrome[0x20];
8118
8119         u8         reserved_at_40[0x40];
8120 };
8121
8122 struct mlx5_ifc_destroy_flow_group_in_bits {
8123         u8         opcode[0x10];
8124         u8         reserved_at_10[0x10];
8125
8126         u8         reserved_at_20[0x10];
8127         u8         op_mod[0x10];
8128
8129         u8         other_vport[0x1];
8130         u8         reserved_at_41[0xf];
8131         u8         vport_number[0x10];
8132
8133         u8         reserved_at_60[0x20];
8134
8135         u8         table_type[0x8];
8136         u8         reserved_at_88[0x18];
8137
8138         u8         reserved_at_a0[0x8];
8139         u8         table_id[0x18];
8140
8141         u8         group_id[0x20];
8142
8143         u8         reserved_at_e0[0x120];
8144 };
8145
8146 struct mlx5_ifc_destroy_eq_out_bits {
8147         u8         status[0x8];
8148         u8         reserved_at_8[0x18];
8149
8150         u8         syndrome[0x20];
8151
8152         u8         reserved_at_40[0x40];
8153 };
8154
8155 struct mlx5_ifc_destroy_eq_in_bits {
8156         u8         opcode[0x10];
8157         u8         reserved_at_10[0x10];
8158
8159         u8         reserved_at_20[0x10];
8160         u8         op_mod[0x10];
8161
8162         u8         reserved_at_40[0x18];
8163         u8         eq_number[0x8];
8164
8165         u8         reserved_at_60[0x20];
8166 };
8167
8168 struct mlx5_ifc_destroy_dct_out_bits {
8169         u8         status[0x8];
8170         u8         reserved_at_8[0x18];
8171
8172         u8         syndrome[0x20];
8173
8174         u8         reserved_at_40[0x40];
8175 };
8176
8177 struct mlx5_ifc_destroy_dct_in_bits {
8178         u8         opcode[0x10];
8179         u8         uid[0x10];
8180
8181         u8         reserved_at_20[0x10];
8182         u8         op_mod[0x10];
8183
8184         u8         reserved_at_40[0x8];
8185         u8         dctn[0x18];
8186
8187         u8         reserved_at_60[0x20];
8188 };
8189
8190 struct mlx5_ifc_destroy_cq_out_bits {
8191         u8         status[0x8];
8192         u8         reserved_at_8[0x18];
8193
8194         u8         syndrome[0x20];
8195
8196         u8         reserved_at_40[0x40];
8197 };
8198
8199 struct mlx5_ifc_destroy_cq_in_bits {
8200         u8         opcode[0x10];
8201         u8         uid[0x10];
8202
8203         u8         reserved_at_20[0x10];
8204         u8         op_mod[0x10];
8205
8206         u8         reserved_at_40[0x8];
8207         u8         cqn[0x18];
8208
8209         u8         reserved_at_60[0x20];
8210 };
8211
8212 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
8213         u8         status[0x8];
8214         u8         reserved_at_8[0x18];
8215
8216         u8         syndrome[0x20];
8217
8218         u8         reserved_at_40[0x40];
8219 };
8220
8221 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
8222         u8         opcode[0x10];
8223         u8         reserved_at_10[0x10];
8224
8225         u8         reserved_at_20[0x10];
8226         u8         op_mod[0x10];
8227
8228         u8         reserved_at_40[0x20];
8229
8230         u8         reserved_at_60[0x10];
8231         u8         vxlan_udp_port[0x10];
8232 };
8233
8234 struct mlx5_ifc_delete_l2_table_entry_out_bits {
8235         u8         status[0x8];
8236         u8         reserved_at_8[0x18];
8237
8238         u8         syndrome[0x20];
8239
8240         u8         reserved_at_40[0x40];
8241 };
8242
8243 struct mlx5_ifc_delete_l2_table_entry_in_bits {
8244         u8         opcode[0x10];
8245         u8         reserved_at_10[0x10];
8246
8247         u8         reserved_at_20[0x10];
8248         u8         op_mod[0x10];
8249
8250         u8         reserved_at_40[0x60];
8251
8252         u8         reserved_at_a0[0x8];
8253         u8         table_index[0x18];
8254
8255         u8         reserved_at_c0[0x140];
8256 };
8257
8258 struct mlx5_ifc_delete_fte_out_bits {
8259         u8         status[0x8];
8260         u8         reserved_at_8[0x18];
8261
8262         u8         syndrome[0x20];
8263
8264         u8         reserved_at_40[0x40];
8265 };
8266
8267 struct mlx5_ifc_delete_fte_in_bits {
8268         u8         opcode[0x10];
8269         u8         reserved_at_10[0x10];
8270
8271         u8         reserved_at_20[0x10];
8272         u8         op_mod[0x10];
8273
8274         u8         other_vport[0x1];
8275         u8         reserved_at_41[0xf];
8276         u8         vport_number[0x10];
8277
8278         u8         reserved_at_60[0x20];
8279
8280         u8         table_type[0x8];
8281         u8         reserved_at_88[0x18];
8282
8283         u8         reserved_at_a0[0x8];
8284         u8         table_id[0x18];
8285
8286         u8         reserved_at_c0[0x40];
8287
8288         u8         flow_index[0x20];
8289
8290         u8         reserved_at_120[0xe0];
8291 };
8292
8293 struct mlx5_ifc_dealloc_xrcd_out_bits {
8294         u8         status[0x8];
8295         u8         reserved_at_8[0x18];
8296
8297         u8         syndrome[0x20];
8298
8299         u8         reserved_at_40[0x40];
8300 };
8301
8302 struct mlx5_ifc_dealloc_xrcd_in_bits {
8303         u8         opcode[0x10];
8304         u8         uid[0x10];
8305
8306         u8         reserved_at_20[0x10];
8307         u8         op_mod[0x10];
8308
8309         u8         reserved_at_40[0x8];
8310         u8         xrcd[0x18];
8311
8312         u8         reserved_at_60[0x20];
8313 };
8314
8315 struct mlx5_ifc_dealloc_uar_out_bits {
8316         u8         status[0x8];
8317         u8         reserved_at_8[0x18];
8318
8319         u8         syndrome[0x20];
8320
8321         u8         reserved_at_40[0x40];
8322 };
8323
8324 struct mlx5_ifc_dealloc_uar_in_bits {
8325         u8         opcode[0x10];
8326         u8         uid[0x10];
8327
8328         u8         reserved_at_20[0x10];
8329         u8         op_mod[0x10];
8330
8331         u8         reserved_at_40[0x8];
8332         u8         uar[0x18];
8333
8334         u8         reserved_at_60[0x20];
8335 };
8336
8337 struct mlx5_ifc_dealloc_transport_domain_out_bits {
8338         u8         status[0x8];
8339         u8         reserved_at_8[0x18];
8340
8341         u8         syndrome[0x20];
8342
8343         u8         reserved_at_40[0x40];
8344 };
8345
8346 struct mlx5_ifc_dealloc_transport_domain_in_bits {
8347         u8         opcode[0x10];
8348         u8         uid[0x10];
8349
8350         u8         reserved_at_20[0x10];
8351         u8         op_mod[0x10];
8352
8353         u8         reserved_at_40[0x8];
8354         u8         transport_domain[0x18];
8355
8356         u8         reserved_at_60[0x20];
8357 };
8358
8359 struct mlx5_ifc_dealloc_q_counter_out_bits {
8360         u8         status[0x8];
8361         u8         reserved_at_8[0x18];
8362
8363         u8         syndrome[0x20];
8364
8365         u8         reserved_at_40[0x40];
8366 };
8367
8368 struct mlx5_ifc_dealloc_q_counter_in_bits {
8369         u8         opcode[0x10];
8370         u8         reserved_at_10[0x10];
8371
8372         u8         reserved_at_20[0x10];
8373         u8         op_mod[0x10];
8374
8375         u8         reserved_at_40[0x18];
8376         u8         counter_set_id[0x8];
8377
8378         u8         reserved_at_60[0x20];
8379 };
8380
8381 struct mlx5_ifc_dealloc_pd_out_bits {
8382         u8         status[0x8];
8383         u8         reserved_at_8[0x18];
8384
8385         u8         syndrome[0x20];
8386
8387         u8         reserved_at_40[0x40];
8388 };
8389
8390 struct mlx5_ifc_dealloc_pd_in_bits {
8391         u8         opcode[0x10];
8392         u8         uid[0x10];
8393
8394         u8         reserved_at_20[0x10];
8395         u8         op_mod[0x10];
8396
8397         u8         reserved_at_40[0x8];
8398         u8         pd[0x18];
8399
8400         u8         reserved_at_60[0x20];
8401 };
8402
8403 struct mlx5_ifc_dealloc_flow_counter_out_bits {
8404         u8         status[0x8];
8405         u8         reserved_at_8[0x18];
8406
8407         u8         syndrome[0x20];
8408
8409         u8         reserved_at_40[0x40];
8410 };
8411
8412 struct mlx5_ifc_dealloc_flow_counter_in_bits {
8413         u8         opcode[0x10];
8414         u8         reserved_at_10[0x10];
8415
8416         u8         reserved_at_20[0x10];
8417         u8         op_mod[0x10];
8418
8419         u8         flow_counter_id[0x20];
8420
8421         u8         reserved_at_60[0x20];
8422 };
8423
8424 struct mlx5_ifc_create_xrq_out_bits {
8425         u8         status[0x8];
8426         u8         reserved_at_8[0x18];
8427
8428         u8         syndrome[0x20];
8429
8430         u8         reserved_at_40[0x8];
8431         u8         xrqn[0x18];
8432
8433         u8         reserved_at_60[0x20];
8434 };
8435
8436 struct mlx5_ifc_create_xrq_in_bits {
8437         u8         opcode[0x10];
8438         u8         uid[0x10];
8439
8440         u8         reserved_at_20[0x10];
8441         u8         op_mod[0x10];
8442
8443         u8         reserved_at_40[0x40];
8444
8445         struct mlx5_ifc_xrqc_bits xrq_context;
8446 };
8447
8448 struct mlx5_ifc_create_xrc_srq_out_bits {
8449         u8         status[0x8];
8450         u8         reserved_at_8[0x18];
8451
8452         u8         syndrome[0x20];
8453
8454         u8         reserved_at_40[0x8];
8455         u8         xrc_srqn[0x18];
8456
8457         u8         reserved_at_60[0x20];
8458 };
8459
8460 struct mlx5_ifc_create_xrc_srq_in_bits {
8461         u8         opcode[0x10];
8462         u8         uid[0x10];
8463
8464         u8         reserved_at_20[0x10];
8465         u8         op_mod[0x10];
8466
8467         u8         reserved_at_40[0x40];
8468
8469         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
8470
8471         u8         reserved_at_280[0x60];
8472
8473         u8         xrc_srq_umem_valid[0x1];
8474         u8         reserved_at_2e1[0x1f];
8475
8476         u8         reserved_at_300[0x580];
8477
8478         u8         pas[][0x40];
8479 };
8480
8481 struct mlx5_ifc_create_tis_out_bits {
8482         u8         status[0x8];
8483         u8         reserved_at_8[0x18];
8484
8485         u8         syndrome[0x20];
8486
8487         u8         reserved_at_40[0x8];
8488         u8         tisn[0x18];
8489
8490         u8         reserved_at_60[0x20];
8491 };
8492
8493 struct mlx5_ifc_create_tis_in_bits {
8494         u8         opcode[0x10];
8495         u8         uid[0x10];
8496
8497         u8         reserved_at_20[0x10];
8498         u8         op_mod[0x10];
8499
8500         u8         reserved_at_40[0xc0];
8501
8502         struct mlx5_ifc_tisc_bits ctx;
8503 };
8504
8505 struct mlx5_ifc_create_tir_out_bits {
8506         u8         status[0x8];
8507         u8         icm_address_63_40[0x18];
8508
8509         u8         syndrome[0x20];
8510
8511         u8         icm_address_39_32[0x8];
8512         u8         tirn[0x18];
8513
8514         u8         icm_address_31_0[0x20];
8515 };
8516
8517 struct mlx5_ifc_create_tir_in_bits {
8518         u8         opcode[0x10];
8519         u8         uid[0x10];
8520
8521         u8         reserved_at_20[0x10];
8522         u8         op_mod[0x10];
8523
8524         u8         reserved_at_40[0xc0];
8525
8526         struct mlx5_ifc_tirc_bits ctx;
8527 };
8528
8529 struct mlx5_ifc_create_srq_out_bits {
8530         u8         status[0x8];
8531         u8         reserved_at_8[0x18];
8532
8533         u8         syndrome[0x20];
8534
8535         u8         reserved_at_40[0x8];
8536         u8         srqn[0x18];
8537
8538         u8         reserved_at_60[0x20];
8539 };
8540
8541 struct mlx5_ifc_create_srq_in_bits {
8542         u8         opcode[0x10];
8543         u8         uid[0x10];
8544
8545         u8         reserved_at_20[0x10];
8546         u8         op_mod[0x10];
8547
8548         u8         reserved_at_40[0x40];
8549
8550         struct mlx5_ifc_srqc_bits srq_context_entry;
8551
8552         u8         reserved_at_280[0x600];
8553
8554         u8         pas[][0x40];
8555 };
8556
8557 struct mlx5_ifc_create_sq_out_bits {
8558         u8         status[0x8];
8559         u8         reserved_at_8[0x18];
8560
8561         u8         syndrome[0x20];
8562
8563         u8         reserved_at_40[0x8];
8564         u8         sqn[0x18];
8565
8566         u8         reserved_at_60[0x20];
8567 };
8568
8569 struct mlx5_ifc_create_sq_in_bits {
8570         u8         opcode[0x10];
8571         u8         uid[0x10];
8572
8573         u8         reserved_at_20[0x10];
8574         u8         op_mod[0x10];
8575
8576         u8         reserved_at_40[0xc0];
8577
8578         struct mlx5_ifc_sqc_bits ctx;
8579 };
8580
8581 struct mlx5_ifc_create_scheduling_element_out_bits {
8582         u8         status[0x8];
8583         u8         reserved_at_8[0x18];
8584
8585         u8         syndrome[0x20];
8586
8587         u8         reserved_at_40[0x40];
8588
8589         u8         scheduling_element_id[0x20];
8590
8591         u8         reserved_at_a0[0x160];
8592 };
8593
8594 struct mlx5_ifc_create_scheduling_element_in_bits {
8595         u8         opcode[0x10];
8596         u8         reserved_at_10[0x10];
8597
8598         u8         reserved_at_20[0x10];
8599         u8         op_mod[0x10];
8600
8601         u8         scheduling_hierarchy[0x8];
8602         u8         reserved_at_48[0x18];
8603
8604         u8         reserved_at_60[0xa0];
8605
8606         struct mlx5_ifc_scheduling_context_bits scheduling_context;
8607
8608         u8         reserved_at_300[0x100];
8609 };
8610
8611 struct mlx5_ifc_create_rqt_out_bits {
8612         u8         status[0x8];
8613         u8         reserved_at_8[0x18];
8614
8615         u8         syndrome[0x20];
8616
8617         u8         reserved_at_40[0x8];
8618         u8         rqtn[0x18];
8619
8620         u8         reserved_at_60[0x20];
8621 };
8622
8623 struct mlx5_ifc_create_rqt_in_bits {
8624         u8         opcode[0x10];
8625         u8         uid[0x10];
8626
8627         u8         reserved_at_20[0x10];
8628         u8         op_mod[0x10];
8629
8630         u8         reserved_at_40[0xc0];
8631
8632         struct mlx5_ifc_rqtc_bits rqt_context;
8633 };
8634
8635 struct mlx5_ifc_create_rq_out_bits {
8636         u8         status[0x8];
8637         u8         reserved_at_8[0x18];
8638
8639         u8         syndrome[0x20];
8640
8641         u8         reserved_at_40[0x8];
8642         u8         rqn[0x18];
8643
8644         u8         reserved_at_60[0x20];
8645 };
8646
8647 struct mlx5_ifc_create_rq_in_bits {
8648         u8         opcode[0x10];
8649         u8         uid[0x10];
8650
8651         u8         reserved_at_20[0x10];
8652         u8         op_mod[0x10];
8653
8654         u8         reserved_at_40[0xc0];
8655
8656         struct mlx5_ifc_rqc_bits ctx;
8657 };
8658
8659 struct mlx5_ifc_create_rmp_out_bits {
8660         u8         status[0x8];
8661         u8         reserved_at_8[0x18];
8662
8663         u8         syndrome[0x20];
8664
8665         u8         reserved_at_40[0x8];
8666         u8         rmpn[0x18];
8667
8668         u8         reserved_at_60[0x20];
8669 };
8670
8671 struct mlx5_ifc_create_rmp_in_bits {
8672         u8         opcode[0x10];
8673         u8         uid[0x10];
8674
8675         u8         reserved_at_20[0x10];
8676         u8         op_mod[0x10];
8677
8678         u8         reserved_at_40[0xc0];
8679
8680         struct mlx5_ifc_rmpc_bits ctx;
8681 };
8682
8683 struct mlx5_ifc_create_qp_out_bits {
8684         u8         status[0x8];
8685         u8         reserved_at_8[0x18];
8686
8687         u8         syndrome[0x20];
8688
8689         u8         reserved_at_40[0x8];
8690         u8         qpn[0x18];
8691
8692         u8         ece[0x20];
8693 };
8694
8695 struct mlx5_ifc_create_qp_in_bits {
8696         u8         opcode[0x10];
8697         u8         uid[0x10];
8698
8699         u8         reserved_at_20[0x10];
8700         u8         op_mod[0x10];
8701
8702         u8         qpc_ext[0x1];
8703         u8         reserved_at_41[0x7];
8704         u8         input_qpn[0x18];
8705
8706         u8         reserved_at_60[0x20];
8707         u8         opt_param_mask[0x20];
8708
8709         u8         ece[0x20];
8710
8711         struct mlx5_ifc_qpc_bits qpc;
8712
8713         u8         reserved_at_800[0x60];
8714
8715         u8         wq_umem_valid[0x1];
8716         u8         reserved_at_861[0x1f];
8717
8718         u8         pas[][0x40];
8719 };
8720
8721 struct mlx5_ifc_create_psv_out_bits {
8722         u8         status[0x8];
8723         u8         reserved_at_8[0x18];
8724
8725         u8         syndrome[0x20];
8726
8727         u8         reserved_at_40[0x40];
8728
8729         u8         reserved_at_80[0x8];
8730         u8         psv0_index[0x18];
8731
8732         u8         reserved_at_a0[0x8];
8733         u8         psv1_index[0x18];
8734
8735         u8         reserved_at_c0[0x8];
8736         u8         psv2_index[0x18];
8737
8738         u8         reserved_at_e0[0x8];
8739         u8         psv3_index[0x18];
8740 };
8741
8742 struct mlx5_ifc_create_psv_in_bits {
8743         u8         opcode[0x10];
8744         u8         reserved_at_10[0x10];
8745
8746         u8         reserved_at_20[0x10];
8747         u8         op_mod[0x10];
8748
8749         u8         num_psv[0x4];
8750         u8         reserved_at_44[0x4];
8751         u8         pd[0x18];
8752
8753         u8         reserved_at_60[0x20];
8754 };
8755
8756 struct mlx5_ifc_create_mkey_out_bits {
8757         u8         status[0x8];
8758         u8         reserved_at_8[0x18];
8759
8760         u8         syndrome[0x20];
8761
8762         u8         reserved_at_40[0x8];
8763         u8         mkey_index[0x18];
8764
8765         u8         reserved_at_60[0x20];
8766 };
8767
8768 struct mlx5_ifc_create_mkey_in_bits {
8769         u8         opcode[0x10];
8770         u8         uid[0x10];
8771
8772         u8         reserved_at_20[0x10];
8773         u8         op_mod[0x10];
8774
8775         u8         reserved_at_40[0x20];
8776
8777         u8         pg_access[0x1];
8778         u8         mkey_umem_valid[0x1];
8779         u8         reserved_at_62[0x1e];
8780
8781         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8782
8783         u8         reserved_at_280[0x80];
8784
8785         u8         translations_octword_actual_size[0x20];
8786
8787         u8         reserved_at_320[0x560];
8788
8789         u8         klm_pas_mtt[][0x20];
8790 };
8791
8792 enum {
8793         MLX5_FLOW_TABLE_TYPE_NIC_RX             = 0x0,
8794         MLX5_FLOW_TABLE_TYPE_NIC_TX             = 0x1,
8795         MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL     = 0x2,
8796         MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL    = 0x3,
8797         MLX5_FLOW_TABLE_TYPE_FDB                = 0X4,
8798         MLX5_FLOW_TABLE_TYPE_SNIFFER_RX         = 0X5,
8799         MLX5_FLOW_TABLE_TYPE_SNIFFER_TX         = 0X6,
8800 };
8801
8802 struct mlx5_ifc_create_flow_table_out_bits {
8803         u8         status[0x8];
8804         u8         icm_address_63_40[0x18];
8805
8806         u8         syndrome[0x20];
8807
8808         u8         icm_address_39_32[0x8];
8809         u8         table_id[0x18];
8810
8811         u8         icm_address_31_0[0x20];
8812 };
8813
8814 struct mlx5_ifc_create_flow_table_in_bits {
8815         u8         opcode[0x10];
8816         u8         uid[0x10];
8817
8818         u8         reserved_at_20[0x10];
8819         u8         op_mod[0x10];
8820
8821         u8         other_vport[0x1];
8822         u8         reserved_at_41[0xf];
8823         u8         vport_number[0x10];
8824
8825         u8         reserved_at_60[0x20];
8826
8827         u8         table_type[0x8];
8828         u8         reserved_at_88[0x18];
8829
8830         u8         reserved_at_a0[0x20];
8831
8832         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8833 };
8834
8835 struct mlx5_ifc_create_flow_group_out_bits {
8836         u8         status[0x8];
8837         u8         reserved_at_8[0x18];
8838
8839         u8         syndrome[0x20];
8840
8841         u8         reserved_at_40[0x8];
8842         u8         group_id[0x18];
8843
8844         u8         reserved_at_60[0x20];
8845 };
8846
8847 enum {
8848         MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE  = 0x0,
8849         MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT     = 0x1,
8850 };
8851
8852 enum {
8853         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
8854         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
8855         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
8856         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
8857 };
8858
8859 struct mlx5_ifc_create_flow_group_in_bits {
8860         u8         opcode[0x10];
8861         u8         reserved_at_10[0x10];
8862
8863         u8         reserved_at_20[0x10];
8864         u8         op_mod[0x10];
8865
8866         u8         other_vport[0x1];
8867         u8         reserved_at_41[0xf];
8868         u8         vport_number[0x10];
8869
8870         u8         reserved_at_60[0x20];
8871
8872         u8         table_type[0x8];
8873         u8         reserved_at_88[0x4];
8874         u8         group_type[0x4];
8875         u8         reserved_at_90[0x10];
8876
8877         u8         reserved_at_a0[0x8];
8878         u8         table_id[0x18];
8879
8880         u8         source_eswitch_owner_vhca_id_valid[0x1];
8881
8882         u8         reserved_at_c1[0x1f];
8883
8884         u8         start_flow_index[0x20];
8885
8886         u8         reserved_at_100[0x20];
8887
8888         u8         end_flow_index[0x20];
8889
8890         u8         reserved_at_140[0x10];
8891         u8         match_definer_id[0x10];
8892
8893         u8         reserved_at_160[0x80];
8894
8895         u8         reserved_at_1e0[0x18];
8896         u8         match_criteria_enable[0x8];
8897
8898         struct mlx5_ifc_fte_match_param_bits match_criteria;
8899
8900         u8         reserved_at_1200[0xe00];
8901 };
8902
8903 struct mlx5_ifc_create_eq_out_bits {
8904         u8         status[0x8];
8905         u8         reserved_at_8[0x18];
8906
8907         u8         syndrome[0x20];
8908
8909         u8         reserved_at_40[0x18];
8910         u8         eq_number[0x8];
8911
8912         u8         reserved_at_60[0x20];
8913 };
8914
8915 struct mlx5_ifc_create_eq_in_bits {
8916         u8         opcode[0x10];
8917         u8         uid[0x10];
8918
8919         u8         reserved_at_20[0x10];
8920         u8         op_mod[0x10];
8921
8922         u8         reserved_at_40[0x40];
8923
8924         struct mlx5_ifc_eqc_bits eq_context_entry;
8925
8926         u8         reserved_at_280[0x40];
8927
8928         u8         event_bitmask[4][0x40];
8929
8930         u8         reserved_at_3c0[0x4c0];
8931
8932         u8         pas[][0x40];
8933 };
8934
8935 struct mlx5_ifc_create_dct_out_bits {
8936         u8         status[0x8];
8937         u8         reserved_at_8[0x18];
8938
8939         u8         syndrome[0x20];
8940
8941         u8         reserved_at_40[0x8];
8942         u8         dctn[0x18];
8943
8944         u8         ece[0x20];
8945 };
8946
8947 struct mlx5_ifc_create_dct_in_bits {
8948         u8         opcode[0x10];
8949         u8         uid[0x10];
8950
8951         u8         reserved_at_20[0x10];
8952         u8         op_mod[0x10];
8953
8954         u8         reserved_at_40[0x40];
8955
8956         struct mlx5_ifc_dctc_bits dct_context_entry;
8957
8958         u8         reserved_at_280[0x180];
8959 };
8960
8961 struct mlx5_ifc_create_cq_out_bits {
8962         u8         status[0x8];
8963         u8         reserved_at_8[0x18];
8964
8965         u8         syndrome[0x20];
8966
8967         u8         reserved_at_40[0x8];
8968         u8         cqn[0x18];
8969
8970         u8         reserved_at_60[0x20];
8971 };
8972
8973 struct mlx5_ifc_create_cq_in_bits {
8974         u8         opcode[0x10];
8975         u8         uid[0x10];
8976
8977         u8         reserved_at_20[0x10];
8978         u8         op_mod[0x10];
8979
8980         u8         reserved_at_40[0x40];
8981
8982         struct mlx5_ifc_cqc_bits cq_context;
8983
8984         u8         reserved_at_280[0x60];
8985
8986         u8         cq_umem_valid[0x1];
8987         u8         reserved_at_2e1[0x59f];
8988
8989         u8         pas[][0x40];
8990 };
8991
8992 struct mlx5_ifc_config_int_moderation_out_bits {
8993         u8         status[0x8];
8994         u8         reserved_at_8[0x18];
8995
8996         u8         syndrome[0x20];
8997
8998         u8         reserved_at_40[0x4];
8999         u8         min_delay[0xc];
9000         u8         int_vector[0x10];
9001
9002         u8         reserved_at_60[0x20];
9003 };
9004
9005 enum {
9006         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
9007         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
9008 };
9009
9010 struct mlx5_ifc_config_int_moderation_in_bits {
9011         u8         opcode[0x10];
9012         u8         reserved_at_10[0x10];
9013
9014         u8         reserved_at_20[0x10];
9015         u8         op_mod[0x10];
9016
9017         u8         reserved_at_40[0x4];
9018         u8         min_delay[0xc];
9019         u8         int_vector[0x10];
9020
9021         u8         reserved_at_60[0x20];
9022 };
9023
9024 struct mlx5_ifc_attach_to_mcg_out_bits {
9025         u8         status[0x8];
9026         u8         reserved_at_8[0x18];
9027
9028         u8         syndrome[0x20];
9029
9030         u8         reserved_at_40[0x40];
9031 };
9032
9033 struct mlx5_ifc_attach_to_mcg_in_bits {
9034         u8         opcode[0x10];
9035         u8         uid[0x10];
9036
9037         u8         reserved_at_20[0x10];
9038         u8         op_mod[0x10];
9039
9040         u8         reserved_at_40[0x8];
9041         u8         qpn[0x18];
9042
9043         u8         reserved_at_60[0x20];
9044
9045         u8         multicast_gid[16][0x8];
9046 };
9047
9048 struct mlx5_ifc_arm_xrq_out_bits {
9049         u8         status[0x8];
9050         u8         reserved_at_8[0x18];
9051
9052         u8         syndrome[0x20];
9053
9054         u8         reserved_at_40[0x40];
9055 };
9056
9057 struct mlx5_ifc_arm_xrq_in_bits {
9058         u8         opcode[0x10];
9059         u8         reserved_at_10[0x10];
9060
9061         u8         reserved_at_20[0x10];
9062         u8         op_mod[0x10];
9063
9064         u8         reserved_at_40[0x8];
9065         u8         xrqn[0x18];
9066
9067         u8         reserved_at_60[0x10];
9068         u8         lwm[0x10];
9069 };
9070
9071 struct mlx5_ifc_arm_xrc_srq_out_bits {
9072         u8         status[0x8];
9073         u8         reserved_at_8[0x18];
9074
9075         u8         syndrome[0x20];
9076
9077         u8         reserved_at_40[0x40];
9078 };
9079
9080 enum {
9081         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
9082 };
9083
9084 struct mlx5_ifc_arm_xrc_srq_in_bits {
9085         u8         opcode[0x10];
9086         u8         uid[0x10];
9087
9088         u8         reserved_at_20[0x10];
9089         u8         op_mod[0x10];
9090
9091         u8         reserved_at_40[0x8];
9092         u8         xrc_srqn[0x18];
9093
9094         u8         reserved_at_60[0x10];
9095         u8         lwm[0x10];
9096 };
9097
9098 struct mlx5_ifc_arm_rq_out_bits {
9099         u8         status[0x8];
9100         u8         reserved_at_8[0x18];
9101
9102         u8         syndrome[0x20];
9103
9104         u8         reserved_at_40[0x40];
9105 };
9106
9107 enum {
9108         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
9109         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
9110 };
9111
9112 struct mlx5_ifc_arm_rq_in_bits {
9113         u8         opcode[0x10];
9114         u8         uid[0x10];
9115
9116         u8         reserved_at_20[0x10];
9117         u8         op_mod[0x10];
9118
9119         u8         reserved_at_40[0x8];
9120         u8         srq_number[0x18];
9121
9122         u8         reserved_at_60[0x10];
9123         u8         lwm[0x10];
9124 };
9125
9126 struct mlx5_ifc_arm_dct_out_bits {
9127         u8         status[0x8];
9128         u8         reserved_at_8[0x18];
9129
9130         u8         syndrome[0x20];
9131
9132         u8         reserved_at_40[0x40];
9133 };
9134
9135 struct mlx5_ifc_arm_dct_in_bits {
9136         u8         opcode[0x10];
9137         u8         reserved_at_10[0x10];
9138
9139         u8         reserved_at_20[0x10];
9140         u8         op_mod[0x10];
9141
9142         u8         reserved_at_40[0x8];
9143         u8         dct_number[0x18];
9144
9145         u8         reserved_at_60[0x20];
9146 };
9147
9148 struct mlx5_ifc_alloc_xrcd_out_bits {
9149         u8         status[0x8];
9150         u8         reserved_at_8[0x18];
9151
9152         u8         syndrome[0x20];
9153
9154         u8         reserved_at_40[0x8];
9155         u8         xrcd[0x18];
9156
9157         u8         reserved_at_60[0x20];
9158 };
9159
9160 struct mlx5_ifc_alloc_xrcd_in_bits {
9161         u8         opcode[0x10];
9162         u8         uid[0x10];
9163
9164         u8         reserved_at_20[0x10];
9165         u8         op_mod[0x10];
9166
9167         u8         reserved_at_40[0x40];
9168 };
9169
9170 struct mlx5_ifc_alloc_uar_out_bits {
9171         u8         status[0x8];
9172         u8         reserved_at_8[0x18];
9173
9174         u8         syndrome[0x20];
9175
9176         u8         reserved_at_40[0x8];
9177         u8         uar[0x18];
9178
9179         u8         reserved_at_60[0x20];
9180 };
9181
9182 struct mlx5_ifc_alloc_uar_in_bits {
9183         u8         opcode[0x10];
9184         u8         uid[0x10];
9185
9186         u8         reserved_at_20[0x10];
9187         u8         op_mod[0x10];
9188
9189         u8         reserved_at_40[0x40];
9190 };
9191
9192 struct mlx5_ifc_alloc_transport_domain_out_bits {
9193         u8         status[0x8];
9194         u8         reserved_at_8[0x18];
9195
9196         u8         syndrome[0x20];
9197
9198         u8         reserved_at_40[0x8];
9199         u8         transport_domain[0x18];
9200
9201         u8         reserved_at_60[0x20];
9202 };
9203
9204 struct mlx5_ifc_alloc_transport_domain_in_bits {
9205         u8         opcode[0x10];
9206         u8         uid[0x10];
9207
9208         u8         reserved_at_20[0x10];
9209         u8         op_mod[0x10];
9210
9211         u8         reserved_at_40[0x40];
9212 };
9213
9214 struct mlx5_ifc_alloc_q_counter_out_bits {
9215         u8         status[0x8];
9216         u8         reserved_at_8[0x18];
9217
9218         u8         syndrome[0x20];
9219
9220         u8         reserved_at_40[0x18];
9221         u8         counter_set_id[0x8];
9222
9223         u8         reserved_at_60[0x20];
9224 };
9225
9226 struct mlx5_ifc_alloc_q_counter_in_bits {
9227         u8         opcode[0x10];
9228         u8         uid[0x10];
9229
9230         u8         reserved_at_20[0x10];
9231         u8         op_mod[0x10];
9232
9233         u8         reserved_at_40[0x40];
9234 };
9235
9236 struct mlx5_ifc_alloc_pd_out_bits {
9237         u8         status[0x8];
9238         u8         reserved_at_8[0x18];
9239
9240         u8         syndrome[0x20];
9241
9242         u8         reserved_at_40[0x8];
9243         u8         pd[0x18];
9244
9245         u8         reserved_at_60[0x20];
9246 };
9247
9248 struct mlx5_ifc_alloc_pd_in_bits {
9249         u8         opcode[0x10];
9250         u8         uid[0x10];
9251
9252         u8         reserved_at_20[0x10];
9253         u8         op_mod[0x10];
9254
9255         u8         reserved_at_40[0x40];
9256 };
9257
9258 struct mlx5_ifc_alloc_flow_counter_out_bits {
9259         u8         status[0x8];
9260         u8         reserved_at_8[0x18];
9261
9262         u8         syndrome[0x20];
9263
9264         u8         flow_counter_id[0x20];
9265
9266         u8         reserved_at_60[0x20];
9267 };
9268
9269 struct mlx5_ifc_alloc_flow_counter_in_bits {
9270         u8         opcode[0x10];
9271         u8         reserved_at_10[0x10];
9272
9273         u8         reserved_at_20[0x10];
9274         u8         op_mod[0x10];
9275
9276         u8         reserved_at_40[0x33];
9277         u8         flow_counter_bulk_log_size[0x5];
9278         u8         flow_counter_bulk[0x8];
9279 };
9280
9281 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
9282         u8         status[0x8];
9283         u8         reserved_at_8[0x18];
9284
9285         u8         syndrome[0x20];
9286
9287         u8         reserved_at_40[0x40];
9288 };
9289
9290 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
9291         u8         opcode[0x10];
9292         u8         reserved_at_10[0x10];
9293
9294         u8         reserved_at_20[0x10];
9295         u8         op_mod[0x10];
9296
9297         u8         reserved_at_40[0x20];
9298
9299         u8         reserved_at_60[0x10];
9300         u8         vxlan_udp_port[0x10];
9301 };
9302
9303 struct mlx5_ifc_set_pp_rate_limit_out_bits {
9304         u8         status[0x8];
9305         u8         reserved_at_8[0x18];
9306
9307         u8         syndrome[0x20];
9308
9309         u8         reserved_at_40[0x40];
9310 };
9311
9312 struct mlx5_ifc_set_pp_rate_limit_context_bits {
9313         u8         rate_limit[0x20];
9314
9315         u8         burst_upper_bound[0x20];
9316
9317         u8         reserved_at_40[0x10];
9318         u8         typical_packet_size[0x10];
9319
9320         u8         reserved_at_60[0x120];
9321 };
9322
9323 struct mlx5_ifc_set_pp_rate_limit_in_bits {
9324         u8         opcode[0x10];
9325         u8         uid[0x10];
9326
9327         u8         reserved_at_20[0x10];
9328         u8         op_mod[0x10];
9329
9330         u8         reserved_at_40[0x10];
9331         u8         rate_limit_index[0x10];
9332
9333         u8         reserved_at_60[0x20];
9334
9335         struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
9336 };
9337
9338 struct mlx5_ifc_access_register_out_bits {
9339         u8         status[0x8];
9340         u8         reserved_at_8[0x18];
9341
9342         u8         syndrome[0x20];
9343
9344         u8         reserved_at_40[0x40];
9345
9346         u8         register_data[][0x20];
9347 };
9348
9349 enum {
9350         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
9351         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
9352 };
9353
9354 struct mlx5_ifc_access_register_in_bits {
9355         u8         opcode[0x10];
9356         u8         reserved_at_10[0x10];
9357
9358         u8         reserved_at_20[0x10];
9359         u8         op_mod[0x10];
9360
9361         u8         reserved_at_40[0x10];
9362         u8         register_id[0x10];
9363
9364         u8         argument[0x20];
9365
9366         u8         register_data[][0x20];
9367 };
9368
9369 struct mlx5_ifc_sltp_reg_bits {
9370         u8         status[0x4];
9371         u8         version[0x4];
9372         u8         local_port[0x8];
9373         u8         pnat[0x2];
9374         u8         reserved_at_12[0x2];
9375         u8         lane[0x4];
9376         u8         reserved_at_18[0x8];
9377
9378         u8         reserved_at_20[0x20];
9379
9380         u8         reserved_at_40[0x7];
9381         u8         polarity[0x1];
9382         u8         ob_tap0[0x8];
9383         u8         ob_tap1[0x8];
9384         u8         ob_tap2[0x8];
9385
9386         u8         reserved_at_60[0xc];
9387         u8         ob_preemp_mode[0x4];
9388         u8         ob_reg[0x8];
9389         u8         ob_bias[0x8];
9390
9391         u8         reserved_at_80[0x20];
9392 };
9393
9394 struct mlx5_ifc_slrg_reg_bits {
9395         u8         status[0x4];
9396         u8         version[0x4];
9397         u8         local_port[0x8];
9398         u8         pnat[0x2];
9399         u8         reserved_at_12[0x2];
9400         u8         lane[0x4];
9401         u8         reserved_at_18[0x8];
9402
9403         u8         time_to_link_up[0x10];
9404         u8         reserved_at_30[0xc];
9405         u8         grade_lane_speed[0x4];
9406
9407         u8         grade_version[0x8];
9408         u8         grade[0x18];
9409
9410         u8         reserved_at_60[0x4];
9411         u8         height_grade_type[0x4];
9412         u8         height_grade[0x18];
9413
9414         u8         height_dz[0x10];
9415         u8         height_dv[0x10];
9416
9417         u8         reserved_at_a0[0x10];
9418         u8         height_sigma[0x10];
9419
9420         u8         reserved_at_c0[0x20];
9421
9422         u8         reserved_at_e0[0x4];
9423         u8         phase_grade_type[0x4];
9424         u8         phase_grade[0x18];
9425
9426         u8         reserved_at_100[0x8];
9427         u8         phase_eo_pos[0x8];
9428         u8         reserved_at_110[0x8];
9429         u8         phase_eo_neg[0x8];
9430
9431         u8         ffe_set_tested[0x10];
9432         u8         test_errors_per_lane[0x10];
9433 };
9434
9435 struct mlx5_ifc_pvlc_reg_bits {
9436         u8         reserved_at_0[0x8];
9437         u8         local_port[0x8];
9438         u8         reserved_at_10[0x10];
9439
9440         u8         reserved_at_20[0x1c];
9441         u8         vl_hw_cap[0x4];
9442
9443         u8         reserved_at_40[0x1c];
9444         u8         vl_admin[0x4];
9445
9446         u8         reserved_at_60[0x1c];
9447         u8         vl_operational[0x4];
9448 };
9449
9450 struct mlx5_ifc_pude_reg_bits {
9451         u8         swid[0x8];
9452         u8         local_port[0x8];
9453         u8         reserved_at_10[0x4];
9454         u8         admin_status[0x4];
9455         u8         reserved_at_18[0x4];
9456         u8         oper_status[0x4];
9457
9458         u8         reserved_at_20[0x60];
9459 };
9460
9461 struct mlx5_ifc_ptys_reg_bits {
9462         u8         reserved_at_0[0x1];
9463         u8         an_disable_admin[0x1];
9464         u8         an_disable_cap[0x1];
9465         u8         reserved_at_3[0x5];
9466         u8         local_port[0x8];
9467         u8         reserved_at_10[0xd];
9468         u8         proto_mask[0x3];
9469
9470         u8         an_status[0x4];
9471         u8         reserved_at_24[0xc];
9472         u8         data_rate_oper[0x10];
9473
9474         u8         ext_eth_proto_capability[0x20];
9475
9476         u8         eth_proto_capability[0x20];
9477
9478         u8         ib_link_width_capability[0x10];
9479         u8         ib_proto_capability[0x10];
9480
9481         u8         ext_eth_proto_admin[0x20];
9482
9483         u8         eth_proto_admin[0x20];
9484
9485         u8         ib_link_width_admin[0x10];
9486         u8         ib_proto_admin[0x10];
9487
9488         u8         ext_eth_proto_oper[0x20];
9489
9490         u8         eth_proto_oper[0x20];
9491
9492         u8         ib_link_width_oper[0x10];
9493         u8         ib_proto_oper[0x10];
9494
9495         u8         reserved_at_160[0x1c];
9496         u8         connector_type[0x4];
9497
9498         u8         eth_proto_lp_advertise[0x20];
9499
9500         u8         reserved_at_1a0[0x60];
9501 };
9502
9503 struct mlx5_ifc_mlcr_reg_bits {
9504         u8         reserved_at_0[0x8];
9505         u8         local_port[0x8];
9506         u8         reserved_at_10[0x20];
9507
9508         u8         beacon_duration[0x10];
9509         u8         reserved_at_40[0x10];
9510
9511         u8         beacon_remain[0x10];
9512 };
9513
9514 struct mlx5_ifc_ptas_reg_bits {
9515         u8         reserved_at_0[0x20];
9516
9517         u8         algorithm_options[0x10];
9518         u8         reserved_at_30[0x4];
9519         u8         repetitions_mode[0x4];
9520         u8         num_of_repetitions[0x8];
9521
9522         u8         grade_version[0x8];
9523         u8         height_grade_type[0x4];
9524         u8         phase_grade_type[0x4];
9525         u8         height_grade_weight[0x8];
9526         u8         phase_grade_weight[0x8];
9527
9528         u8         gisim_measure_bits[0x10];
9529         u8         adaptive_tap_measure_bits[0x10];
9530
9531         u8         ber_bath_high_error_threshold[0x10];
9532         u8         ber_bath_mid_error_threshold[0x10];
9533
9534         u8         ber_bath_low_error_threshold[0x10];
9535         u8         one_ratio_high_threshold[0x10];
9536
9537         u8         one_ratio_high_mid_threshold[0x10];
9538         u8         one_ratio_low_mid_threshold[0x10];
9539
9540         u8         one_ratio_low_threshold[0x10];
9541         u8         ndeo_error_threshold[0x10];
9542
9543         u8         mixer_offset_step_size[0x10];
9544         u8         reserved_at_110[0x8];
9545         u8         mix90_phase_for_voltage_bath[0x8];
9546
9547         u8         mixer_offset_start[0x10];
9548         u8         mixer_offset_end[0x10];
9549
9550         u8         reserved_at_140[0x15];
9551         u8         ber_test_time[0xb];
9552 };
9553
9554 struct mlx5_ifc_pspa_reg_bits {
9555         u8         swid[0x8];
9556         u8         local_port[0x8];
9557         u8         sub_port[0x8];
9558         u8         reserved_at_18[0x8];
9559
9560         u8         reserved_at_20[0x20];
9561 };
9562
9563 struct mlx5_ifc_pqdr_reg_bits {
9564         u8         reserved_at_0[0x8];
9565         u8         local_port[0x8];
9566         u8         reserved_at_10[0x5];
9567         u8         prio[0x3];
9568         u8         reserved_at_18[0x6];
9569         u8         mode[0x2];
9570
9571         u8         reserved_at_20[0x20];
9572
9573         u8         reserved_at_40[0x10];
9574         u8         min_threshold[0x10];
9575
9576         u8         reserved_at_60[0x10];
9577         u8         max_threshold[0x10];
9578
9579         u8         reserved_at_80[0x10];
9580         u8         mark_probability_denominator[0x10];
9581
9582         u8         reserved_at_a0[0x60];
9583 };
9584
9585 struct mlx5_ifc_ppsc_reg_bits {
9586         u8         reserved_at_0[0x8];
9587         u8         local_port[0x8];
9588         u8         reserved_at_10[0x10];
9589
9590         u8         reserved_at_20[0x60];
9591
9592         u8         reserved_at_80[0x1c];
9593         u8         wrps_admin[0x4];
9594
9595         u8         reserved_at_a0[0x1c];
9596         u8         wrps_status[0x4];
9597
9598         u8         reserved_at_c0[0x8];
9599         u8         up_threshold[0x8];
9600         u8         reserved_at_d0[0x8];
9601         u8         down_threshold[0x8];
9602
9603         u8         reserved_at_e0[0x20];
9604
9605         u8         reserved_at_100[0x1c];
9606         u8         srps_admin[0x4];
9607
9608         u8         reserved_at_120[0x1c];
9609         u8         srps_status[0x4];
9610
9611         u8         reserved_at_140[0x40];
9612 };
9613
9614 struct mlx5_ifc_pplr_reg_bits {
9615         u8         reserved_at_0[0x8];
9616         u8         local_port[0x8];
9617         u8         reserved_at_10[0x10];
9618
9619         u8         reserved_at_20[0x8];
9620         u8         lb_cap[0x8];
9621         u8         reserved_at_30[0x8];
9622         u8         lb_en[0x8];
9623 };
9624
9625 struct mlx5_ifc_pplm_reg_bits {
9626         u8         reserved_at_0[0x8];
9627         u8         local_port[0x8];
9628         u8         reserved_at_10[0x10];
9629
9630         u8         reserved_at_20[0x20];
9631
9632         u8         port_profile_mode[0x8];
9633         u8         static_port_profile[0x8];
9634         u8         active_port_profile[0x8];
9635         u8         reserved_at_58[0x8];
9636
9637         u8         retransmission_active[0x8];
9638         u8         fec_mode_active[0x18];
9639
9640         u8         rs_fec_correction_bypass_cap[0x4];
9641         u8         reserved_at_84[0x8];
9642         u8         fec_override_cap_56g[0x4];
9643         u8         fec_override_cap_100g[0x4];
9644         u8         fec_override_cap_50g[0x4];
9645         u8         fec_override_cap_25g[0x4];
9646         u8         fec_override_cap_10g_40g[0x4];
9647
9648         u8         rs_fec_correction_bypass_admin[0x4];
9649         u8         reserved_at_a4[0x8];
9650         u8         fec_override_admin_56g[0x4];
9651         u8         fec_override_admin_100g[0x4];
9652         u8         fec_override_admin_50g[0x4];
9653         u8         fec_override_admin_25g[0x4];
9654         u8         fec_override_admin_10g_40g[0x4];
9655
9656         u8         fec_override_cap_400g_8x[0x10];
9657         u8         fec_override_cap_200g_4x[0x10];
9658
9659         u8         fec_override_cap_100g_2x[0x10];
9660         u8         fec_override_cap_50g_1x[0x10];
9661
9662         u8         fec_override_admin_400g_8x[0x10];
9663         u8         fec_override_admin_200g_4x[0x10];
9664
9665         u8         fec_override_admin_100g_2x[0x10];
9666         u8         fec_override_admin_50g_1x[0x10];
9667
9668         u8         reserved_at_140[0x140];
9669 };
9670
9671 struct mlx5_ifc_ppcnt_reg_bits {
9672         u8         swid[0x8];
9673         u8         local_port[0x8];
9674         u8         pnat[0x2];
9675         u8         reserved_at_12[0x8];
9676         u8         grp[0x6];
9677
9678         u8         clr[0x1];
9679         u8         reserved_at_21[0x1c];
9680         u8         prio_tc[0x3];
9681
9682         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9683 };
9684
9685 struct mlx5_ifc_mpein_reg_bits {
9686         u8         reserved_at_0[0x2];
9687         u8         depth[0x6];
9688         u8         pcie_index[0x8];
9689         u8         node[0x8];
9690         u8         reserved_at_18[0x8];
9691
9692         u8         capability_mask[0x20];
9693
9694         u8         reserved_at_40[0x8];
9695         u8         link_width_enabled[0x8];
9696         u8         link_speed_enabled[0x10];
9697
9698         u8         lane0_physical_position[0x8];
9699         u8         link_width_active[0x8];
9700         u8         link_speed_active[0x10];
9701
9702         u8         num_of_pfs[0x10];
9703         u8         num_of_vfs[0x10];
9704
9705         u8         bdf0[0x10];
9706         u8         reserved_at_b0[0x10];
9707
9708         u8         max_read_request_size[0x4];
9709         u8         max_payload_size[0x4];
9710         u8         reserved_at_c8[0x5];
9711         u8         pwr_status[0x3];
9712         u8         port_type[0x4];
9713         u8         reserved_at_d4[0xb];
9714         u8         lane_reversal[0x1];
9715
9716         u8         reserved_at_e0[0x14];
9717         u8         pci_power[0xc];
9718
9719         u8         reserved_at_100[0x20];
9720
9721         u8         device_status[0x10];
9722         u8         port_state[0x8];
9723         u8         reserved_at_138[0x8];
9724
9725         u8         reserved_at_140[0x10];
9726         u8         receiver_detect_result[0x10];
9727
9728         u8         reserved_at_160[0x20];
9729 };
9730
9731 struct mlx5_ifc_mpcnt_reg_bits {
9732         u8         reserved_at_0[0x8];
9733         u8         pcie_index[0x8];
9734         u8         reserved_at_10[0xa];
9735         u8         grp[0x6];
9736
9737         u8         clr[0x1];
9738         u8         reserved_at_21[0x1f];
9739
9740         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
9741 };
9742
9743 struct mlx5_ifc_ppad_reg_bits {
9744         u8         reserved_at_0[0x3];
9745         u8         single_mac[0x1];
9746         u8         reserved_at_4[0x4];
9747         u8         local_port[0x8];
9748         u8         mac_47_32[0x10];
9749
9750         u8         mac_31_0[0x20];
9751
9752         u8         reserved_at_40[0x40];
9753 };
9754
9755 struct mlx5_ifc_pmtu_reg_bits {
9756         u8         reserved_at_0[0x8];
9757         u8         local_port[0x8];
9758         u8         reserved_at_10[0x10];
9759
9760         u8         max_mtu[0x10];
9761         u8         reserved_at_30[0x10];
9762
9763         u8         admin_mtu[0x10];
9764         u8         reserved_at_50[0x10];
9765
9766         u8         oper_mtu[0x10];
9767         u8         reserved_at_70[0x10];
9768 };
9769
9770 struct mlx5_ifc_pmpr_reg_bits {
9771         u8         reserved_at_0[0x8];
9772         u8         module[0x8];
9773         u8         reserved_at_10[0x10];
9774
9775         u8         reserved_at_20[0x18];
9776         u8         attenuation_5g[0x8];
9777
9778         u8         reserved_at_40[0x18];
9779         u8         attenuation_7g[0x8];
9780
9781         u8         reserved_at_60[0x18];
9782         u8         attenuation_12g[0x8];
9783 };
9784
9785 struct mlx5_ifc_pmpe_reg_bits {
9786         u8         reserved_at_0[0x8];
9787         u8         module[0x8];
9788         u8         reserved_at_10[0xc];
9789         u8         module_status[0x4];
9790
9791         u8         reserved_at_20[0x60];
9792 };
9793
9794 struct mlx5_ifc_pmpc_reg_bits {
9795         u8         module_state_updated[32][0x8];
9796 };
9797
9798 struct mlx5_ifc_pmlpn_reg_bits {
9799         u8         reserved_at_0[0x4];
9800         u8         mlpn_status[0x4];
9801         u8         local_port[0x8];
9802         u8         reserved_at_10[0x10];
9803
9804         u8         e[0x1];
9805         u8         reserved_at_21[0x1f];
9806 };
9807
9808 struct mlx5_ifc_pmlp_reg_bits {
9809         u8         rxtx[0x1];
9810         u8         reserved_at_1[0x7];
9811         u8         local_port[0x8];
9812         u8         reserved_at_10[0x8];
9813         u8         width[0x8];
9814
9815         u8         lane0_module_mapping[0x20];
9816
9817         u8         lane1_module_mapping[0x20];
9818
9819         u8         lane2_module_mapping[0x20];
9820
9821         u8         lane3_module_mapping[0x20];
9822
9823         u8         reserved_at_a0[0x160];
9824 };
9825
9826 struct mlx5_ifc_pmaos_reg_bits {
9827         u8         reserved_at_0[0x8];
9828         u8         module[0x8];
9829         u8         reserved_at_10[0x4];
9830         u8         admin_status[0x4];
9831         u8         reserved_at_18[0x4];
9832         u8         oper_status[0x4];
9833
9834         u8         ase[0x1];
9835         u8         ee[0x1];
9836         u8         reserved_at_22[0x1c];
9837         u8         e[0x2];
9838
9839         u8         reserved_at_40[0x40];
9840 };
9841
9842 struct mlx5_ifc_plpc_reg_bits {
9843         u8         reserved_at_0[0x4];
9844         u8         profile_id[0xc];
9845         u8         reserved_at_10[0x4];
9846         u8         proto_mask[0x4];
9847         u8         reserved_at_18[0x8];
9848
9849         u8         reserved_at_20[0x10];
9850         u8         lane_speed[0x10];
9851
9852         u8         reserved_at_40[0x17];
9853         u8         lpbf[0x1];
9854         u8         fec_mode_policy[0x8];
9855
9856         u8         retransmission_capability[0x8];
9857         u8         fec_mode_capability[0x18];
9858
9859         u8         retransmission_support_admin[0x8];
9860         u8         fec_mode_support_admin[0x18];
9861
9862         u8         retransmission_request_admin[0x8];
9863         u8         fec_mode_request_admin[0x18];
9864
9865         u8         reserved_at_c0[0x80];
9866 };
9867
9868 struct mlx5_ifc_plib_reg_bits {
9869         u8         reserved_at_0[0x8];
9870         u8         local_port[0x8];
9871         u8         reserved_at_10[0x8];
9872         u8         ib_port[0x8];
9873
9874         u8         reserved_at_20[0x60];
9875 };
9876
9877 struct mlx5_ifc_plbf_reg_bits {
9878         u8         reserved_at_0[0x8];
9879         u8         local_port[0x8];
9880         u8         reserved_at_10[0xd];
9881         u8         lbf_mode[0x3];
9882
9883         u8         reserved_at_20[0x20];
9884 };
9885
9886 struct mlx5_ifc_pipg_reg_bits {
9887         u8         reserved_at_0[0x8];
9888         u8         local_port[0x8];
9889         u8         reserved_at_10[0x10];
9890
9891         u8         dic[0x1];
9892         u8         reserved_at_21[0x19];
9893         u8         ipg[0x4];
9894         u8         reserved_at_3e[0x2];
9895 };
9896
9897 struct mlx5_ifc_pifr_reg_bits {
9898         u8         reserved_at_0[0x8];
9899         u8         local_port[0x8];
9900         u8         reserved_at_10[0x10];
9901
9902         u8         reserved_at_20[0xe0];
9903
9904         u8         port_filter[8][0x20];
9905
9906         u8         port_filter_update_en[8][0x20];
9907 };
9908
9909 struct mlx5_ifc_pfcc_reg_bits {
9910         u8         reserved_at_0[0x8];
9911         u8         local_port[0x8];
9912         u8         reserved_at_10[0xb];
9913         u8         ppan_mask_n[0x1];
9914         u8         minor_stall_mask[0x1];
9915         u8         critical_stall_mask[0x1];
9916         u8         reserved_at_1e[0x2];
9917
9918         u8         ppan[0x4];
9919         u8         reserved_at_24[0x4];
9920         u8         prio_mask_tx[0x8];
9921         u8         reserved_at_30[0x8];
9922         u8         prio_mask_rx[0x8];
9923
9924         u8         pptx[0x1];
9925         u8         aptx[0x1];
9926         u8         pptx_mask_n[0x1];
9927         u8         reserved_at_43[0x5];
9928         u8         pfctx[0x8];
9929         u8         reserved_at_50[0x10];
9930
9931         u8         pprx[0x1];
9932         u8         aprx[0x1];
9933         u8         pprx_mask_n[0x1];
9934         u8         reserved_at_63[0x5];
9935         u8         pfcrx[0x8];
9936         u8         reserved_at_70[0x10];
9937
9938         u8         device_stall_minor_watermark[0x10];
9939         u8         device_stall_critical_watermark[0x10];
9940
9941         u8         reserved_at_a0[0x60];
9942 };
9943
9944 struct mlx5_ifc_pelc_reg_bits {
9945         u8         op[0x4];
9946         u8         reserved_at_4[0x4];
9947         u8         local_port[0x8];
9948         u8         reserved_at_10[0x10];
9949
9950         u8         op_admin[0x8];
9951         u8         op_capability[0x8];
9952         u8         op_request[0x8];
9953         u8         op_active[0x8];
9954
9955         u8         admin[0x40];
9956
9957         u8         capability[0x40];
9958
9959         u8         request[0x40];
9960
9961         u8         active[0x40];
9962
9963         u8         reserved_at_140[0x80];
9964 };
9965
9966 struct mlx5_ifc_peir_reg_bits {
9967         u8         reserved_at_0[0x8];
9968         u8         local_port[0x8];
9969         u8         reserved_at_10[0x10];
9970
9971         u8         reserved_at_20[0xc];
9972         u8         error_count[0x4];
9973         u8         reserved_at_30[0x10];
9974
9975         u8         reserved_at_40[0xc];
9976         u8         lane[0x4];
9977         u8         reserved_at_50[0x8];
9978         u8         error_type[0x8];
9979 };
9980
9981 struct mlx5_ifc_mpegc_reg_bits {
9982         u8         reserved_at_0[0x30];
9983         u8         field_select[0x10];
9984
9985         u8         tx_overflow_sense[0x1];
9986         u8         mark_cqe[0x1];
9987         u8         mark_cnp[0x1];
9988         u8         reserved_at_43[0x1b];
9989         u8         tx_lossy_overflow_oper[0x2];
9990
9991         u8         reserved_at_60[0x100];
9992 };
9993
9994 enum {
9995         MLX5_MTUTC_FREQ_ADJ_UNITS_PPB          = 0x0,
9996         MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM   = 0x1,
9997 };
9998
9999 enum {
10000         MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,
10001         MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,
10002         MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,
10003 };
10004
10005 struct mlx5_ifc_mtutc_reg_bits {
10006         u8         reserved_at_0[0x5];
10007         u8         freq_adj_units[0x3];
10008         u8         reserved_at_8[0x14];
10009         u8         operation[0x4];
10010
10011         u8         freq_adjustment[0x20];
10012
10013         u8         reserved_at_40[0x40];
10014
10015         u8         utc_sec[0x20];
10016
10017         u8         reserved_at_a0[0x2];
10018         u8         utc_nsec[0x1e];
10019
10020         u8         time_adjustment[0x20];
10021 };
10022
10023 struct mlx5_ifc_pcam_enhanced_features_bits {
10024         u8         reserved_at_0[0x68];
10025         u8         fec_50G_per_lane_in_pplm[0x1];
10026         u8         reserved_at_69[0x4];
10027         u8         rx_icrc_encapsulated_counter[0x1];
10028         u8         reserved_at_6e[0x4];
10029         u8         ptys_extended_ethernet[0x1];
10030         u8         reserved_at_73[0x3];
10031         u8         pfcc_mask[0x1];
10032         u8         reserved_at_77[0x3];
10033         u8         per_lane_error_counters[0x1];
10034         u8         rx_buffer_fullness_counters[0x1];
10035         u8         ptys_connector_type[0x1];
10036         u8         reserved_at_7d[0x1];
10037         u8         ppcnt_discard_group[0x1];
10038         u8         ppcnt_statistical_group[0x1];
10039 };
10040
10041 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
10042         u8         port_access_reg_cap_mask_127_to_96[0x20];
10043         u8         port_access_reg_cap_mask_95_to_64[0x20];
10044
10045         u8         port_access_reg_cap_mask_63_to_36[0x1c];
10046         u8         pplm[0x1];
10047         u8         port_access_reg_cap_mask_34_to_32[0x3];
10048
10049         u8         port_access_reg_cap_mask_31_to_13[0x13];
10050         u8         pbmc[0x1];
10051         u8         pptb[0x1];
10052         u8         port_access_reg_cap_mask_10_to_09[0x2];
10053         u8         ppcnt[0x1];
10054         u8         port_access_reg_cap_mask_07_to_00[0x8];
10055 };
10056
10057 struct mlx5_ifc_pcam_reg_bits {
10058         u8         reserved_at_0[0x8];
10059         u8         feature_group[0x8];
10060         u8         reserved_at_10[0x8];
10061         u8         access_reg_group[0x8];
10062
10063         u8         reserved_at_20[0x20];
10064
10065         union {
10066                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
10067                 u8         reserved_at_0[0x80];
10068         } port_access_reg_cap_mask;
10069
10070         u8         reserved_at_c0[0x80];
10071
10072         union {
10073                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
10074                 u8         reserved_at_0[0x80];
10075         } feature_cap_mask;
10076
10077         u8         reserved_at_1c0[0xc0];
10078 };
10079
10080 struct mlx5_ifc_mcam_enhanced_features_bits {
10081         u8         reserved_at_0[0x50];
10082         u8         mtutc_freq_adj_units[0x1];
10083         u8         mtutc_time_adjustment_extended_range[0x1];
10084         u8         reserved_at_52[0xb];
10085         u8         mcia_32dwords[0x1];
10086         u8         out_pulse_duration_ns[0x1];
10087         u8         npps_period[0x1];
10088         u8         reserved_at_60[0xa];
10089         u8         reset_state[0x1];
10090         u8         ptpcyc2realtime_modify[0x1];
10091         u8         reserved_at_6c[0x2];
10092         u8         pci_status_and_power[0x1];
10093         u8         reserved_at_6f[0x5];
10094         u8         mark_tx_action_cnp[0x1];
10095         u8         mark_tx_action_cqe[0x1];
10096         u8         dynamic_tx_overflow[0x1];
10097         u8         reserved_at_77[0x4];
10098         u8         pcie_outbound_stalled[0x1];
10099         u8         tx_overflow_buffer_pkt[0x1];
10100         u8         mtpps_enh_out_per_adj[0x1];
10101         u8         mtpps_fs[0x1];
10102         u8         pcie_performance_group[0x1];
10103 };
10104
10105 struct mlx5_ifc_mcam_access_reg_bits {
10106         u8         reserved_at_0[0x1c];
10107         u8         mcda[0x1];
10108         u8         mcc[0x1];
10109         u8         mcqi[0x1];
10110         u8         mcqs[0x1];
10111
10112         u8         regs_95_to_87[0x9];
10113         u8         mpegc[0x1];
10114         u8         mtutc[0x1];
10115         u8         regs_84_to_68[0x11];
10116         u8         tracer_registers[0x4];
10117
10118         u8         regs_63_to_46[0x12];
10119         u8         mrtc[0x1];
10120         u8         regs_44_to_32[0xd];
10121
10122         u8         regs_31_to_0[0x20];
10123 };
10124
10125 struct mlx5_ifc_mcam_access_reg_bits1 {
10126         u8         regs_127_to_96[0x20];
10127
10128         u8         regs_95_to_64[0x20];
10129
10130         u8         regs_63_to_32[0x20];
10131
10132         u8         regs_31_to_0[0x20];
10133 };
10134
10135 struct mlx5_ifc_mcam_access_reg_bits2 {
10136         u8         regs_127_to_99[0x1d];
10137         u8         mirc[0x1];
10138         u8         regs_97_to_96[0x2];
10139
10140         u8         regs_95_to_64[0x20];
10141
10142         u8         regs_63_to_32[0x20];
10143
10144         u8         regs_31_to_0[0x20];
10145 };
10146
10147 struct mlx5_ifc_mcam_reg_bits {
10148         u8         reserved_at_0[0x8];
10149         u8         feature_group[0x8];
10150         u8         reserved_at_10[0x8];
10151         u8         access_reg_group[0x8];
10152
10153         u8         reserved_at_20[0x20];
10154
10155         union {
10156                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
10157                 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
10158                 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
10159                 u8         reserved_at_0[0x80];
10160         } mng_access_reg_cap_mask;
10161
10162         u8         reserved_at_c0[0x80];
10163
10164         union {
10165                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
10166                 u8         reserved_at_0[0x80];
10167         } mng_feature_cap_mask;
10168
10169         u8         reserved_at_1c0[0x80];
10170 };
10171
10172 struct mlx5_ifc_qcam_access_reg_cap_mask {
10173         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
10174         u8         qpdpm[0x1];
10175         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
10176         u8         qdpm[0x1];
10177         u8         qpts[0x1];
10178         u8         qcap[0x1];
10179         u8         qcam_access_reg_cap_mask_0[0x1];
10180 };
10181
10182 struct mlx5_ifc_qcam_qos_feature_cap_mask {
10183         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
10184         u8         qpts_trust_both[0x1];
10185 };
10186
10187 struct mlx5_ifc_qcam_reg_bits {
10188         u8         reserved_at_0[0x8];
10189         u8         feature_group[0x8];
10190         u8         reserved_at_10[0x8];
10191         u8         access_reg_group[0x8];
10192         u8         reserved_at_20[0x20];
10193
10194         union {
10195                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
10196                 u8  reserved_at_0[0x80];
10197         } qos_access_reg_cap_mask;
10198
10199         u8         reserved_at_c0[0x80];
10200
10201         union {
10202                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
10203                 u8  reserved_at_0[0x80];
10204         } qos_feature_cap_mask;
10205
10206         u8         reserved_at_1c0[0x80];
10207 };
10208
10209 struct mlx5_ifc_core_dump_reg_bits {
10210         u8         reserved_at_0[0x18];
10211         u8         core_dump_type[0x8];
10212
10213         u8         reserved_at_20[0x30];
10214         u8         vhca_id[0x10];
10215
10216         u8         reserved_at_60[0x8];
10217         u8         qpn[0x18];
10218         u8         reserved_at_80[0x180];
10219 };
10220
10221 struct mlx5_ifc_pcap_reg_bits {
10222         u8         reserved_at_0[0x8];
10223         u8         local_port[0x8];
10224         u8         reserved_at_10[0x10];
10225
10226         u8         port_capability_mask[4][0x20];
10227 };
10228
10229 struct mlx5_ifc_paos_reg_bits {
10230         u8         swid[0x8];
10231         u8         local_port[0x8];
10232         u8         reserved_at_10[0x4];
10233         u8         admin_status[0x4];
10234         u8         reserved_at_18[0x4];
10235         u8         oper_status[0x4];
10236
10237         u8         ase[0x1];
10238         u8         ee[0x1];
10239         u8         reserved_at_22[0x1c];
10240         u8         e[0x2];
10241
10242         u8         reserved_at_40[0x40];
10243 };
10244
10245 struct mlx5_ifc_pamp_reg_bits {
10246         u8         reserved_at_0[0x8];
10247         u8         opamp_group[0x8];
10248         u8         reserved_at_10[0xc];
10249         u8         opamp_group_type[0x4];
10250
10251         u8         start_index[0x10];
10252         u8         reserved_at_30[0x4];
10253         u8         num_of_indices[0xc];
10254
10255         u8         index_data[18][0x10];
10256 };
10257
10258 struct mlx5_ifc_pcmr_reg_bits {
10259         u8         reserved_at_0[0x8];
10260         u8         local_port[0x8];
10261         u8         reserved_at_10[0x10];
10262
10263         u8         entropy_force_cap[0x1];
10264         u8         entropy_calc_cap[0x1];
10265         u8         entropy_gre_calc_cap[0x1];
10266         u8         reserved_at_23[0xf];
10267         u8         rx_ts_over_crc_cap[0x1];
10268         u8         reserved_at_33[0xb];
10269         u8         fcs_cap[0x1];
10270         u8         reserved_at_3f[0x1];
10271
10272         u8         entropy_force[0x1];
10273         u8         entropy_calc[0x1];
10274         u8         entropy_gre_calc[0x1];
10275         u8         reserved_at_43[0xf];
10276         u8         rx_ts_over_crc[0x1];
10277         u8         reserved_at_53[0xb];
10278         u8         fcs_chk[0x1];
10279         u8         reserved_at_5f[0x1];
10280 };
10281
10282 struct mlx5_ifc_lane_2_module_mapping_bits {
10283         u8         reserved_at_0[0x4];
10284         u8         rx_lane[0x4];
10285         u8         reserved_at_8[0x4];
10286         u8         tx_lane[0x4];
10287         u8         reserved_at_10[0x8];
10288         u8         module[0x8];
10289 };
10290
10291 struct mlx5_ifc_bufferx_reg_bits {
10292         u8         reserved_at_0[0x6];
10293         u8         lossy[0x1];
10294         u8         epsb[0x1];
10295         u8         reserved_at_8[0x8];
10296         u8         size[0x10];
10297
10298         u8         xoff_threshold[0x10];
10299         u8         xon_threshold[0x10];
10300 };
10301
10302 struct mlx5_ifc_set_node_in_bits {
10303         u8         node_description[64][0x8];
10304 };
10305
10306 struct mlx5_ifc_register_power_settings_bits {
10307         u8         reserved_at_0[0x18];
10308         u8         power_settings_level[0x8];
10309
10310         u8         reserved_at_20[0x60];
10311 };
10312
10313 struct mlx5_ifc_register_host_endianness_bits {
10314         u8         he[0x1];
10315         u8         reserved_at_1[0x1f];
10316
10317         u8         reserved_at_20[0x60];
10318 };
10319
10320 struct mlx5_ifc_umr_pointer_desc_argument_bits {
10321         u8         reserved_at_0[0x20];
10322
10323         u8         mkey[0x20];
10324
10325         u8         addressh_63_32[0x20];
10326
10327         u8         addressl_31_0[0x20];
10328 };
10329
10330 struct mlx5_ifc_ud_adrs_vector_bits {
10331         u8         dc_key[0x40];
10332
10333         u8         ext[0x1];
10334         u8         reserved_at_41[0x7];
10335         u8         destination_qp_dct[0x18];
10336
10337         u8         static_rate[0x4];
10338         u8         sl_eth_prio[0x4];
10339         u8         fl[0x1];
10340         u8         mlid[0x7];
10341         u8         rlid_udp_sport[0x10];
10342
10343         u8         reserved_at_80[0x20];
10344
10345         u8         rmac_47_16[0x20];
10346
10347         u8         rmac_15_0[0x10];
10348         u8         tclass[0x8];
10349         u8         hop_limit[0x8];
10350
10351         u8         reserved_at_e0[0x1];
10352         u8         grh[0x1];
10353         u8         reserved_at_e2[0x2];
10354         u8         src_addr_index[0x8];
10355         u8         flow_label[0x14];
10356
10357         u8         rgid_rip[16][0x8];
10358 };
10359
10360 struct mlx5_ifc_pages_req_event_bits {
10361         u8         reserved_at_0[0x10];
10362         u8         function_id[0x10];
10363
10364         u8         num_pages[0x20];
10365
10366         u8         reserved_at_40[0xa0];
10367 };
10368
10369 struct mlx5_ifc_eqe_bits {
10370         u8         reserved_at_0[0x8];
10371         u8         event_type[0x8];
10372         u8         reserved_at_10[0x8];
10373         u8         event_sub_type[0x8];
10374
10375         u8         reserved_at_20[0xe0];
10376
10377         union mlx5_ifc_event_auto_bits event_data;
10378
10379         u8         reserved_at_1e0[0x10];
10380         u8         signature[0x8];
10381         u8         reserved_at_1f8[0x7];
10382         u8         owner[0x1];
10383 };
10384
10385 enum {
10386         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
10387 };
10388
10389 struct mlx5_ifc_cmd_queue_entry_bits {
10390         u8         type[0x8];
10391         u8         reserved_at_8[0x18];
10392
10393         u8         input_length[0x20];
10394
10395         u8         input_mailbox_pointer_63_32[0x20];
10396
10397         u8         input_mailbox_pointer_31_9[0x17];
10398         u8         reserved_at_77[0x9];
10399
10400         u8         command_input_inline_data[16][0x8];
10401
10402         u8         command_output_inline_data[16][0x8];
10403
10404         u8         output_mailbox_pointer_63_32[0x20];
10405
10406         u8         output_mailbox_pointer_31_9[0x17];
10407         u8         reserved_at_1b7[0x9];
10408
10409         u8         output_length[0x20];
10410
10411         u8         token[0x8];
10412         u8         signature[0x8];
10413         u8         reserved_at_1f0[0x8];
10414         u8         status[0x7];
10415         u8         ownership[0x1];
10416 };
10417
10418 struct mlx5_ifc_cmd_out_bits {
10419         u8         status[0x8];
10420         u8         reserved_at_8[0x18];
10421
10422         u8         syndrome[0x20];
10423
10424         u8         command_output[0x20];
10425 };
10426
10427 struct mlx5_ifc_cmd_in_bits {
10428         u8         opcode[0x10];
10429         u8         reserved_at_10[0x10];
10430
10431         u8         reserved_at_20[0x10];
10432         u8         op_mod[0x10];
10433
10434         u8         command[][0x20];
10435 };
10436
10437 struct mlx5_ifc_cmd_if_box_bits {
10438         u8         mailbox_data[512][0x8];
10439
10440         u8         reserved_at_1000[0x180];
10441
10442         u8         next_pointer_63_32[0x20];
10443
10444         u8         next_pointer_31_10[0x16];
10445         u8         reserved_at_11b6[0xa];
10446
10447         u8         block_number[0x20];
10448
10449         u8         reserved_at_11e0[0x8];
10450         u8         token[0x8];
10451         u8         ctrl_signature[0x8];
10452         u8         signature[0x8];
10453 };
10454
10455 struct mlx5_ifc_mtt_bits {
10456         u8         ptag_63_32[0x20];
10457
10458         u8         ptag_31_8[0x18];
10459         u8         reserved_at_38[0x6];
10460         u8         wr_en[0x1];
10461         u8         rd_en[0x1];
10462 };
10463
10464 struct mlx5_ifc_query_wol_rol_out_bits {
10465         u8         status[0x8];
10466         u8         reserved_at_8[0x18];
10467
10468         u8         syndrome[0x20];
10469
10470         u8         reserved_at_40[0x10];
10471         u8         rol_mode[0x8];
10472         u8         wol_mode[0x8];
10473
10474         u8         reserved_at_60[0x20];
10475 };
10476
10477 struct mlx5_ifc_query_wol_rol_in_bits {
10478         u8         opcode[0x10];
10479         u8         reserved_at_10[0x10];
10480
10481         u8         reserved_at_20[0x10];
10482         u8         op_mod[0x10];
10483
10484         u8         reserved_at_40[0x40];
10485 };
10486
10487 struct mlx5_ifc_set_wol_rol_out_bits {
10488         u8         status[0x8];
10489         u8         reserved_at_8[0x18];
10490
10491         u8         syndrome[0x20];
10492
10493         u8         reserved_at_40[0x40];
10494 };
10495
10496 struct mlx5_ifc_set_wol_rol_in_bits {
10497         u8         opcode[0x10];
10498         u8         reserved_at_10[0x10];
10499
10500         u8         reserved_at_20[0x10];
10501         u8         op_mod[0x10];
10502
10503         u8         rol_mode_valid[0x1];
10504         u8         wol_mode_valid[0x1];
10505         u8         reserved_at_42[0xe];
10506         u8         rol_mode[0x8];
10507         u8         wol_mode[0x8];
10508
10509         u8         reserved_at_60[0x20];
10510 };
10511
10512 enum {
10513         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
10514         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
10515         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
10516 };
10517
10518 enum {
10519         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
10520         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
10521         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
10522 };
10523
10524 enum {
10525         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
10526         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
10527         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
10528         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
10529         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
10530         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
10531         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
10532         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
10533         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
10534         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
10535         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
10536 };
10537
10538 struct mlx5_ifc_initial_seg_bits {
10539         u8         fw_rev_minor[0x10];
10540         u8         fw_rev_major[0x10];
10541
10542         u8         cmd_interface_rev[0x10];
10543         u8         fw_rev_subminor[0x10];
10544
10545         u8         reserved_at_40[0x40];
10546
10547         u8         cmdq_phy_addr_63_32[0x20];
10548
10549         u8         cmdq_phy_addr_31_12[0x14];
10550         u8         reserved_at_b4[0x2];
10551         u8         nic_interface[0x2];
10552         u8         log_cmdq_size[0x4];
10553         u8         log_cmdq_stride[0x4];
10554
10555         u8         command_doorbell_vector[0x20];
10556
10557         u8         reserved_at_e0[0xf00];
10558
10559         u8         initializing[0x1];
10560         u8         reserved_at_fe1[0x4];
10561         u8         nic_interface_supported[0x3];
10562         u8         embedded_cpu[0x1];
10563         u8         reserved_at_fe9[0x17];
10564
10565         struct mlx5_ifc_health_buffer_bits health_buffer;
10566
10567         u8         no_dram_nic_offset[0x20];
10568
10569         u8         reserved_at_1220[0x6e40];
10570
10571         u8         reserved_at_8060[0x1f];
10572         u8         clear_int[0x1];
10573
10574         u8         health_syndrome[0x8];
10575         u8         health_counter[0x18];
10576
10577         u8         reserved_at_80a0[0x17fc0];
10578 };
10579
10580 struct mlx5_ifc_mtpps_reg_bits {
10581         u8         reserved_at_0[0xc];
10582         u8         cap_number_of_pps_pins[0x4];
10583         u8         reserved_at_10[0x4];
10584         u8         cap_max_num_of_pps_in_pins[0x4];
10585         u8         reserved_at_18[0x4];
10586         u8         cap_max_num_of_pps_out_pins[0x4];
10587
10588         u8         reserved_at_20[0x13];
10589         u8         cap_log_min_npps_period[0x5];
10590         u8         reserved_at_38[0x3];
10591         u8         cap_log_min_out_pulse_duration_ns[0x5];
10592
10593         u8         reserved_at_40[0x4];
10594         u8         cap_pin_3_mode[0x4];
10595         u8         reserved_at_48[0x4];
10596         u8         cap_pin_2_mode[0x4];
10597         u8         reserved_at_50[0x4];
10598         u8         cap_pin_1_mode[0x4];
10599         u8         reserved_at_58[0x4];
10600         u8         cap_pin_0_mode[0x4];
10601
10602         u8         reserved_at_60[0x4];
10603         u8         cap_pin_7_mode[0x4];
10604         u8         reserved_at_68[0x4];
10605         u8         cap_pin_6_mode[0x4];
10606         u8         reserved_at_70[0x4];
10607         u8         cap_pin_5_mode[0x4];
10608         u8         reserved_at_78[0x4];
10609         u8         cap_pin_4_mode[0x4];
10610
10611         u8         field_select[0x20];
10612         u8         reserved_at_a0[0x20];
10613
10614         u8         npps_period[0x40];
10615
10616         u8         enable[0x1];
10617         u8         reserved_at_101[0xb];
10618         u8         pattern[0x4];
10619         u8         reserved_at_110[0x4];
10620         u8         pin_mode[0x4];
10621         u8         pin[0x8];
10622
10623         u8         reserved_at_120[0x2];
10624         u8         out_pulse_duration_ns[0x1e];
10625
10626         u8         time_stamp[0x40];
10627
10628         u8         out_pulse_duration[0x10];
10629         u8         out_periodic_adjustment[0x10];
10630         u8         enhanced_out_periodic_adjustment[0x20];
10631
10632         u8         reserved_at_1c0[0x20];
10633 };
10634
10635 struct mlx5_ifc_mtppse_reg_bits {
10636         u8         reserved_at_0[0x18];
10637         u8         pin[0x8];
10638         u8         event_arm[0x1];
10639         u8         reserved_at_21[0x1b];
10640         u8         event_generation_mode[0x4];
10641         u8         reserved_at_40[0x40];
10642 };
10643
10644 struct mlx5_ifc_mcqs_reg_bits {
10645         u8         last_index_flag[0x1];
10646         u8         reserved_at_1[0x7];
10647         u8         fw_device[0x8];
10648         u8         component_index[0x10];
10649
10650         u8         reserved_at_20[0x10];
10651         u8         identifier[0x10];
10652
10653         u8         reserved_at_40[0x17];
10654         u8         component_status[0x5];
10655         u8         component_update_state[0x4];
10656
10657         u8         last_update_state_changer_type[0x4];
10658         u8         last_update_state_changer_host_id[0x4];
10659         u8         reserved_at_68[0x18];
10660 };
10661
10662 struct mlx5_ifc_mcqi_cap_bits {
10663         u8         supported_info_bitmask[0x20];
10664
10665         u8         component_size[0x20];
10666
10667         u8         max_component_size[0x20];
10668
10669         u8         log_mcda_word_size[0x4];
10670         u8         reserved_at_64[0xc];
10671         u8         mcda_max_write_size[0x10];
10672
10673         u8         rd_en[0x1];
10674         u8         reserved_at_81[0x1];
10675         u8         match_chip_id[0x1];
10676         u8         match_psid[0x1];
10677         u8         check_user_timestamp[0x1];
10678         u8         match_base_guid_mac[0x1];
10679         u8         reserved_at_86[0x1a];
10680 };
10681
10682 struct mlx5_ifc_mcqi_version_bits {
10683         u8         reserved_at_0[0x2];
10684         u8         build_time_valid[0x1];
10685         u8         user_defined_time_valid[0x1];
10686         u8         reserved_at_4[0x14];
10687         u8         version_string_length[0x8];
10688
10689         u8         version[0x20];
10690
10691         u8         build_time[0x40];
10692
10693         u8         user_defined_time[0x40];
10694
10695         u8         build_tool_version[0x20];
10696
10697         u8         reserved_at_e0[0x20];
10698
10699         u8         version_string[92][0x8];
10700 };
10701
10702 struct mlx5_ifc_mcqi_activation_method_bits {
10703         u8         pending_server_ac_power_cycle[0x1];
10704         u8         pending_server_dc_power_cycle[0x1];
10705         u8         pending_server_reboot[0x1];
10706         u8         pending_fw_reset[0x1];
10707         u8         auto_activate[0x1];
10708         u8         all_hosts_sync[0x1];
10709         u8         device_hw_reset[0x1];
10710         u8         reserved_at_7[0x19];
10711 };
10712
10713 union mlx5_ifc_mcqi_reg_data_bits {
10714         struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
10715         struct mlx5_ifc_mcqi_version_bits           mcqi_version;
10716         struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
10717 };
10718
10719 struct mlx5_ifc_mcqi_reg_bits {
10720         u8         read_pending_component[0x1];
10721         u8         reserved_at_1[0xf];
10722         u8         component_index[0x10];
10723
10724         u8         reserved_at_20[0x20];
10725
10726         u8         reserved_at_40[0x1b];
10727         u8         info_type[0x5];
10728
10729         u8         info_size[0x20];
10730
10731         u8         offset[0x20];
10732
10733         u8         reserved_at_a0[0x10];
10734         u8         data_size[0x10];
10735
10736         union mlx5_ifc_mcqi_reg_data_bits data[];
10737 };
10738
10739 struct mlx5_ifc_mcc_reg_bits {
10740         u8         reserved_at_0[0x4];
10741         u8         time_elapsed_since_last_cmd[0xc];
10742         u8         reserved_at_10[0x8];
10743         u8         instruction[0x8];
10744
10745         u8         reserved_at_20[0x10];
10746         u8         component_index[0x10];
10747
10748         u8         reserved_at_40[0x8];
10749         u8         update_handle[0x18];
10750
10751         u8         handle_owner_type[0x4];
10752         u8         handle_owner_host_id[0x4];
10753         u8         reserved_at_68[0x1];
10754         u8         control_progress[0x7];
10755         u8         error_code[0x8];
10756         u8         reserved_at_78[0x4];
10757         u8         control_state[0x4];
10758
10759         u8         component_size[0x20];
10760
10761         u8         reserved_at_a0[0x60];
10762 };
10763
10764 struct mlx5_ifc_mcda_reg_bits {
10765         u8         reserved_at_0[0x8];
10766         u8         update_handle[0x18];
10767
10768         u8         offset[0x20];
10769
10770         u8         reserved_at_40[0x10];
10771         u8         size[0x10];
10772
10773         u8         reserved_at_60[0x20];
10774
10775         u8         data[][0x20];
10776 };
10777
10778 enum {
10779         MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
10780         MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
10781         MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
10782         MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3,
10783         MLX5_MFRL_REG_RESET_STATE_NACK = 4,
10784 };
10785
10786 enum {
10787         MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
10788         MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
10789 };
10790
10791 enum {
10792         MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
10793         MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
10794         MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
10795 };
10796
10797 struct mlx5_ifc_mfrl_reg_bits {
10798         u8         reserved_at_0[0x20];
10799
10800         u8         reserved_at_20[0x2];
10801         u8         pci_sync_for_fw_update_start[0x1];
10802         u8         pci_sync_for_fw_update_resp[0x2];
10803         u8         rst_type_sel[0x3];
10804         u8         reserved_at_28[0x4];
10805         u8         reset_state[0x4];
10806         u8         reset_type[0x8];
10807         u8         reset_level[0x8];
10808 };
10809
10810 struct mlx5_ifc_mirc_reg_bits {
10811         u8         reserved_at_0[0x18];
10812         u8         status_code[0x8];
10813
10814         u8         reserved_at_20[0x20];
10815 };
10816
10817 struct mlx5_ifc_pddr_monitor_opcode_bits {
10818         u8         reserved_at_0[0x10];
10819         u8         monitor_opcode[0x10];
10820 };
10821
10822 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
10823         struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10824         u8         reserved_at_0[0x20];
10825 };
10826
10827 enum {
10828         /* Monitor opcodes */
10829         MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10830 };
10831
10832 struct mlx5_ifc_pddr_troubleshooting_page_bits {
10833         u8         reserved_at_0[0x10];
10834         u8         group_opcode[0x10];
10835
10836         union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
10837
10838         u8         reserved_at_40[0x20];
10839
10840         u8         status_message[59][0x20];
10841 };
10842
10843 union mlx5_ifc_pddr_reg_page_data_auto_bits {
10844         struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10845         u8         reserved_at_0[0x7c0];
10846 };
10847
10848 enum {
10849         MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
10850 };
10851
10852 struct mlx5_ifc_pddr_reg_bits {
10853         u8         reserved_at_0[0x8];
10854         u8         local_port[0x8];
10855         u8         pnat[0x2];
10856         u8         reserved_at_12[0xe];
10857
10858         u8         reserved_at_20[0x18];
10859         u8         page_select[0x8];
10860
10861         union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
10862 };
10863
10864 struct mlx5_ifc_mrtc_reg_bits {
10865         u8         time_synced[0x1];
10866         u8         reserved_at_1[0x1f];
10867
10868         u8         reserved_at_20[0x20];
10869
10870         u8         time_h[0x20];
10871
10872         u8         time_l[0x20];
10873 };
10874
10875 union mlx5_ifc_ports_control_registers_document_bits {
10876         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10877         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10878         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10879         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10880         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10881         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10882         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10883         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
10884         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
10885         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10886         struct mlx5_ifc_pamp_reg_bits pamp_reg;
10887         struct mlx5_ifc_paos_reg_bits paos_reg;
10888         struct mlx5_ifc_pcap_reg_bits pcap_reg;
10889         struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10890         struct mlx5_ifc_pddr_reg_bits pddr_reg;
10891         struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10892         struct mlx5_ifc_peir_reg_bits peir_reg;
10893         struct mlx5_ifc_pelc_reg_bits pelc_reg;
10894         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
10895         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
10896         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10897         struct mlx5_ifc_pifr_reg_bits pifr_reg;
10898         struct mlx5_ifc_pipg_reg_bits pipg_reg;
10899         struct mlx5_ifc_plbf_reg_bits plbf_reg;
10900         struct mlx5_ifc_plib_reg_bits plib_reg;
10901         struct mlx5_ifc_plpc_reg_bits plpc_reg;
10902         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10903         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10904         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10905         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10906         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10907         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10908         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10909         struct mlx5_ifc_ppad_reg_bits ppad_reg;
10910         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
10911         struct mlx5_ifc_mpein_reg_bits mpein_reg;
10912         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
10913         struct mlx5_ifc_pplm_reg_bits pplm_reg;
10914         struct mlx5_ifc_pplr_reg_bits pplr_reg;
10915         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10916         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
10917         struct mlx5_ifc_pspa_reg_bits pspa_reg;
10918         struct mlx5_ifc_ptas_reg_bits ptas_reg;
10919         struct mlx5_ifc_ptys_reg_bits ptys_reg;
10920         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
10921         struct mlx5_ifc_pude_reg_bits pude_reg;
10922         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10923         struct mlx5_ifc_slrg_reg_bits slrg_reg;
10924         struct mlx5_ifc_sltp_reg_bits sltp_reg;
10925         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
10926         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
10927         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
10928         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
10929         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
10930         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
10931         struct mlx5_ifc_mcc_reg_bits mcc_reg;
10932         struct mlx5_ifc_mcda_reg_bits mcda_reg;
10933         struct mlx5_ifc_mirc_reg_bits mirc_reg;
10934         struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
10935         struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
10936         struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
10937         u8         reserved_at_0[0x60e0];
10938 };
10939
10940 union mlx5_ifc_debug_enhancements_document_bits {
10941         struct mlx5_ifc_health_buffer_bits health_buffer;
10942         u8         reserved_at_0[0x200];
10943 };
10944
10945 union mlx5_ifc_uplink_pci_interface_document_bits {
10946         struct mlx5_ifc_initial_seg_bits initial_seg;
10947         u8         reserved_at_0[0x20060];
10948 };
10949
10950 struct mlx5_ifc_set_flow_table_root_out_bits {
10951         u8         status[0x8];
10952         u8         reserved_at_8[0x18];
10953
10954         u8         syndrome[0x20];
10955
10956         u8         reserved_at_40[0x40];
10957 };
10958
10959 struct mlx5_ifc_set_flow_table_root_in_bits {
10960         u8         opcode[0x10];
10961         u8         reserved_at_10[0x10];
10962
10963         u8         reserved_at_20[0x10];
10964         u8         op_mod[0x10];
10965
10966         u8         other_vport[0x1];
10967         u8         reserved_at_41[0xf];
10968         u8         vport_number[0x10];
10969
10970         u8         reserved_at_60[0x20];
10971
10972         u8         table_type[0x8];
10973         u8         reserved_at_88[0x7];
10974         u8         table_of_other_vport[0x1];
10975         u8         table_vport_number[0x10];
10976
10977         u8         reserved_at_a0[0x8];
10978         u8         table_id[0x18];
10979
10980         u8         reserved_at_c0[0x8];
10981         u8         underlay_qpn[0x18];
10982         u8         table_eswitch_owner_vhca_id_valid[0x1];
10983         u8         reserved_at_e1[0xf];
10984         u8         table_eswitch_owner_vhca_id[0x10];
10985         u8         reserved_at_100[0x100];
10986 };
10987
10988 enum {
10989         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
10990         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
10991 };
10992
10993 struct mlx5_ifc_modify_flow_table_out_bits {
10994         u8         status[0x8];
10995         u8         reserved_at_8[0x18];
10996
10997         u8         syndrome[0x20];
10998
10999         u8         reserved_at_40[0x40];
11000 };
11001
11002 struct mlx5_ifc_modify_flow_table_in_bits {
11003         u8         opcode[0x10];
11004         u8         reserved_at_10[0x10];
11005
11006         u8         reserved_at_20[0x10];
11007         u8         op_mod[0x10];
11008
11009         u8         other_vport[0x1];
11010         u8         reserved_at_41[0xf];
11011         u8         vport_number[0x10];
11012
11013         u8         reserved_at_60[0x10];
11014         u8         modify_field_select[0x10];
11015
11016         u8         table_type[0x8];
11017         u8         reserved_at_88[0x18];
11018
11019         u8         reserved_at_a0[0x8];
11020         u8         table_id[0x18];
11021
11022         struct mlx5_ifc_flow_table_context_bits flow_table_context;
11023 };
11024
11025 struct mlx5_ifc_ets_tcn_config_reg_bits {
11026         u8         g[0x1];
11027         u8         b[0x1];
11028         u8         r[0x1];
11029         u8         reserved_at_3[0x9];
11030         u8         group[0x4];
11031         u8         reserved_at_10[0x9];
11032         u8         bw_allocation[0x7];
11033
11034         u8         reserved_at_20[0xc];
11035         u8         max_bw_units[0x4];
11036         u8         reserved_at_30[0x8];
11037         u8         max_bw_value[0x8];
11038 };
11039
11040 struct mlx5_ifc_ets_global_config_reg_bits {
11041         u8         reserved_at_0[0x2];
11042         u8         r[0x1];
11043         u8         reserved_at_3[0x1d];
11044
11045         u8         reserved_at_20[0xc];
11046         u8         max_bw_units[0x4];
11047         u8         reserved_at_30[0x8];
11048         u8         max_bw_value[0x8];
11049 };
11050
11051 struct mlx5_ifc_qetc_reg_bits {
11052         u8                                         reserved_at_0[0x8];
11053         u8                                         port_number[0x8];
11054         u8                                         reserved_at_10[0x30];
11055
11056         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
11057         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
11058 };
11059
11060 struct mlx5_ifc_qpdpm_dscp_reg_bits {
11061         u8         e[0x1];
11062         u8         reserved_at_01[0x0b];
11063         u8         prio[0x04];
11064 };
11065
11066 struct mlx5_ifc_qpdpm_reg_bits {
11067         u8                                     reserved_at_0[0x8];
11068         u8                                     local_port[0x8];
11069         u8                                     reserved_at_10[0x10];
11070         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
11071 };
11072
11073 struct mlx5_ifc_qpts_reg_bits {
11074         u8         reserved_at_0[0x8];
11075         u8         local_port[0x8];
11076         u8         reserved_at_10[0x2d];
11077         u8         trust_state[0x3];
11078 };
11079
11080 struct mlx5_ifc_pptb_reg_bits {
11081         u8         reserved_at_0[0x2];
11082         u8         mm[0x2];
11083         u8         reserved_at_4[0x4];
11084         u8         local_port[0x8];
11085         u8         reserved_at_10[0x6];
11086         u8         cm[0x1];
11087         u8         um[0x1];
11088         u8         pm[0x8];
11089
11090         u8         prio_x_buff[0x20];
11091
11092         u8         pm_msb[0x8];
11093         u8         reserved_at_48[0x10];
11094         u8         ctrl_buff[0x4];
11095         u8         untagged_buff[0x4];
11096 };
11097
11098 struct mlx5_ifc_sbcam_reg_bits {
11099         u8         reserved_at_0[0x8];
11100         u8         feature_group[0x8];
11101         u8         reserved_at_10[0x8];
11102         u8         access_reg_group[0x8];
11103
11104         u8         reserved_at_20[0x20];
11105
11106         u8         sb_access_reg_cap_mask[4][0x20];
11107
11108         u8         reserved_at_c0[0x80];
11109
11110         u8         sb_feature_cap_mask[4][0x20];
11111
11112         u8         reserved_at_1c0[0x40];
11113
11114         u8         cap_total_buffer_size[0x20];
11115
11116         u8         cap_cell_size[0x10];
11117         u8         cap_max_pg_buffers[0x8];
11118         u8         cap_num_pool_supported[0x8];
11119
11120         u8         reserved_at_240[0x8];
11121         u8         cap_sbsr_stat_size[0x8];
11122         u8         cap_max_tclass_data[0x8];
11123         u8         cap_max_cpu_ingress_tclass_sb[0x8];
11124 };
11125
11126 struct mlx5_ifc_pbmc_reg_bits {
11127         u8         reserved_at_0[0x8];
11128         u8         local_port[0x8];
11129         u8         reserved_at_10[0x10];
11130
11131         u8         xoff_timer_value[0x10];
11132         u8         xoff_refresh[0x10];
11133
11134         u8         reserved_at_40[0x9];
11135         u8         fullness_threshold[0x7];
11136         u8         port_buffer_size[0x10];
11137
11138         struct mlx5_ifc_bufferx_reg_bits buffer[10];
11139
11140         u8         reserved_at_2e0[0x80];
11141 };
11142
11143 struct mlx5_ifc_sbpr_reg_bits {
11144         u8         desc[0x1];
11145         u8         snap[0x1];
11146         u8         reserved_at_2[0x4];
11147         u8         dir[0x2];
11148         u8         reserved_at_8[0x14];
11149         u8         pool[0x4];
11150
11151         u8         infi_size[0x1];
11152         u8         reserved_at_21[0x7];
11153         u8         size[0x18];
11154
11155         u8         reserved_at_40[0x1c];
11156         u8         mode[0x4];
11157
11158         u8         reserved_at_60[0x8];
11159         u8         buff_occupancy[0x18];
11160
11161         u8         clr[0x1];
11162         u8         reserved_at_81[0x7];
11163         u8         max_buff_occupancy[0x18];
11164
11165         u8         reserved_at_a0[0x8];
11166         u8         ext_buff_occupancy[0x18];
11167 };
11168
11169 struct mlx5_ifc_sbcm_reg_bits {
11170         u8         desc[0x1];
11171         u8         snap[0x1];
11172         u8         reserved_at_2[0x6];
11173         u8         local_port[0x8];
11174         u8         pnat[0x2];
11175         u8         pg_buff[0x6];
11176         u8         reserved_at_18[0x6];
11177         u8         dir[0x2];
11178
11179         u8         reserved_at_20[0x1f];
11180         u8         exc[0x1];
11181
11182         u8         reserved_at_40[0x40];
11183
11184         u8         reserved_at_80[0x8];
11185         u8         buff_occupancy[0x18];
11186
11187         u8         clr[0x1];
11188         u8         reserved_at_a1[0x7];
11189         u8         max_buff_occupancy[0x18];
11190
11191         u8         reserved_at_c0[0x8];
11192         u8         min_buff[0x18];
11193
11194         u8         infi_max[0x1];
11195         u8         reserved_at_e1[0x7];
11196         u8         max_buff[0x18];
11197
11198         u8         reserved_at_100[0x20];
11199
11200         u8         reserved_at_120[0x1c];
11201         u8         pool[0x4];
11202 };
11203
11204 struct mlx5_ifc_qtct_reg_bits {
11205         u8         reserved_at_0[0x8];
11206         u8         port_number[0x8];
11207         u8         reserved_at_10[0xd];
11208         u8         prio[0x3];
11209
11210         u8         reserved_at_20[0x1d];
11211         u8         tclass[0x3];
11212 };
11213
11214 struct mlx5_ifc_mcia_reg_bits {
11215         u8         l[0x1];
11216         u8         reserved_at_1[0x7];
11217         u8         module[0x8];
11218         u8         reserved_at_10[0x8];
11219         u8         status[0x8];
11220
11221         u8         i2c_device_address[0x8];
11222         u8         page_number[0x8];
11223         u8         device_address[0x10];
11224
11225         u8         reserved_at_40[0x10];
11226         u8         size[0x10];
11227
11228         u8         reserved_at_60[0x20];
11229
11230         u8         dword_0[0x20];
11231         u8         dword_1[0x20];
11232         u8         dword_2[0x20];
11233         u8         dword_3[0x20];
11234         u8         dword_4[0x20];
11235         u8         dword_5[0x20];
11236         u8         dword_6[0x20];
11237         u8         dword_7[0x20];
11238         u8         dword_8[0x20];
11239         u8         dword_9[0x20];
11240         u8         dword_10[0x20];
11241         u8         dword_11[0x20];
11242 };
11243
11244 struct mlx5_ifc_dcbx_param_bits {
11245         u8         dcbx_cee_cap[0x1];
11246         u8         dcbx_ieee_cap[0x1];
11247         u8         dcbx_standby_cap[0x1];
11248         u8         reserved_at_3[0x5];
11249         u8         port_number[0x8];
11250         u8         reserved_at_10[0xa];
11251         u8         max_application_table_size[6];
11252         u8         reserved_at_20[0x15];
11253         u8         version_oper[0x3];
11254         u8         reserved_at_38[5];
11255         u8         version_admin[0x3];
11256         u8         willing_admin[0x1];
11257         u8         reserved_at_41[0x3];
11258         u8         pfc_cap_oper[0x4];
11259         u8         reserved_at_48[0x4];
11260         u8         pfc_cap_admin[0x4];
11261         u8         reserved_at_50[0x4];
11262         u8         num_of_tc_oper[0x4];
11263         u8         reserved_at_58[0x4];
11264         u8         num_of_tc_admin[0x4];
11265         u8         remote_willing[0x1];
11266         u8         reserved_at_61[3];
11267         u8         remote_pfc_cap[4];
11268         u8         reserved_at_68[0x14];
11269         u8         remote_num_of_tc[0x4];
11270         u8         reserved_at_80[0x18];
11271         u8         error[0x8];
11272         u8         reserved_at_a0[0x160];
11273 };
11274
11275 enum {
11276         MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
11277         MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
11278         MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
11279 };
11280
11281 struct mlx5_ifc_lagc_bits {
11282         u8         fdb_selection_mode[0x1];
11283         u8         reserved_at_1[0x14];
11284         u8         port_select_mode[0x3];
11285         u8         reserved_at_18[0x5];
11286         u8         lag_state[0x3];
11287
11288         u8         reserved_at_20[0xc];
11289         u8         active_port[0x4];
11290         u8         reserved_at_30[0x4];
11291         u8         tx_remap_affinity_2[0x4];
11292         u8         reserved_at_38[0x4];
11293         u8         tx_remap_affinity_1[0x4];
11294 };
11295
11296 struct mlx5_ifc_create_lag_out_bits {
11297         u8         status[0x8];
11298         u8         reserved_at_8[0x18];
11299
11300         u8         syndrome[0x20];
11301
11302         u8         reserved_at_40[0x40];
11303 };
11304
11305 struct mlx5_ifc_create_lag_in_bits {
11306         u8         opcode[0x10];
11307         u8         reserved_at_10[0x10];
11308
11309         u8         reserved_at_20[0x10];
11310         u8         op_mod[0x10];
11311
11312         struct mlx5_ifc_lagc_bits ctx;
11313 };
11314
11315 struct mlx5_ifc_modify_lag_out_bits {
11316         u8         status[0x8];
11317         u8         reserved_at_8[0x18];
11318
11319         u8         syndrome[0x20];
11320
11321         u8         reserved_at_40[0x40];
11322 };
11323
11324 struct mlx5_ifc_modify_lag_in_bits {
11325         u8         opcode[0x10];
11326         u8         reserved_at_10[0x10];
11327
11328         u8         reserved_at_20[0x10];
11329         u8         op_mod[0x10];
11330
11331         u8         reserved_at_40[0x20];
11332         u8         field_select[0x20];
11333
11334         struct mlx5_ifc_lagc_bits ctx;
11335 };
11336
11337 struct mlx5_ifc_query_lag_out_bits {
11338         u8         status[0x8];
11339         u8         reserved_at_8[0x18];
11340
11341         u8         syndrome[0x20];
11342
11343         struct mlx5_ifc_lagc_bits ctx;
11344 };
11345
11346 struct mlx5_ifc_query_lag_in_bits {
11347         u8         opcode[0x10];
11348         u8         reserved_at_10[0x10];
11349
11350         u8         reserved_at_20[0x10];
11351         u8         op_mod[0x10];
11352
11353         u8         reserved_at_40[0x40];
11354 };
11355
11356 struct mlx5_ifc_destroy_lag_out_bits {
11357         u8         status[0x8];
11358         u8         reserved_at_8[0x18];
11359
11360         u8         syndrome[0x20];
11361
11362         u8         reserved_at_40[0x40];
11363 };
11364
11365 struct mlx5_ifc_destroy_lag_in_bits {
11366         u8         opcode[0x10];
11367         u8         reserved_at_10[0x10];
11368
11369         u8         reserved_at_20[0x10];
11370         u8         op_mod[0x10];
11371
11372         u8         reserved_at_40[0x40];
11373 };
11374
11375 struct mlx5_ifc_create_vport_lag_out_bits {
11376         u8         status[0x8];
11377         u8         reserved_at_8[0x18];
11378
11379         u8         syndrome[0x20];
11380
11381         u8         reserved_at_40[0x40];
11382 };
11383
11384 struct mlx5_ifc_create_vport_lag_in_bits {
11385         u8         opcode[0x10];
11386         u8         reserved_at_10[0x10];
11387
11388         u8         reserved_at_20[0x10];
11389         u8         op_mod[0x10];
11390
11391         u8         reserved_at_40[0x40];
11392 };
11393
11394 struct mlx5_ifc_destroy_vport_lag_out_bits {
11395         u8         status[0x8];
11396         u8         reserved_at_8[0x18];
11397
11398         u8         syndrome[0x20];
11399
11400         u8         reserved_at_40[0x40];
11401 };
11402
11403 struct mlx5_ifc_destroy_vport_lag_in_bits {
11404         u8         opcode[0x10];
11405         u8         reserved_at_10[0x10];
11406
11407         u8         reserved_at_20[0x10];
11408         u8         op_mod[0x10];
11409
11410         u8         reserved_at_40[0x40];
11411 };
11412
11413 enum {
11414         MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
11415         MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
11416 };
11417
11418 struct mlx5_ifc_modify_memic_in_bits {
11419         u8         opcode[0x10];
11420         u8         uid[0x10];
11421
11422         u8         reserved_at_20[0x10];
11423         u8         op_mod[0x10];
11424
11425         u8         reserved_at_40[0x20];
11426
11427         u8         reserved_at_60[0x18];
11428         u8         memic_operation_type[0x8];
11429
11430         u8         memic_start_addr[0x40];
11431
11432         u8         reserved_at_c0[0x140];
11433 };
11434
11435 struct mlx5_ifc_modify_memic_out_bits {
11436         u8         status[0x8];
11437         u8         reserved_at_8[0x18];
11438
11439         u8         syndrome[0x20];
11440
11441         u8         reserved_at_40[0x40];
11442
11443         u8         memic_operation_addr[0x40];
11444
11445         u8         reserved_at_c0[0x140];
11446 };
11447
11448 struct mlx5_ifc_alloc_memic_in_bits {
11449         u8         opcode[0x10];
11450         u8         reserved_at_10[0x10];
11451
11452         u8         reserved_at_20[0x10];
11453         u8         op_mod[0x10];
11454
11455         u8         reserved_at_30[0x20];
11456
11457         u8         reserved_at_40[0x18];
11458         u8         log_memic_addr_alignment[0x8];
11459
11460         u8         range_start_addr[0x40];
11461
11462         u8         range_size[0x20];
11463
11464         u8         memic_size[0x20];
11465 };
11466
11467 struct mlx5_ifc_alloc_memic_out_bits {
11468         u8         status[0x8];
11469         u8         reserved_at_8[0x18];
11470
11471         u8         syndrome[0x20];
11472
11473         u8         memic_start_addr[0x40];
11474 };
11475
11476 struct mlx5_ifc_dealloc_memic_in_bits {
11477         u8         opcode[0x10];
11478         u8         reserved_at_10[0x10];
11479
11480         u8         reserved_at_20[0x10];
11481         u8         op_mod[0x10];
11482
11483         u8         reserved_at_40[0x40];
11484
11485         u8         memic_start_addr[0x40];
11486
11487         u8         memic_size[0x20];
11488
11489         u8         reserved_at_e0[0x20];
11490 };
11491
11492 struct mlx5_ifc_dealloc_memic_out_bits {
11493         u8         status[0x8];
11494         u8         reserved_at_8[0x18];
11495
11496         u8         syndrome[0x20];
11497
11498         u8         reserved_at_40[0x40];
11499 };
11500
11501 struct mlx5_ifc_umem_bits {
11502         u8         reserved_at_0[0x80];
11503
11504         u8         ats[0x1];
11505         u8         reserved_at_81[0x1a];
11506         u8         log_page_size[0x5];
11507
11508         u8         page_offset[0x20];
11509
11510         u8         num_of_mtt[0x40];
11511
11512         struct mlx5_ifc_mtt_bits  mtt[];
11513 };
11514
11515 struct mlx5_ifc_uctx_bits {
11516         u8         cap[0x20];
11517
11518         u8         reserved_at_20[0x160];
11519 };
11520
11521 struct mlx5_ifc_sw_icm_bits {
11522         u8         modify_field_select[0x40];
11523
11524         u8         reserved_at_40[0x18];
11525         u8         log_sw_icm_size[0x8];
11526
11527         u8         reserved_at_60[0x20];
11528
11529         u8         sw_icm_start_addr[0x40];
11530
11531         u8         reserved_at_c0[0x140];
11532 };
11533
11534 struct mlx5_ifc_geneve_tlv_option_bits {
11535         u8         modify_field_select[0x40];
11536
11537         u8         reserved_at_40[0x18];
11538         u8         geneve_option_fte_index[0x8];
11539
11540         u8         option_class[0x10];
11541         u8         option_type[0x8];
11542         u8         reserved_at_78[0x3];
11543         u8         option_data_length[0x5];
11544
11545         u8         reserved_at_80[0x180];
11546 };
11547
11548 struct mlx5_ifc_create_umem_in_bits {
11549         u8         opcode[0x10];
11550         u8         uid[0x10];
11551
11552         u8         reserved_at_20[0x10];
11553         u8         op_mod[0x10];
11554
11555         u8         reserved_at_40[0x40];
11556
11557         struct mlx5_ifc_umem_bits  umem;
11558 };
11559
11560 struct mlx5_ifc_create_umem_out_bits {
11561         u8         status[0x8];
11562         u8         reserved_at_8[0x18];
11563
11564         u8         syndrome[0x20];
11565
11566         u8         reserved_at_40[0x8];
11567         u8         umem_id[0x18];
11568
11569         u8         reserved_at_60[0x20];
11570 };
11571
11572 struct mlx5_ifc_destroy_umem_in_bits {
11573         u8        opcode[0x10];
11574         u8        uid[0x10];
11575
11576         u8        reserved_at_20[0x10];
11577         u8        op_mod[0x10];
11578
11579         u8        reserved_at_40[0x8];
11580         u8        umem_id[0x18];
11581
11582         u8        reserved_at_60[0x20];
11583 };
11584
11585 struct mlx5_ifc_destroy_umem_out_bits {
11586         u8        status[0x8];
11587         u8        reserved_at_8[0x18];
11588
11589         u8        syndrome[0x20];
11590
11591         u8        reserved_at_40[0x40];
11592 };
11593
11594 struct mlx5_ifc_create_uctx_in_bits {
11595         u8         opcode[0x10];
11596         u8         reserved_at_10[0x10];
11597
11598         u8         reserved_at_20[0x10];
11599         u8         op_mod[0x10];
11600
11601         u8         reserved_at_40[0x40];
11602
11603         struct mlx5_ifc_uctx_bits  uctx;
11604 };
11605
11606 struct mlx5_ifc_create_uctx_out_bits {
11607         u8         status[0x8];
11608         u8         reserved_at_8[0x18];
11609
11610         u8         syndrome[0x20];
11611
11612         u8         reserved_at_40[0x10];
11613         u8         uid[0x10];
11614
11615         u8         reserved_at_60[0x20];
11616 };
11617
11618 struct mlx5_ifc_destroy_uctx_in_bits {
11619         u8         opcode[0x10];
11620         u8         reserved_at_10[0x10];
11621
11622         u8         reserved_at_20[0x10];
11623         u8         op_mod[0x10];
11624
11625         u8         reserved_at_40[0x10];
11626         u8         uid[0x10];
11627
11628         u8         reserved_at_60[0x20];
11629 };
11630
11631 struct mlx5_ifc_destroy_uctx_out_bits {
11632         u8         status[0x8];
11633         u8         reserved_at_8[0x18];
11634
11635         u8         syndrome[0x20];
11636
11637         u8          reserved_at_40[0x40];
11638 };
11639
11640 struct mlx5_ifc_create_sw_icm_in_bits {
11641         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11642         struct mlx5_ifc_sw_icm_bits                   sw_icm;
11643 };
11644
11645 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
11646         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11647         struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
11648 };
11649
11650 struct mlx5_ifc_mtrc_string_db_param_bits {
11651         u8         string_db_base_address[0x20];
11652
11653         u8         reserved_at_20[0x8];
11654         u8         string_db_size[0x18];
11655 };
11656
11657 struct mlx5_ifc_mtrc_cap_bits {
11658         u8         trace_owner[0x1];
11659         u8         trace_to_memory[0x1];
11660         u8         reserved_at_2[0x4];
11661         u8         trc_ver[0x2];
11662         u8         reserved_at_8[0x14];
11663         u8         num_string_db[0x4];
11664
11665         u8         first_string_trace[0x8];
11666         u8         num_string_trace[0x8];
11667         u8         reserved_at_30[0x28];
11668
11669         u8         log_max_trace_buffer_size[0x8];
11670
11671         u8         reserved_at_60[0x20];
11672
11673         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
11674
11675         u8         reserved_at_280[0x180];
11676 };
11677
11678 struct mlx5_ifc_mtrc_conf_bits {
11679         u8         reserved_at_0[0x1c];
11680         u8         trace_mode[0x4];
11681         u8         reserved_at_20[0x18];
11682         u8         log_trace_buffer_size[0x8];
11683         u8         trace_mkey[0x20];
11684         u8         reserved_at_60[0x3a0];
11685 };
11686
11687 struct mlx5_ifc_mtrc_stdb_bits {
11688         u8         string_db_index[0x4];
11689         u8         reserved_at_4[0x4];
11690         u8         read_size[0x18];
11691         u8         start_offset[0x20];
11692         u8         string_db_data[];
11693 };
11694
11695 struct mlx5_ifc_mtrc_ctrl_bits {
11696         u8         trace_status[0x2];
11697         u8         reserved_at_2[0x2];
11698         u8         arm_event[0x1];
11699         u8         reserved_at_5[0xb];
11700         u8         modify_field_select[0x10];
11701         u8         reserved_at_20[0x2b];
11702         u8         current_timestamp52_32[0x15];
11703         u8         current_timestamp31_0[0x20];
11704         u8         reserved_at_80[0x180];
11705 };
11706
11707 struct mlx5_ifc_host_params_context_bits {
11708         u8         host_number[0x8];
11709         u8         reserved_at_8[0x7];
11710         u8         host_pf_disabled[0x1];
11711         u8         host_num_of_vfs[0x10];
11712
11713         u8         host_total_vfs[0x10];
11714         u8         host_pci_bus[0x10];
11715
11716         u8         reserved_at_40[0x10];
11717         u8         host_pci_device[0x10];
11718
11719         u8         reserved_at_60[0x10];
11720         u8         host_pci_function[0x10];
11721
11722         u8         reserved_at_80[0x180];
11723 };
11724
11725 struct mlx5_ifc_query_esw_functions_in_bits {
11726         u8         opcode[0x10];
11727         u8         reserved_at_10[0x10];
11728
11729         u8         reserved_at_20[0x10];
11730         u8         op_mod[0x10];
11731
11732         u8         reserved_at_40[0x40];
11733 };
11734
11735 struct mlx5_ifc_query_esw_functions_out_bits {
11736         u8         status[0x8];
11737         u8         reserved_at_8[0x18];
11738
11739         u8         syndrome[0x20];
11740
11741         u8         reserved_at_40[0x40];
11742
11743         struct mlx5_ifc_host_params_context_bits host_params_context;
11744
11745         u8         reserved_at_280[0x180];
11746         u8         host_sf_enable[][0x40];
11747 };
11748
11749 struct mlx5_ifc_sf_partition_bits {
11750         u8         reserved_at_0[0x10];
11751         u8         log_num_sf[0x8];
11752         u8         log_sf_bar_size[0x8];
11753 };
11754
11755 struct mlx5_ifc_query_sf_partitions_out_bits {
11756         u8         status[0x8];
11757         u8         reserved_at_8[0x18];
11758
11759         u8         syndrome[0x20];
11760
11761         u8         reserved_at_40[0x18];
11762         u8         num_sf_partitions[0x8];
11763
11764         u8         reserved_at_60[0x20];
11765
11766         struct mlx5_ifc_sf_partition_bits sf_partition[];
11767 };
11768
11769 struct mlx5_ifc_query_sf_partitions_in_bits {
11770         u8         opcode[0x10];
11771         u8         reserved_at_10[0x10];
11772
11773         u8         reserved_at_20[0x10];
11774         u8         op_mod[0x10];
11775
11776         u8         reserved_at_40[0x40];
11777 };
11778
11779 struct mlx5_ifc_dealloc_sf_out_bits {
11780         u8         status[0x8];
11781         u8         reserved_at_8[0x18];
11782
11783         u8         syndrome[0x20];
11784
11785         u8         reserved_at_40[0x40];
11786 };
11787
11788 struct mlx5_ifc_dealloc_sf_in_bits {
11789         u8         opcode[0x10];
11790         u8         reserved_at_10[0x10];
11791
11792         u8         reserved_at_20[0x10];
11793         u8         op_mod[0x10];
11794
11795         u8         reserved_at_40[0x10];
11796         u8         function_id[0x10];
11797
11798         u8         reserved_at_60[0x20];
11799 };
11800
11801 struct mlx5_ifc_alloc_sf_out_bits {
11802         u8         status[0x8];
11803         u8         reserved_at_8[0x18];
11804
11805         u8         syndrome[0x20];
11806
11807         u8         reserved_at_40[0x40];
11808 };
11809
11810 struct mlx5_ifc_alloc_sf_in_bits {
11811         u8         opcode[0x10];
11812         u8         reserved_at_10[0x10];
11813
11814         u8         reserved_at_20[0x10];
11815         u8         op_mod[0x10];
11816
11817         u8         reserved_at_40[0x10];
11818         u8         function_id[0x10];
11819
11820         u8         reserved_at_60[0x20];
11821 };
11822
11823 struct mlx5_ifc_affiliated_event_header_bits {
11824         u8         reserved_at_0[0x10];
11825         u8         obj_type[0x10];
11826
11827         u8         obj_id[0x20];
11828 };
11829
11830 enum {
11831         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
11832         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
11833         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
11834         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24),
11835 };
11836
11837 enum {
11838         MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
11839         MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
11840         MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
11841         MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
11842         MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
11843         MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47,
11844 };
11845
11846 enum {
11847         MLX5_IPSEC_OBJECT_ICV_LEN_16B,
11848 };
11849
11850 enum {
11851         MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
11852         MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
11853         MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
11854         MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
11855 };
11856
11857 enum {
11858         MLX5_IPSEC_ASO_MODE              = 0x0,
11859         MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
11860         MLX5_IPSEC_ASO_INC_SN            = 0x2,
11861 };
11862
11863 struct mlx5_ifc_ipsec_aso_bits {
11864         u8         valid[0x1];
11865         u8         reserved_at_201[0x1];
11866         u8         mode[0x2];
11867         u8         window_sz[0x2];
11868         u8         soft_lft_arm[0x1];
11869         u8         hard_lft_arm[0x1];
11870         u8         remove_flow_enable[0x1];
11871         u8         esn_event_arm[0x1];
11872         u8         reserved_at_20a[0x16];
11873
11874         u8         remove_flow_pkt_cnt[0x20];
11875
11876         u8         remove_flow_soft_lft[0x20];
11877
11878         u8         reserved_at_260[0x80];
11879
11880         u8         mode_parameter[0x20];
11881
11882         u8         replay_protection_window[0x100];
11883 };
11884
11885 struct mlx5_ifc_ipsec_obj_bits {
11886         u8         modify_field_select[0x40];
11887         u8         full_offload[0x1];
11888         u8         reserved_at_41[0x1];
11889         u8         esn_en[0x1];
11890         u8         esn_overlap[0x1];
11891         u8         reserved_at_44[0x2];
11892         u8         icv_length[0x2];
11893         u8         reserved_at_48[0x4];
11894         u8         aso_return_reg[0x4];
11895         u8         reserved_at_50[0x10];
11896
11897         u8         esn_msb[0x20];
11898
11899         u8         reserved_at_80[0x8];
11900         u8         dekn[0x18];
11901
11902         u8         salt[0x20];
11903
11904         u8         implicit_iv[0x40];
11905
11906         u8         reserved_at_100[0x8];
11907         u8         ipsec_aso_access_pd[0x18];
11908         u8         reserved_at_120[0xe0];
11909
11910         struct mlx5_ifc_ipsec_aso_bits ipsec_aso;
11911 };
11912
11913 struct mlx5_ifc_create_ipsec_obj_in_bits {
11914         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11915         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11916 };
11917
11918 enum {
11919         MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
11920         MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
11921 };
11922
11923 struct mlx5_ifc_query_ipsec_obj_out_bits {
11924         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11925         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11926 };
11927
11928 struct mlx5_ifc_modify_ipsec_obj_in_bits {
11929         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11930         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11931 };
11932
11933 enum {
11934         MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
11935 };
11936
11937 enum {
11938         MLX5_MACSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
11939         MLX5_MACSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
11940         MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
11941         MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
11942 };
11943
11944 #define MLX5_MACSEC_ASO_INC_SN  0x2
11945 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2
11946
11947 struct mlx5_ifc_macsec_aso_bits {
11948         u8    valid[0x1];
11949         u8    reserved_at_1[0x1];
11950         u8    mode[0x2];
11951         u8    window_size[0x2];
11952         u8    soft_lifetime_arm[0x1];
11953         u8    hard_lifetime_arm[0x1];
11954         u8    remove_flow_enable[0x1];
11955         u8    epn_event_arm[0x1];
11956         u8    reserved_at_a[0x16];
11957
11958         u8    remove_flow_packet_count[0x20];
11959
11960         u8    remove_flow_soft_lifetime[0x20];
11961
11962         u8    reserved_at_60[0x80];
11963
11964         u8    mode_parameter[0x20];
11965
11966         u8    replay_protection_window[8][0x20];
11967 };
11968
11969 struct mlx5_ifc_macsec_offload_obj_bits {
11970         u8    modify_field_select[0x40];
11971
11972         u8    confidentiality_en[0x1];
11973         u8    reserved_at_41[0x1];
11974         u8    epn_en[0x1];
11975         u8    epn_overlap[0x1];
11976         u8    reserved_at_44[0x2];
11977         u8    confidentiality_offset[0x2];
11978         u8    reserved_at_48[0x4];
11979         u8    aso_return_reg[0x4];
11980         u8    reserved_at_50[0x10];
11981
11982         u8    epn_msb[0x20];
11983
11984         u8    reserved_at_80[0x8];
11985         u8    dekn[0x18];
11986
11987         u8    reserved_at_a0[0x20];
11988
11989         u8    sci[0x40];
11990
11991         u8    reserved_at_100[0x8];
11992         u8    macsec_aso_access_pd[0x18];
11993
11994         u8    reserved_at_120[0x60];
11995
11996         u8    salt[3][0x20];
11997
11998         u8    reserved_at_1e0[0x20];
11999
12000         struct mlx5_ifc_macsec_aso_bits macsec_aso;
12001 };
12002
12003 struct mlx5_ifc_create_macsec_obj_in_bits {
12004         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12005         struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12006 };
12007
12008 struct mlx5_ifc_modify_macsec_obj_in_bits {
12009         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12010         struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12011 };
12012
12013 enum {
12014         MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0),
12015         MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1),
12016 };
12017
12018 struct mlx5_ifc_query_macsec_obj_out_bits {
12019         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12020         struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12021 };
12022
12023 struct mlx5_ifc_wrapped_dek_bits {
12024         u8         gcm_iv[0x60];
12025
12026         u8         reserved_at_60[0x20];
12027
12028         u8         const0[0x1];
12029         u8         key_size[0x1];
12030         u8         reserved_at_82[0x2];
12031         u8         key2_invalid[0x1];
12032         u8         reserved_at_85[0x3];
12033         u8         pd[0x18];
12034
12035         u8         key_purpose[0x5];
12036         u8         reserved_at_a5[0x13];
12037         u8         kek_id[0x8];
12038
12039         u8         reserved_at_c0[0x40];
12040
12041         u8         key1[0x8][0x20];
12042
12043         u8         key2[0x8][0x20];
12044
12045         u8         reserved_at_300[0x40];
12046
12047         u8         const1[0x1];
12048         u8         reserved_at_341[0x1f];
12049
12050         u8         reserved_at_360[0x20];
12051
12052         u8         auth_tag[0x80];
12053 };
12054
12055 struct mlx5_ifc_encryption_key_obj_bits {
12056         u8         modify_field_select[0x40];
12057
12058         u8         state[0x8];
12059         u8         sw_wrapped[0x1];
12060         u8         reserved_at_49[0xb];
12061         u8         key_size[0x4];
12062         u8         reserved_at_58[0x4];
12063         u8         key_purpose[0x4];
12064
12065         u8         reserved_at_60[0x8];
12066         u8         pd[0x18];
12067
12068         u8         reserved_at_80[0x100];
12069
12070         u8         opaque[0x40];
12071
12072         u8         reserved_at_1c0[0x40];
12073
12074         u8         key[8][0x80];
12075
12076         u8         sw_wrapped_dek[8][0x80];
12077
12078         u8         reserved_at_a00[0x600];
12079 };
12080
12081 struct mlx5_ifc_create_encryption_key_in_bits {
12082         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12083         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12084 };
12085
12086 struct mlx5_ifc_modify_encryption_key_in_bits {
12087         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12088         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12089 };
12090
12091 enum {
12092         MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH            = 0x0,
12093         MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2         = 0x1,
12094         MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG     = 0x2,
12095         MLX5_FLOW_METER_MODE_NUM_PACKETS                = 0x3,
12096 };
12097
12098 struct mlx5_ifc_flow_meter_parameters_bits {
12099         u8         valid[0x1];
12100         u8         bucket_overflow[0x1];
12101         u8         start_color[0x2];
12102         u8         both_buckets_on_green[0x1];
12103         u8         reserved_at_5[0x1];
12104         u8         meter_mode[0x2];
12105         u8         reserved_at_8[0x18];
12106
12107         u8         reserved_at_20[0x20];
12108
12109         u8         reserved_at_40[0x3];
12110         u8         cbs_exponent[0x5];
12111         u8         cbs_mantissa[0x8];
12112         u8         reserved_at_50[0x3];
12113         u8         cir_exponent[0x5];
12114         u8         cir_mantissa[0x8];
12115
12116         u8         reserved_at_60[0x20];
12117
12118         u8         reserved_at_80[0x3];
12119         u8         ebs_exponent[0x5];
12120         u8         ebs_mantissa[0x8];
12121         u8         reserved_at_90[0x3];
12122         u8         eir_exponent[0x5];
12123         u8         eir_mantissa[0x8];
12124
12125         u8         reserved_at_a0[0x60];
12126 };
12127
12128 struct mlx5_ifc_flow_meter_aso_obj_bits {
12129         u8         modify_field_select[0x40];
12130
12131         u8         reserved_at_40[0x40];
12132
12133         u8         reserved_at_80[0x8];
12134         u8         meter_aso_access_pd[0x18];
12135
12136         u8         reserved_at_a0[0x160];
12137
12138         struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2];
12139 };
12140
12141 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits {
12142         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
12143         struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj;
12144 };
12145
12146 struct mlx5_ifc_int_kek_obj_bits {
12147         u8         modify_field_select[0x40];
12148
12149         u8         state[0x8];
12150         u8         auto_gen[0x1];
12151         u8         reserved_at_49[0xb];
12152         u8         key_size[0x4];
12153         u8         reserved_at_58[0x8];
12154
12155         u8         reserved_at_60[0x8];
12156         u8         pd[0x18];
12157
12158         u8         reserved_at_80[0x180];
12159         u8         key[8][0x80];
12160
12161         u8         reserved_at_600[0x200];
12162 };
12163
12164 struct mlx5_ifc_create_int_kek_obj_in_bits {
12165         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12166         struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12167 };
12168
12169 struct mlx5_ifc_create_int_kek_obj_out_bits {
12170         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12171         struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12172 };
12173
12174 struct mlx5_ifc_sampler_obj_bits {
12175         u8         modify_field_select[0x40];
12176
12177         u8         table_type[0x8];
12178         u8         level[0x8];
12179         u8         reserved_at_50[0xf];
12180         u8         ignore_flow_level[0x1];
12181
12182         u8         sample_ratio[0x20];
12183
12184         u8         reserved_at_80[0x8];
12185         u8         sample_table_id[0x18];
12186
12187         u8         reserved_at_a0[0x8];
12188         u8         default_table_id[0x18];
12189
12190         u8         sw_steering_icm_address_rx[0x40];
12191         u8         sw_steering_icm_address_tx[0x40];
12192
12193         u8         reserved_at_140[0xa0];
12194 };
12195
12196 struct mlx5_ifc_create_sampler_obj_in_bits {
12197         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12198         struct mlx5_ifc_sampler_obj_bits sampler_object;
12199 };
12200
12201 struct mlx5_ifc_query_sampler_obj_out_bits {
12202         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12203         struct mlx5_ifc_sampler_obj_bits sampler_object;
12204 };
12205
12206 enum {
12207         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
12208         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
12209 };
12210
12211 enum {
12212         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1,
12213         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2,
12214         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4,
12215 };
12216
12217 struct mlx5_ifc_tls_static_params_bits {
12218         u8         const_2[0x2];
12219         u8         tls_version[0x4];
12220         u8         const_1[0x2];
12221         u8         reserved_at_8[0x14];
12222         u8         encryption_standard[0x4];
12223
12224         u8         reserved_at_20[0x20];
12225
12226         u8         initial_record_number[0x40];
12227
12228         u8         resync_tcp_sn[0x20];
12229
12230         u8         gcm_iv[0x20];
12231
12232         u8         implicit_iv[0x40];
12233
12234         u8         reserved_at_100[0x8];
12235         u8         dek_index[0x18];
12236
12237         u8         reserved_at_120[0xe0];
12238 };
12239
12240 struct mlx5_ifc_tls_progress_params_bits {
12241         u8         next_record_tcp_sn[0x20];
12242
12243         u8         hw_resync_tcp_sn[0x20];
12244
12245         u8         record_tracker_state[0x2];
12246         u8         auth_state[0x2];
12247         u8         reserved_at_44[0x4];
12248         u8         hw_offset_record_number[0x18];
12249 };
12250
12251 enum {
12252         MLX5_MTT_PERM_READ      = 1 << 0,
12253         MLX5_MTT_PERM_WRITE     = 1 << 1,
12254         MLX5_MTT_PERM_RW        = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
12255 };
12256
12257 enum {
12258         MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR  = 0x0,
12259         MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER  = 0x1,
12260 };
12261
12262 struct mlx5_ifc_suspend_vhca_in_bits {
12263         u8         opcode[0x10];
12264         u8         uid[0x10];
12265
12266         u8         reserved_at_20[0x10];
12267         u8         op_mod[0x10];
12268
12269         u8         reserved_at_40[0x10];
12270         u8         vhca_id[0x10];
12271
12272         u8         reserved_at_60[0x20];
12273 };
12274
12275 struct mlx5_ifc_suspend_vhca_out_bits {
12276         u8         status[0x8];
12277         u8         reserved_at_8[0x18];
12278
12279         u8         syndrome[0x20];
12280
12281         u8         reserved_at_40[0x40];
12282 };
12283
12284 enum {
12285         MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER  = 0x0,
12286         MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR  = 0x1,
12287 };
12288
12289 struct mlx5_ifc_resume_vhca_in_bits {
12290         u8         opcode[0x10];
12291         u8         uid[0x10];
12292
12293         u8         reserved_at_20[0x10];
12294         u8         op_mod[0x10];
12295
12296         u8         reserved_at_40[0x10];
12297         u8         vhca_id[0x10];
12298
12299         u8         reserved_at_60[0x20];
12300 };
12301
12302 struct mlx5_ifc_resume_vhca_out_bits {
12303         u8         status[0x8];
12304         u8         reserved_at_8[0x18];
12305
12306         u8         syndrome[0x20];
12307
12308         u8         reserved_at_40[0x40];
12309 };
12310
12311 struct mlx5_ifc_query_vhca_migration_state_in_bits {
12312         u8         opcode[0x10];
12313         u8         uid[0x10];
12314
12315         u8         reserved_at_20[0x10];
12316         u8         op_mod[0x10];
12317
12318         u8         incremental[0x1];
12319         u8         reserved_at_41[0xf];
12320         u8         vhca_id[0x10];
12321
12322         u8         reserved_at_60[0x20];
12323 };
12324
12325 struct mlx5_ifc_query_vhca_migration_state_out_bits {
12326         u8         status[0x8];
12327         u8         reserved_at_8[0x18];
12328
12329         u8         syndrome[0x20];
12330
12331         u8         reserved_at_40[0x40];
12332
12333         u8         required_umem_size[0x20];
12334
12335         u8         reserved_at_a0[0x160];
12336 };
12337
12338 struct mlx5_ifc_save_vhca_state_in_bits {
12339         u8         opcode[0x10];
12340         u8         uid[0x10];
12341
12342         u8         reserved_at_20[0x10];
12343         u8         op_mod[0x10];
12344
12345         u8         incremental[0x1];
12346         u8         set_track[0x1];
12347         u8         reserved_at_42[0xe];
12348         u8         vhca_id[0x10];
12349
12350         u8         reserved_at_60[0x20];
12351
12352         u8         va[0x40];
12353
12354         u8         mkey[0x20];
12355
12356         u8         size[0x20];
12357 };
12358
12359 struct mlx5_ifc_save_vhca_state_out_bits {
12360         u8         status[0x8];
12361         u8         reserved_at_8[0x18];
12362
12363         u8         syndrome[0x20];
12364
12365         u8         actual_image_size[0x20];
12366
12367         u8         reserved_at_60[0x20];
12368 };
12369
12370 struct mlx5_ifc_load_vhca_state_in_bits {
12371         u8         opcode[0x10];
12372         u8         uid[0x10];
12373
12374         u8         reserved_at_20[0x10];
12375         u8         op_mod[0x10];
12376
12377         u8         reserved_at_40[0x10];
12378         u8         vhca_id[0x10];
12379
12380         u8         reserved_at_60[0x20];
12381
12382         u8         va[0x40];
12383
12384         u8         mkey[0x20];
12385
12386         u8         size[0x20];
12387 };
12388
12389 struct mlx5_ifc_load_vhca_state_out_bits {
12390         u8         status[0x8];
12391         u8         reserved_at_8[0x18];
12392
12393         u8         syndrome[0x20];
12394
12395         u8         reserved_at_40[0x40];
12396 };
12397
12398 struct mlx5_ifc_adv_virtualization_cap_bits {
12399         u8         reserved_at_0[0x3];
12400         u8         pg_track_log_max_num[0x5];
12401         u8         pg_track_max_num_range[0x8];
12402         u8         pg_track_log_min_addr_space[0x8];
12403         u8         pg_track_log_max_addr_space[0x8];
12404
12405         u8         reserved_at_20[0x3];
12406         u8         pg_track_log_min_msg_size[0x5];
12407         u8         reserved_at_28[0x3];
12408         u8         pg_track_log_max_msg_size[0x5];
12409         u8         reserved_at_30[0x3];
12410         u8         pg_track_log_min_page_size[0x5];
12411         u8         reserved_at_38[0x3];
12412         u8         pg_track_log_max_page_size[0x5];
12413
12414         u8         reserved_at_40[0x7c0];
12415 };
12416
12417 struct mlx5_ifc_page_track_report_entry_bits {
12418         u8         dirty_address_high[0x20];
12419
12420         u8         dirty_address_low[0x20];
12421 };
12422
12423 enum {
12424         MLX5_PAGE_TRACK_STATE_TRACKING,
12425         MLX5_PAGE_TRACK_STATE_REPORTING,
12426         MLX5_PAGE_TRACK_STATE_ERROR,
12427 };
12428
12429 struct mlx5_ifc_page_track_range_bits {
12430         u8         start_address[0x40];
12431
12432         u8         length[0x40];
12433 };
12434
12435 struct mlx5_ifc_page_track_bits {
12436         u8         modify_field_select[0x40];
12437
12438         u8         reserved_at_40[0x10];
12439         u8         vhca_id[0x10];
12440
12441         u8         reserved_at_60[0x20];
12442
12443         u8         state[0x4];
12444         u8         track_type[0x4];
12445         u8         log_addr_space_size[0x8];
12446         u8         reserved_at_90[0x3];
12447         u8         log_page_size[0x5];
12448         u8         reserved_at_98[0x3];
12449         u8         log_msg_size[0x5];
12450
12451         u8         reserved_at_a0[0x8];
12452         u8         reporting_qpn[0x18];
12453
12454         u8         reserved_at_c0[0x18];
12455         u8         num_ranges[0x8];
12456
12457         u8         reserved_at_e0[0x20];
12458
12459         u8         range_start_address[0x40];
12460
12461         u8         length[0x40];
12462
12463         struct     mlx5_ifc_page_track_range_bits track_range[0];
12464 };
12465
12466 struct mlx5_ifc_create_page_track_obj_in_bits {
12467         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12468         struct mlx5_ifc_page_track_bits obj_context;
12469 };
12470
12471 struct mlx5_ifc_modify_page_track_obj_in_bits {
12472         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12473         struct mlx5_ifc_page_track_bits obj_context;
12474 };
12475
12476 #endif /* MLX5_IFC_H */