1 // SPDX-License-Identifier: GPL-2.0
3 // Driver for Microchip S/PDIF TX Controller
5 // Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
7 // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
11 #include <linux/module.h>
12 #include <linux/spinlock.h>
14 #include <sound/asoundef.h>
15 #include <sound/dmaengine_pcm.h>
16 #include <sound/pcm_params.h>
17 #include <sound/soc.h>
20 * ---- S/PDIF Transmitter Controller Register map ----
22 #define SPDIFTX_CR 0x00 /* Control Register */
23 #define SPDIFTX_MR 0x04 /* Mode Register */
24 #define SPDIFTX_CDR 0x0C /* Common Data Register */
26 #define SPDIFTX_IER 0x14 /* Interrupt Enable Register */
27 #define SPDIFTX_IDR 0x18 /* Interrupt Disable Register */
28 #define SPDIFTX_IMR 0x1C /* Interrupt Mask Register */
29 #define SPDIFTX_ISR 0x20 /* Interrupt Status Register */
31 #define SPDIFTX_CH1UD(reg) (0x50 + (reg) * 4) /* User Data 1 Register x */
32 #define SPDIFTX_CH1S(reg) (0x80 + (reg) * 4) /* Channel Status 1 Register x */
34 #define SPDIFTX_VERSION 0xF0
37 * ---- Control Register (Write-only) ----
39 #define SPDIFTX_CR_SWRST BIT(0) /* Software Reset */
40 #define SPDIFTX_CR_FCLR BIT(1) /* FIFO clear */
43 * ---- Mode Register (Read/Write) ----
46 #define SPDIFTX_MR_TXEN_MASK GENMASK(0, 0)
47 #define SPDIFTX_MR_TXEN_DISABLE (0 << 0)
48 #define SPDIFTX_MR_TXEN_ENABLE (1 << 0)
50 /* Multichannel Transfer */
51 #define SPDIFTX_MR_MULTICH_MASK GENAMSK(1, 1)
52 #define SPDIFTX_MR_MULTICH_MONO (0 << 1)
53 #define SPDIFTX_MR_MULTICH_DUAL (1 << 1)
55 /* Data Word Endian Mode */
56 #define SPDIFTX_MR_ENDIAN_MASK GENMASK(2, 2)
57 #define SPDIFTX_MR_ENDIAN_LITTLE (0 << 2)
58 #define SPDIFTX_MR_ENDIAN_BIG (1 << 2)
60 /* Data Justification */
61 #define SPDIFTX_MR_JUSTIFY_MASK GENMASK(3, 3)
62 #define SPDIFTX_MR_JUSTIFY_LSB (0 << 3)
63 #define SPDIFTX_MR_JUSTIFY_MSB (1 << 3)
65 /* Common Audio Register Transfer Mode */
66 #define SPDIFTX_MR_CMODE_MASK GENMASK(5, 4)
67 #define SPDIFTX_MR_CMODE_INDEX_ACCESS (0 << 4)
68 #define SPDIFTX_MR_CMODE_TOGGLE_ACCESS (1 << 4)
69 #define SPDIFTX_MR_CMODE_INTERLVD_ACCESS (2 << 4)
71 /* Valid Bits per Sample */
72 #define SPDIFTX_MR_VBPS_MASK GENMASK(13, 8)
73 #define SPDIFTX_MR_VBPS(bps) (((bps) << 8) & SPDIFTX_MR_VBPS_MASK)
76 #define SPDIFTX_MR_CHUNK_MASK GENMASK(19, 16)
77 #define SPDIFTX_MR_CHUNK(size) (((size) << 16) & SPDIFTX_MR_CHUNK_MASK)
79 /* Validity Bits for Channels 1 and 2 */
80 #define SPDIFTX_MR_VALID1 BIT(24)
81 #define SPDIFTX_MR_VALID2 BIT(25)
83 /* Disable Null Frame on underrun */
84 #define SPDIFTX_MR_DNFR_MASK GENMASK(27, 27)
85 #define SPDIFTX_MR_DNFR_INVALID (0 << 27)
86 #define SPDIFTX_MR_DNFR_VALID (1 << 27)
88 /* Bytes per Sample */
89 #define SPDIFTX_MR_BPS_MASK GENMASK(29, 28)
90 #define SPDIFTX_MR_BPS(bytes) \
91 ((((bytes) - 1) << 28) & SPDIFTX_MR_BPS_MASK)
94 * ---- Interrupt Enable/Disable/Mask/Status Register (Write/Read-only) ----
96 #define SPDIFTX_IR_TXRDY BIT(0)
97 #define SPDIFTX_IR_TXEMPTY BIT(1)
98 #define SPDIFTX_IR_TXFULL BIT(2)
99 #define SPDIFTX_IR_TXCHUNK BIT(3)
100 #define SPDIFTX_IR_TXUDR BIT(4)
101 #define SPDIFTX_IR_TXOVR BIT(5)
102 #define SPDIFTX_IR_CSRDY BIT(6)
103 #define SPDIFTX_IR_UDRDY BIT(7)
104 #define SPDIFTX_IR_TXRDYCH(ch) BIT((ch) + 8)
105 #define SPDIFTX_IR_SECE BIT(10)
106 #define SPDIFTX_IR_TXUDRCH(ch) BIT((ch) + 11)
107 #define SPDIFTX_IR_BEND BIT(13)
109 static bool mchp_spdiftx_readable_reg(struct device *dev, unsigned int reg)
115 case SPDIFTX_CH1UD(0):
116 case SPDIFTX_CH1UD(1):
117 case SPDIFTX_CH1UD(2):
118 case SPDIFTX_CH1UD(3):
119 case SPDIFTX_CH1UD(4):
120 case SPDIFTX_CH1UD(5):
121 case SPDIFTX_CH1S(0):
122 case SPDIFTX_CH1S(1):
123 case SPDIFTX_CH1S(2):
124 case SPDIFTX_CH1S(3):
125 case SPDIFTX_CH1S(4):
126 case SPDIFTX_CH1S(5):
133 static bool mchp_spdiftx_writeable_reg(struct device *dev, unsigned int reg)
141 case SPDIFTX_CH1UD(0):
142 case SPDIFTX_CH1UD(1):
143 case SPDIFTX_CH1UD(2):
144 case SPDIFTX_CH1UD(3):
145 case SPDIFTX_CH1UD(4):
146 case SPDIFTX_CH1UD(5):
147 case SPDIFTX_CH1S(0):
148 case SPDIFTX_CH1S(1):
149 case SPDIFTX_CH1S(2):
150 case SPDIFTX_CH1S(3):
151 case SPDIFTX_CH1S(4):
152 case SPDIFTX_CH1S(5):
159 static bool mchp_spdiftx_precious_reg(struct device *dev, unsigned int reg)
170 static const struct regmap_config mchp_spdiftx_regmap_config = {
174 .max_register = SPDIFTX_VERSION,
175 .readable_reg = mchp_spdiftx_readable_reg,
176 .writeable_reg = mchp_spdiftx_writeable_reg,
177 .precious_reg = mchp_spdiftx_precious_reg,
180 #define SPDIFTX_GCLK_RATIO 128
182 #define SPDIFTX_CS_BITS 192
183 #define SPDIFTX_UD_BITS 192
185 struct mchp_spdiftx_mixer_control {
186 unsigned char ch_stat[SPDIFTX_CS_BITS / 8];
187 unsigned char user_data[SPDIFTX_UD_BITS / 8];
188 spinlock_t lock; /* exclusive access to control data */
191 struct mchp_spdiftx_dev {
192 struct mchp_spdiftx_mixer_control control;
193 struct snd_dmaengine_dai_dma_data playback;
195 struct regmap *regmap;
199 unsigned int gclk_enabled:1;
202 static inline int mchp_spdiftx_is_running(struct mchp_spdiftx_dev *dev)
206 regmap_read(dev->regmap, SPDIFTX_MR, &mr);
207 return !!(mr & SPDIFTX_MR_TXEN_ENABLE);
210 static void mchp_spdiftx_channel_status_write(struct mchp_spdiftx_dev *dev)
212 struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
216 for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat) / 4; i++) {
217 val = (ctrl->ch_stat[(i * 4) + 0] << 0) |
218 (ctrl->ch_stat[(i * 4) + 1] << 8) |
219 (ctrl->ch_stat[(i * 4) + 2] << 16) |
220 (ctrl->ch_stat[(i * 4) + 3] << 24);
222 regmap_write(dev->regmap, SPDIFTX_CH1S(i), val);
226 static void mchp_spdiftx_user_data_write(struct mchp_spdiftx_dev *dev)
228 struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
232 for (i = 0; i < ARRAY_SIZE(ctrl->user_data) / 4; i++) {
233 val = (ctrl->user_data[(i * 4) + 0] << 0) |
234 (ctrl->user_data[(i * 4) + 1] << 8) |
235 (ctrl->user_data[(i * 4) + 2] << 16) |
236 (ctrl->user_data[(i * 4) + 3] << 24);
238 regmap_write(dev->regmap, SPDIFTX_CH1UD(i), val);
242 static irqreturn_t mchp_spdiftx_interrupt(int irq, void *dev_id)
244 struct mchp_spdiftx_dev *dev = dev_id;
245 struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
246 u32 sr, imr, pending, idr = 0;
248 regmap_read(dev->regmap, SPDIFTX_ISR, &sr);
249 regmap_read(dev->regmap, SPDIFTX_IMR, &imr);
255 if (pending & SPDIFTX_IR_TXUDR) {
256 dev_warn(dev->dev, "underflow detected\n");
257 idr |= SPDIFTX_IR_TXUDR;
260 if (pending & SPDIFTX_IR_TXOVR) {
261 dev_warn(dev->dev, "overflow detected\n");
262 idr |= SPDIFTX_IR_TXOVR;
265 if (pending & SPDIFTX_IR_UDRDY) {
266 spin_lock(&ctrl->lock);
267 mchp_spdiftx_user_data_write(dev);
268 spin_unlock(&ctrl->lock);
269 idr |= SPDIFTX_IR_UDRDY;
272 if (pending & SPDIFTX_IR_CSRDY) {
273 spin_lock(&ctrl->lock);
274 mchp_spdiftx_channel_status_write(dev);
275 spin_unlock(&ctrl->lock);
276 idr |= SPDIFTX_IR_CSRDY;
279 regmap_write(dev->regmap, SPDIFTX_IDR, idr);
284 static int mchp_spdiftx_dai_startup(struct snd_pcm_substream *substream,
285 struct snd_soc_dai *dai)
287 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
289 /* Software reset the IP */
290 regmap_write(dev->regmap, SPDIFTX_CR,
291 SPDIFTX_CR_SWRST | SPDIFTX_CR_FCLR);
296 static void mchp_spdiftx_dai_shutdown(struct snd_pcm_substream *substream,
297 struct snd_soc_dai *dai)
299 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
301 /* Disable interrupts */
302 regmap_write(dev->regmap, SPDIFTX_IDR, 0xffffffff);
305 static int mchp_spdiftx_trigger(struct snd_pcm_substream *substream, int cmd,
306 struct snd_soc_dai *dai)
308 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
309 struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
314 /* do not start/stop while channel status or user data is updated */
315 spin_lock(&ctrl->lock);
316 regmap_read(dev->regmap, SPDIFTX_MR, &mr);
317 running = !!(mr & SPDIFTX_MR_TXEN_ENABLE);
320 case SNDRV_PCM_TRIGGER_START:
321 case SNDRV_PCM_TRIGGER_RESUME:
322 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
324 mr &= ~SPDIFTX_MR_TXEN_MASK;
325 mr |= SPDIFTX_MR_TXEN_ENABLE;
328 case SNDRV_PCM_TRIGGER_STOP:
329 case SNDRV_PCM_TRIGGER_SUSPEND:
330 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
332 mr &= ~SPDIFTX_MR_TXEN_MASK;
333 mr |= SPDIFTX_MR_TXEN_DISABLE;
337 spin_unlock(&ctrl->lock);
341 ret = regmap_write(dev->regmap, SPDIFTX_MR, mr);
342 spin_unlock(&ctrl->lock);
344 dev_err(dev->dev, "unable to disable TX: %d\n", ret);
351 static int mchp_spdiftx_hw_params(struct snd_pcm_substream *substream,
352 struct snd_pcm_hw_params *params,
353 struct snd_soc_dai *dai)
356 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
357 struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
359 unsigned int bps = params_physical_width(params) / 8;
362 dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u\n",
363 __func__, params_rate(params), params_format(params),
364 params_width(params), params_channels(params));
366 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
367 dev_err(dev->dev, "Capture is not supported\n");
371 regmap_read(dev->regmap, SPDIFTX_MR, &mr);
373 if (mr & SPDIFTX_MR_TXEN_ENABLE) {
374 dev_err(dev->dev, "PCM already running\n");
378 /* Defaults: Toggle mode, justify to LSB, chunksize 1 */
379 mr = SPDIFTX_MR_CMODE_TOGGLE_ACCESS | SPDIFTX_MR_JUSTIFY_LSB;
380 dev->playback.maxburst = 1;
381 switch (params_channels(params)) {
383 mr |= SPDIFTX_MR_MULTICH_MONO;
386 mr |= SPDIFTX_MR_MULTICH_DUAL;
388 dev->playback.maxburst = 2;
391 dev_err(dev->dev, "unsupported number of channels: %d\n",
392 params_channels(params));
395 mr |= SPDIFTX_MR_CHUNK(dev->playback.maxburst);
397 switch (params_format(params)) {
398 case SNDRV_PCM_FORMAT_S8:
399 mr |= SPDIFTX_MR_VBPS(8);
401 case SNDRV_PCM_FORMAT_S16_BE:
402 mr |= SPDIFTX_MR_ENDIAN_BIG;
404 case SNDRV_PCM_FORMAT_S16_LE:
405 mr |= SPDIFTX_MR_VBPS(16);
407 case SNDRV_PCM_FORMAT_S18_3BE:
408 mr |= SPDIFTX_MR_ENDIAN_BIG;
410 case SNDRV_PCM_FORMAT_S18_3LE:
411 mr |= SPDIFTX_MR_VBPS(18);
413 case SNDRV_PCM_FORMAT_S20_3BE:
414 mr |= SPDIFTX_MR_ENDIAN_BIG;
416 case SNDRV_PCM_FORMAT_S20_3LE:
417 mr |= SPDIFTX_MR_VBPS(20);
419 case SNDRV_PCM_FORMAT_S24_3BE:
420 mr |= SPDIFTX_MR_ENDIAN_BIG;
422 case SNDRV_PCM_FORMAT_S24_3LE:
423 mr |= SPDIFTX_MR_VBPS(24);
425 case SNDRV_PCM_FORMAT_S24_BE:
426 mr |= SPDIFTX_MR_ENDIAN_BIG;
428 case SNDRV_PCM_FORMAT_S24_LE:
429 mr |= SPDIFTX_MR_VBPS(24);
431 case SNDRV_PCM_FORMAT_S32_BE:
432 mr |= SPDIFTX_MR_ENDIAN_BIG;
434 case SNDRV_PCM_FORMAT_S32_LE:
435 mr |= SPDIFTX_MR_VBPS(32);
438 dev_err(dev->dev, "unsupported PCM format: %d\n",
439 params_format(params));
443 mr |= SPDIFTX_MR_BPS(bps);
445 spin_lock_irqsave(&ctrl->lock, flags);
446 ctrl->ch_stat[3] &= ~IEC958_AES3_CON_FS;
447 switch (params_rate(params)) {
449 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_22050;
452 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_24000;
455 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_32000;
458 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_44100;
461 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_48000;
464 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_88200;
467 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_96000;
470 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_176400;
473 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_192000;
479 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_NOTID;
482 dev_err(dev->dev, "unsupported sample frequency: %u\n",
483 params_rate(params));
484 spin_unlock_irqrestore(&ctrl->lock, flags);
487 mchp_spdiftx_channel_status_write(dev);
488 spin_unlock_irqrestore(&ctrl->lock, flags);
490 if (dev->gclk_enabled) {
491 clk_disable_unprepare(dev->gclk);
492 dev->gclk_enabled = 0;
494 ret = clk_set_rate(dev->gclk, params_rate(params) *
498 "unable to change gclk rate to: rate %u * ratio %u\n",
499 params_rate(params), SPDIFTX_GCLK_RATIO);
502 ret = clk_prepare_enable(dev->gclk);
504 dev_err(dev->dev, "unable to enable gclk: %d\n", ret);
507 dev->gclk_enabled = 1;
508 dev_dbg(dev->dev, "%s(): GCLK set to %d\n", __func__,
509 params_rate(params) * SPDIFTX_GCLK_RATIO);
511 /* Enable interrupts */
512 regmap_write(dev->regmap, SPDIFTX_IER,
513 SPDIFTX_IR_TXUDR | SPDIFTX_IR_TXOVR);
515 regmap_write(dev->regmap, SPDIFTX_MR, mr);
520 static int mchp_spdiftx_hw_free(struct snd_pcm_substream *substream,
521 struct snd_soc_dai *dai)
523 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
525 regmap_write(dev->regmap, SPDIFTX_IDR,
526 SPDIFTX_IR_TXUDR | SPDIFTX_IR_TXOVR);
527 if (dev->gclk_enabled) {
528 clk_disable_unprepare(dev->gclk);
529 dev->gclk_enabled = 0;
532 return regmap_write(dev->regmap, SPDIFTX_CR,
533 SPDIFTX_CR_SWRST | SPDIFTX_CR_FCLR);
536 static const struct snd_soc_dai_ops mchp_spdiftx_dai_ops = {
537 .startup = mchp_spdiftx_dai_startup,
538 .shutdown = mchp_spdiftx_dai_shutdown,
539 .trigger = mchp_spdiftx_trigger,
540 .hw_params = mchp_spdiftx_hw_params,
541 .hw_free = mchp_spdiftx_hw_free,
544 #define MCHP_SPDIFTX_RATES SNDRV_PCM_RATE_8000_192000
546 #define MCHP_SPDIFTX_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
547 SNDRV_PCM_FMTBIT_S16_LE | \
548 SNDRV_PCM_FMTBIT_U16_BE | \
549 SNDRV_PCM_FMTBIT_S18_3LE | \
550 SNDRV_PCM_FMTBIT_S18_3BE | \
551 SNDRV_PCM_FMTBIT_S20_3LE | \
552 SNDRV_PCM_FMTBIT_S20_3BE | \
553 SNDRV_PCM_FMTBIT_S24_3LE | \
554 SNDRV_PCM_FMTBIT_S24_3BE | \
555 SNDRV_PCM_FMTBIT_S24_LE | \
556 SNDRV_PCM_FMTBIT_S24_BE | \
557 SNDRV_PCM_FMTBIT_S32_LE | \
558 SNDRV_PCM_FMTBIT_S32_BE \
561 static int mchp_spdiftx_info(struct snd_kcontrol *kcontrol,
562 struct snd_ctl_elem_info *uinfo)
564 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
570 static int mchp_spdiftx_cs_get(struct snd_kcontrol *kcontrol,
571 struct snd_ctl_elem_value *uvalue)
574 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
575 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
576 struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
578 spin_lock_irqsave(&ctrl->lock, flags);
579 memcpy(uvalue->value.iec958.status, ctrl->ch_stat,
580 sizeof(ctrl->ch_stat));
581 spin_unlock_irqrestore(&ctrl->lock, flags);
586 static int mchp_spdiftx_cs_put(struct snd_kcontrol *kcontrol,
587 struct snd_ctl_elem_value *uvalue)
590 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
591 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
592 struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
596 spin_lock_irqsave(&ctrl->lock, flags);
597 for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat); i++) {
598 if (ctrl->ch_stat[i] != uvalue->value.iec958.status[i])
600 ctrl->ch_stat[i] = uvalue->value.iec958.status[i];
604 /* don't enable IP while we copy the channel status */
605 if (mchp_spdiftx_is_running(dev)) {
607 * if SPDIF is running, wait for interrupt to write
610 regmap_write(dev->regmap, SPDIFTX_IER,
613 mchp_spdiftx_channel_status_write(dev);
616 spin_unlock_irqrestore(&ctrl->lock, flags);
621 static int mchp_spdiftx_cs_mask(struct snd_kcontrol *kcontrol,
622 struct snd_ctl_elem_value *uvalue)
624 memset(uvalue->value.iec958.status, 0xff,
625 sizeof(uvalue->value.iec958.status));
630 static int mchp_spdiftx_subcode_get(struct snd_kcontrol *kcontrol,
631 struct snd_ctl_elem_value *uvalue)
633 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
634 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
635 struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
638 spin_lock_irqsave(&ctrl->lock, flags);
639 memcpy(uvalue->value.iec958.subcode, ctrl->user_data,
640 sizeof(ctrl->user_data));
641 spin_unlock_irqrestore(&ctrl->lock, flags);
646 static int mchp_spdiftx_subcode_put(struct snd_kcontrol *kcontrol,
647 struct snd_ctl_elem_value *uvalue)
650 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
651 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
652 struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
656 spin_lock_irqsave(&ctrl->lock, flags);
657 for (i = 0; i < ARRAY_SIZE(ctrl->user_data); i++) {
658 if (ctrl->user_data[i] != uvalue->value.iec958.subcode[i])
661 ctrl->user_data[i] = uvalue->value.iec958.subcode[i];
664 if (mchp_spdiftx_is_running(dev)) {
666 * if SPDIF is running, wait for interrupt to write
669 regmap_write(dev->regmap, SPDIFTX_IER,
672 mchp_spdiftx_user_data_write(dev);
675 spin_unlock_irqrestore(&ctrl->lock, flags);
680 static struct snd_kcontrol_new mchp_spdiftx_ctrls[] = {
681 /* Channel status controller */
683 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
684 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
685 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
686 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
687 .info = mchp_spdiftx_info,
688 .get = mchp_spdiftx_cs_get,
689 .put = mchp_spdiftx_cs_put,
692 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
693 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
694 .access = SNDRV_CTL_ELEM_ACCESS_READ,
695 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
696 .info = mchp_spdiftx_info,
697 .get = mchp_spdiftx_cs_mask,
699 /* User bits controller */
701 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
702 .name = "IEC958 Subcode Playback Default",
703 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
704 .info = mchp_spdiftx_info,
705 .get = mchp_spdiftx_subcode_get,
706 .put = mchp_spdiftx_subcode_put,
710 static int mchp_spdiftx_dai_probe(struct snd_soc_dai *dai)
712 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
715 snd_soc_dai_init_dma_data(dai, &dev->playback, NULL);
717 ret = clk_prepare_enable(dev->pclk);
720 "failed to enable the peripheral clock: %d\n", ret);
725 snd_soc_add_dai_controls(dai, mchp_spdiftx_ctrls,
726 ARRAY_SIZE(mchp_spdiftx_ctrls));
731 static int mchp_spdiftx_dai_remove(struct snd_soc_dai *dai)
733 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
735 clk_disable_unprepare(dev->pclk);
740 static struct snd_soc_dai_driver mchp_spdiftx_dai = {
741 .name = "mchp-spdiftx",
742 .probe = mchp_spdiftx_dai_probe,
743 .remove = mchp_spdiftx_dai_remove,
745 .stream_name = "S/PDIF Playback",
748 .rates = MCHP_SPDIFTX_RATES,
749 .formats = MCHP_SPDIFTX_FORMATS,
751 .ops = &mchp_spdiftx_dai_ops,
754 static const struct snd_soc_component_driver mchp_spdiftx_component = {
755 .name = "mchp-spdiftx",
758 static const struct of_device_id mchp_spdiftx_dt_ids[] = {
760 .compatible = "microchip,sama7g5-spdiftx",
765 MODULE_DEVICE_TABLE(of, mchp_spdiftx_dt_ids);
766 static int mchp_spdiftx_probe(struct platform_device *pdev)
768 struct mchp_spdiftx_dev *dev;
769 struct resource *mem;
770 struct regmap *regmap;
772 struct mchp_spdiftx_mixer_control *ctrl;
776 /* Get memory for driver data. */
777 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
781 /* Map I/O registers. */
782 base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
784 return PTR_ERR(base);
786 regmap = devm_regmap_init_mmio(&pdev->dev, base,
787 &mchp_spdiftx_regmap_config);
789 return PTR_ERR(regmap);
792 irq = platform_get_irq(pdev, 0);
796 err = devm_request_irq(&pdev->dev, irq, mchp_spdiftx_interrupt, 0,
797 dev_name(&pdev->dev), dev);
801 /* Get the peripheral clock */
802 dev->pclk = devm_clk_get(&pdev->dev, "pclk");
803 if (IS_ERR(dev->pclk)) {
804 err = PTR_ERR(dev->pclk);
806 "failed to get the peripheral clock: %d\n", err);
810 /* Get the generic clock */
811 dev->gclk = devm_clk_get(&pdev->dev, "gclk");
812 if (IS_ERR(dev->gclk)) {
813 err = PTR_ERR(dev->gclk);
815 "failed to get the PMC generic clock: %d\n", err);
819 ctrl = &dev->control;
820 spin_lock_init(&ctrl->lock);
822 /* Init channel status */
823 ctrl->ch_stat[0] = IEC958_AES0_CON_NOT_COPYRIGHT |
824 IEC958_AES0_CON_EMPHASIS_NONE;
826 dev->dev = &pdev->dev;
827 dev->regmap = regmap;
828 platform_set_drvdata(pdev, dev);
830 dev->playback.addr = (dma_addr_t)mem->start + SPDIFTX_CDR;
831 dev->playback.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
833 err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
835 dev_err(&pdev->dev, "failed to register PMC: %d\n", err);
839 err = devm_snd_soc_register_component(&pdev->dev,
840 &mchp_spdiftx_component,
841 &mchp_spdiftx_dai, 1);
843 dev_err(&pdev->dev, "failed to register component: %d\n", err);
850 static struct platform_driver mchp_spdiftx_driver = {
851 .probe = mchp_spdiftx_probe,
853 .name = "mchp_spdiftx",
854 .of_match_table = of_match_ptr(mchp_spdiftx_dt_ids),
858 module_platform_driver(mchp_spdiftx_driver);
860 MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>");
861 MODULE_DESCRIPTION("Microchip S/PDIF TX Controller Driver");
862 MODULE_LICENSE("GPL v2");