]> git.itanic.dy.fi Git - linux-stable/commit
mips: dts: ralink: mt7621: add port@5 as CPU port
authorArınç ÜNAL <arinc.unal@arinc9.com>
Sat, 11 Feb 2023 10:49:15 +0000 (13:49 +0300)
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>
Fri, 17 Feb 2023 10:58:37 +0000 (11:58 +0100)
commitbae833414bfe6a33f6d55d5e0eb38e5989c6fe7b
treeecea91381b3dc8241ea9007d3064ca632097c384
parent09e61efd884ca68a768717d60858f138685b161b
mips: dts: ralink: mt7621: add port@5 as CPU port

On MT7621AT, MT7621DAT, and MT7621ST SoCs, port 5 of the MT7530 switch is
connected to the second MAC of the SoC as a CPU port. Add the port and set
up the second MAC on the bindings. Revert PHY muxing on GB-PC1.

There's an external PHY connected to the second MAC of the SoC on GB-PC2,
therefore, disable port@5 for this device.

Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts
arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts
arch/mips/boot/dts/ralink/mt7621.dtsi