};
};
- timers5: timer@40003000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40003000 0x400>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM5_K>;
- clock-names = "int";
- dmas = <&dmamux1 55 0x400 0x1>,
- <&dmamux1 56 0x400 0x1>,
- <&dmamux1 57 0x400 0x1>,
- <&dmamux1 58 0x400 0x1>,
- <&dmamux1 59 0x400 0x1>,
- <&dmamux1 60 0x400 0x1>;
- dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@4 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <4>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-timer-counter";
- status = "disabled";
- };
+ pwr_mcu: pwr_mcu@50001014 {
+ compatible = "st,stm32mp151-pwr-mcu", "syscon";
+ reg = <0x50001014 0x4>;
};
- timers6: timer@40004000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40004000 0x400>;
- interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM6_K>;
- clock-names = "int";
- dmas = <&dmamux1 69 0x400 0x1>;
- dma-names = "up";
- status = "disabled";
-
- timer@5 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <5>;
- status = "disabled";
- };
+ exti: interrupt-controller@5000d000 {
+ compatible = "st,stm32mp1-exti", "syscon";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x5000d000 0x400>;
++ interrupts-extended =
++ <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */
++ <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */
++ <&intc GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
++ <0>,
++ <0>,
++ <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
++ <0>, /* EXTI_20 */
++ <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */
++ <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
++ <0>,
++ <0>,
++ <0>,
++ <0>,
++ <0>,
++ <0>,
++ <0>, /* EXTI_40 */
++ <0>,
++ <0>,
++ <0>,
++ <0>,
++ <0>,
++ <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
++ <0>,
++ <&intc GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */
++ <0>,
++ <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
++ <0>,
++ <0>,
++ <0>,
++ <0>,
++ <0>,
++ <0>, /* EXTI_60 */
++ <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
++ <0>,
++ <0>,
++ <0>,
++ <&intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
++ <0>,
++ <0>,
++ <&intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
++ <0>,
++ <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */
++ <0>,
++ <0>,
++ <&intc GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
};
- timers7: timer@40005000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40005000 0x400>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM7_K>;
- clock-names = "int";
- dmas = <&dmamux1 70 0x400 0x1>;
- dma-names = "up";
- status = "disabled";
-
- timer@6 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <6>;
- status = "disabled";
- };
+ syscfg: syscon@50020000 {
+ compatible = "st,stm32mp157-syscfg", "syscon";
+ reg = <0x50020000 0x400>;
+ clocks = <&rcc SYSCFG>;
};
- timers12: timer@40006000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40006000 0x400>;
- interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM12_K>;
- clock-names = "int";
+ dts: thermal@50028000 {
+ compatible = "st,stm32-thermal";
+ reg = <0x50028000 0x100>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc TMPSENS>;
+ clock-names = "pclk";
+ #thermal-sensor-cells = <0>;
status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@11 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <11>;
- status = "disabled";
- };
};
- timers13: timer@40007000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40007000 0x400>;
- interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM13_K>;
- clock-names = "int";
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@12 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <12>;
- status = "disabled";
- };
+ mdma1: dma-controller@58000000 {
+ compatible = "st,stm32h7-mdma";
+ reg = <0x58000000 0x1000>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc MDMA>;
+ resets = <&rcc MDMA_R>;
+ #dma-cells = <5>;
+ dma-channels = <32>;
+ dma-requests = <48>;
};
- timers14: timer@40008000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-timers";
- reg = <0x40008000 0x400>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global";
- clocks = <&rcc TIM14_K>;
- clock-names = "int";
+ sdmmc1: mmc@58005000 {
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x00253180>;
+ reg = <0x58005000 0x1000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SDMMC1_K>;
+ clock-names = "apb_pclk";
+ resets = <&rcc SDMMC1_R>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <120000000>;
status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- timer@13 {
- compatible = "st,stm32h7-timer-trigger";
- reg = <13>;
- status = "disabled";
- };
};
- lptimer1: timer@40009000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32-lptimer";
- reg = <0x40009000 0x400>;
- interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc LPTIM1_K>;
- clock-names = "mux";
- wakeup-source;
- status = "disabled";
-
- pwm {
- compatible = "st,stm32-pwm-lp";
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- trigger@0 {
- compatible = "st,stm32-lptimer-trigger";
- reg = <0>;
- status = "disabled";
- };
-
- counter {
- compatible = "st,stm32-lptimer-counter";
- status = "disabled";
- };
- };
-
- spi2: spi@4000b000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "st,stm32h7-spi";
- reg = <0x4000b000 0x400>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc SPI2_K>;
- resets = <&rcc SPI2_R>;
- dmas = <&dmamux1 39 0x400 0x05>,
- <&dmamux1 40 0x400 0x05>;
- dma-names = "rx", "tx";
+ sdmmc2: mmc@58007000 {
+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x00253180>;
+ reg = <0x58007000 0x1000>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc SDMMC2_K>;
+ clock-names = "apb_pclk";
+ resets = <&rcc SDMMC2_R>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <120000000>;
status = "disabled";
};
projects / linux-stable / commitdiff