ARM: dts: renesas: r8a7740: Add LCDC nodes

Add device nodes for the two LCD Controllers (LCDC) on the R-Mobile A1
SoC, and for the two optional external LCDL clock inputs.

Note that the HDMI clock for LCDC1 is not added, as this clock is not
yet supported.

Based on a patch by Laurent Pinchart adding the first LCDC device node.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/12dcec10e6fb3b55c39f6221349d35d6d6f17a5d.1700669207.git.geert+renesas@glider.be

diff --git a/arch/arm/boot/dts/renesas/r8a7740.dtsi b/arch/arm/boot/dts/renesas/r8a7740.dtsi
index 1b2cf5fa322b298549910bed487f0d56b1d49997..55884ec701f8dab49ee2223dd0b9e03df7a07262 100644 (file)
--- a/arch/arm/boot/dts/renesas/r8a7740.dtsi
+++ b/arch/arm/boot/dts/renesas/r8a7740.dtsi
@@ -398,6 +398,61 @@ sh_fsi2: sound@fe1f0000 {
                status = "disabled";
        };
 
+       lcdc0: lcd-controller@fe940000 {
+               compatible = "renesas,r8a7740-lcdc";
+               reg = <0xfe940000 0x4000>;
+               interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp1_clks R8A7740_CLK_LCDC0>,
+                        <&cpg_clocks R8A7740_CLK_M3>, <&lcdlclk0_clk>,
+                        <&vou_clk>;
+               clock-names = "fck", "media", "lclk", "video";
+               power-domains = <&pd_a4lc>;
+               status = "disabled";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+
+                               lcdc0_rgb: endpoint {
+                               };
+                       };
+               };
+       };
+
+       lcdc1: lcd-controller@fe944000 {
+               compatible = "renesas,r8a7740-lcdc";
+               reg = <0xfe944000 0x4000>;
+               interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp1_clks R8A7740_CLK_LCDC1>,
+                        <&cpg_clocks R8A7740_CLK_M3>, <&lcdlclk1_clk>,
+                        <&vou_clk>;
+               clock-names = "fck", "media", "lclk", "video";
+               power-domains = <&pd_a4lc>;
+               status = "disabled";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+
+                               lcdc1_rgb: endpoint {
+                               };
+                       };
+
+                       port@1 {
+                               reg = <1>;
+
+                               lcdc1_hdmi: endpoint {
+                               };
+                       };
+               };
+       };
+
        tmu0: timer@fff80000 {
                compatible = "renesas,tmu-r8a7740", "renesas,tmu";
                reg = <0xfff80000 0x2c>;
@@ -474,6 +529,16 @@ fsibck_clk: fsibck {
                        #clock-cells = <0>;
                        clock-frequency = <0>;
                };
+               lcdlclk0_clk: lcdlclk0 {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <0>;
+               };
+               lcdlclk1_clk: lcdlclk1 {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <0>;
+               };
 
                /* Special CPG clocks */
                cpg_clocks: cpg_clocks@e6150000 {