PCI: Add PCI_L1SS_CTL2 fields

Add L1 PM Substates Control 2 Register fields (PCI_L1SS_CTL2_*).

Link: https://lore.kernel.org/r/20230915155752.84640-2-ilpo.jarvinen@linux.intel.com
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index e5f558d9649396faed564c9156ab3d03b9aaa7ab..3a7ea95815681482a21ed5d2ad0f771614c8b735 100644 (file)
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -1088,6 +1088,8 @@
 #define  PCI_L1SS_CTL1_LTR_L12_TH_VALUE        0x03ff0000  /* LTR_L1.2_THRESHOLD_Value */
 #define  PCI_L1SS_CTL1_LTR_L12_TH_SCALE        0xe0000000  /* LTR_L1.2_THRESHOLD_Scale */
 #define PCI_L1SS_CTL2          0x0c    /* Control 2 Register */
+#define  PCI_L1SS_CTL2_T_PWR_ON_SCALE  0x00000003  /* T_POWER_ON Scale */
+#define  PCI_L1SS_CTL2_T_PWR_ON_VALUE  0x000000f8  /* T_POWER_ON Value */
 
 /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */
 #define PCI_DVSEC_HEADER1              0x4 /* Designated Vendor-Specific Header1 */