]> git.itanic.dy.fi Git - linux-stable/commitdiff
drm/amdgpu/gfx: set sched.ready status after ring/IB test in gfx
authorGuchun Chen <guchun.chen@amd.com>
Fri, 12 May 2023 08:10:40 +0000 (16:10 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 9 Jun 2023 14:57:11 +0000 (10:57 -0400)
sched.ready is nothing with ring initialization, it needs to set
to be true after ring/IB test in amdgpu_ring_test_helper to tell
the ring is ready for submission.

Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

index 0d15002eac691ef6ed1f54279aed36179c665fa4..f7ad883a70fa25893699399a2b0b648664a6a179 100644 (file)
@@ -6073,7 +6073,6 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
        u32 tmp;
        u32 rb_bufsz;
        u64 rb_addr, rptr_addr, wptr_gpu_addr;
-       u32 i;
 
        /* Set the write pointer delay */
        WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
@@ -6168,11 +6167,6 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
        /* start the ring */
        gfx_v10_0_cp_gfx_start(adev);
 
-       for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
-               ring = &adev->gfx.gfx_ring[i];
-               ring->sched.ready = true;
-       }
-
        return 0;
 }
 
@@ -6470,7 +6464,7 @@ static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
 
                r = amdgpu_bo_reserve(ring->mqd_obj, false);
                if (unlikely(r != 0))
-                       goto done;
+                       return r;
 
                r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
                if (!r) {
@@ -6480,23 +6474,14 @@ static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
                }
                amdgpu_bo_unreserve(ring->mqd_obj);
                if (r)
-                       goto done;
+                       return r;
        }
 
        r = amdgpu_gfx_enable_kgq(adev, 0);
        if (r)
-               goto done;
-
-       r = gfx_v10_0_cp_gfx_start(adev);
-       if (r)
-               goto done;
+               return r;
 
-       for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
-               ring = &adev->gfx.gfx_ring[i];
-               ring->sched.ready = true;
-       }
-done:
-       return r;
+       return gfx_v10_0_cp_gfx_start(adev);
 }
 
 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
@@ -6812,7 +6797,6 @@ static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
        amdgpu_bo_kunmap(ring->mqd_obj);
        ring->mqd_ptr = NULL;
        amdgpu_bo_unreserve(ring->mqd_obj);
-       ring->sched.ready = true;
        return 0;
 }
 
index 4b7224de879ec1dea1198eb45827559dbb3a4488..da21bf868080e6a1d90858bff5e71a41c1440ee1 100644 (file)
@@ -3228,7 +3228,6 @@ static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev)
        u32 tmp;
        u32 rb_bufsz;
        u64 rb_addr, rptr_addr, wptr_gpu_addr;
-       u32 i;
 
        /* Set the write pointer delay */
        WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0);
@@ -3320,11 +3319,6 @@ static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev)
        /* start the ring */
        gfx_v11_0_cp_gfx_start(adev);
 
-       for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
-               ring = &adev->gfx.gfx_ring[i];
-               ring->sched.ready = true;
-       }
-
        return 0;
 }
 
@@ -3370,8 +3364,6 @@ static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
                WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data);
        }
 
-       adev->gfx.kiq[0].ring.sched.ready = enable;
-
        udelay(50);
 }
 
@@ -3711,7 +3703,7 @@ static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
 
                r = amdgpu_bo_reserve(ring->mqd_obj, false);
                if (unlikely(r != 0))
-                       goto done;
+                       return r;
 
                r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
                if (!r) {
@@ -3721,23 +3713,14 @@ static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
                }
                amdgpu_bo_unreserve(ring->mqd_obj);
                if (r)
-                       goto done;
+                       return r;
        }
 
        r = amdgpu_gfx_enable_kgq(adev, 0);
        if (r)
-               goto done;
-
-       r = gfx_v11_0_cp_gfx_start(adev);
-       if (r)
-               goto done;
+               return r;
 
-       for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
-               ring = &adev->gfx.gfx_ring[i];
-               ring->sched.ready = true;
-       }
-done:
-       return r;
+       return gfx_v11_0_cp_gfx_start(adev);
 }
 
 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
index 6d0589dc1d6ccc978153fedf61d74f962c78f934..2f1ef75e126c77f05d345e346492cba646e1222f 100644 (file)
@@ -4283,7 +4283,6 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
        /* start the ring */
        amdgpu_ring_clear_ring(ring);
        gfx_v8_0_cp_gfx_start(adev);
-       ring->sched.ready = true;
 
        return 0;
 }
@@ -4693,7 +4692,6 @@ static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)
        amdgpu_bo_kunmap(ring->mqd_obj);
        ring->mqd_ptr = NULL;
        amdgpu_bo_unreserve(ring->mqd_obj);
-       ring->sched.ready = true;
        return 0;
 }
 
index 8bf95a6b07677a5517eba25a7b631665cbac1277..fe090eafa3665254db56755b9c297f8852c7a150 100644 (file)
@@ -3144,7 +3144,6 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
 
        /* start the ring */
        gfx_v9_0_cp_gfx_start(adev);
-       ring->sched.ready = true;
 
        return 0;
 }
@@ -3623,7 +3622,6 @@ static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
        amdgpu_bo_kunmap(ring->mqd_obj);
        ring->mqd_ptr = NULL;
        amdgpu_bo_unreserve(ring->mqd_obj);
-       ring->sched.ready = true;
        return 0;
 }
 
index c54bf0b38fe149e64c07d7b532bd8eac941173dc..ed41a7862d9f9e7f0cd5d95a129b707631088e59 100644 (file)
@@ -1845,7 +1845,6 @@ static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id)
        amdgpu_bo_kunmap(ring->mqd_obj);
        ring->mqd_ptr = NULL;
        amdgpu_bo_unreserve(ring->mqd_obj);
-       ring->sched.ready = true;
        return 0;
 }