clk: imx: pll14xx: avoid glitch when set rate

[ Upstream commit dee1bc9c23cd41fe32549c0adbe6cb57cab02282 ]

According to PLL1443XA and PLL1416X spec,
"When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to
output unstable clock until lock time passes. PLL1416X/PLL1443XA may
generate a glitch at FOUT."

So set BYPASS when RESETB is changed from 0 to 1 to avoid glitch.
In the end of set rate, BYPASS will be cleared.

When prepare clock, also need to take care to avoid glitch. So
we also follow Spec to set BYPASS before RESETB changed from 0 to 1.
And add a check if the RESETB is already 0, directly return 0;

Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc")
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lkml.kernel.org/r/1568043491-20680-2-git-send-email-peng.fan@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
index b7213023b238fdeadbf0548b17790432956483c4..656f48b002dd3a2453b030de1d4798e4c9b16902 100644 (file)
--- a/drivers/clk/imx/clk-pll14xx.c
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -191,6 +191,10 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
        tmp &= ~RST_MASK;
        writel_relaxed(tmp, pll->base);
 
+       /* Enable BYPASS */
+       tmp |= BYPASS_MASK;
+       writel(tmp, pll->base);
+
        div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
                (rate->sdiv << SDIV_SHIFT);
        writel_relaxed(div_val, pll->base + 0x4);
@@ -250,6 +254,10 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
        tmp &= ~RST_MASK;
        writel_relaxed(tmp, pll->base);
 
+       /* Enable BYPASS */
+       tmp |= BYPASS_MASK;
+       writel_relaxed(tmp, pll->base);
+
        div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
                (rate->sdiv << SDIV_SHIFT);
        writel_relaxed(div_val, pll->base + 0x4);
@@ -283,16 +291,28 @@ static int clk_pll14xx_prepare(struct clk_hw *hw)
 {
        struct clk_pll14xx *pll = to_clk_pll14xx(hw);
        u32 val;
+       int ret;
 
        /*
         * RESETB = 1 from 0, PLL starts its normal
         * operation after lock time
         */
        val = readl_relaxed(pll->base + GNRL_CTL);
+       if (val & RST_MASK)
+               return 0;
+       val |= BYPASS_MASK;
+       writel_relaxed(val, pll->base + GNRL_CTL);
        val |= RST_MASK;
        writel_relaxed(val, pll->base + GNRL_CTL);
 
-       return clk_pll14xx_wait_lock(pll);
+       ret = clk_pll14xx_wait_lock(pll);
+       if (ret)
+               return ret;
+
+       val &= ~BYPASS_MASK;
+       writel_relaxed(val, pll->base + GNRL_CTL);
+
+       return 0;
 }
 
 static int clk_pll14xx_is_prepared(struct clk_hw *hw)