arm64: dts: rockchip: Set RK3399-Gru PCLK_EDP to 24 MHz

[ Upstream commit 8123437cf46ea5a0f6ca5cb3c528d8b6db97b9c2 ]

We've found the AUX channel to be less reliable with PCLK_EDP at a
higher rate (typically 25 MHz). This is especially important on systems
with PSR-enabled panels (like Gru-Kevin), since we make heavy, constant
use of AUX.

According to Rockchip, using any rate other than 24 MHz can cause
"problems between syncing the PHY an PCLK", which leads to all sorts of
unreliabilities around register operations.

Fixes: d67a38c5a623 ("arm64: dts: rockchip: move core edp from rk3399-kevin to shared chromebook")
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: zain wang <wzz@rock-chips.com>
Signed-off-by: Brian Norris <briannorris@chromium.org>
Link: https://lore.kernel.org/r/20220830131212.v2.1.I98d30623f13b785ca77094d0c0fd4339550553b6@changeid
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
index ff81dfda3b9524885956a20e7229da1c70ddf9ba..3ba927f3034791f8a9fa74a0bf8c5f15463bb73a 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
@@ -232,6 +232,14 @@ &cdn_dp {
 &edp {
        status = "okay";
 
+       /*
+        * eDP PHY/clk don't sync reliably at anything other than 24 MHz. Only
+        * set this here, because rk3399-gru.dtsi ensures we can generate this
+        * off GPLL=600MHz, whereas some other RK3399 boards may not.
+        */
+       assigned-clocks = <&cru PCLK_EDP>;
+       assigned-clock-rates = <24000000>;
+
        ports {
                edp_out: port@1 {
                        reg = <1>;