drm/i915/mtl: Extend PSR support

Meteorlake and display 14 platform don't have any PSR differences
when comparing to Alderlake-P display, so it was only necessary to
extend some checks to properly program hardware.

BSpec: 55229, 49196

Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220907081543.92268-1-mika.kahola@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index d4cce627d7a87f4b51575f1a45994f699130e019..16cf17b1e9d99820d2a450dbd345be1b0c3bf75c 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -533,7 +533,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 
        val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
 
-       if (!IS_ALDERLAKE_P(dev_priv))
+       if (DISPLAY_VER(dev_priv) <= 13 && !IS_ALDERLAKE_P(dev_priv))
                val |= EDP_SU_TRACK_ENABLE;
 
        if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
@@ -616,7 +616,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 static bool
 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans)
 {
-       if (IS_ALDERLAKE_P(dev_priv))
+       if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
                return trans == TRANSCODER_A || trans == TRANSCODER_B;
        else if (DISPLAY_VER(dev_priv) >= 12)
                return trans == TRANSCODER_A;
@@ -696,7 +696,7 @@ dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp,
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
        enum port port = dig_port->base.port;
 
-       if (IS_ALDERLAKE_P(dev_priv))
+       if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
                return pipe <= PIPE_B && port <= PORT_B;
        else
                return pipe == PIPE_A && port == PORT_A;
@@ -795,11 +795,11 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp,
                return intel_dp->psr.su_y_granularity == 4;
 
        /*
-        * adl_p has 1 line granularity. For other platforms with SW tracking we
-        * can adjust the y coordinates to match sink requirement if multiple of
-        * 4.
+        * adl_p and display 14+ platforms has 1 line granularity.
+        * For other platforms with SW tracking we can adjust the y coordinates
+        * to match sink requirement if multiple of 4.
         */
-       if (IS_ALDERLAKE_P(dev_priv))
+       if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
                y_granularity = intel_dp->psr.su_y_granularity;
        else if (intel_dp->psr.su_y_granularity <= 2)
                y_granularity = 4;
@@ -883,7 +883,8 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
         * resolution requires DSC to be enabled, priority is given to DSC
         * over PSR2.
         */
-       if (crtc_state->dsc.compression_enable) {
+       if (crtc_state->dsc.compression_enable &&
+           (DISPLAY_VER(dev_priv) <= 13 && !IS_ALDERLAKE_P(dev_priv))) {
                drm_dbg_kms(&dev_priv->drm,
                            "PSR2 cannot be enabled since DSC is enabled\n");
                return false;
@@ -1474,7 +1475,7 @@ static u32 man_trk_ctl_enable_bit_get(struct drm_i915_private *dev_priv)
 
 static u32 man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private *dev_priv)
 {
-       return IS_ALDERLAKE_P(dev_priv) ?
+       return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ?
               ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME :
               PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
 }
@@ -1627,7 +1628,7 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
        if (clip->y1 == -1)
                goto exit;
 
-       if (IS_ALDERLAKE_P(dev_priv)) {
+       if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) {
                val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1);
                val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 - 1);
        } else {
@@ -1664,7 +1665,15 @@ static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *c
                                                struct drm_rect *pipe_clip)
 {
        struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
-       const u16 y_alignment = crtc_state->su_y_granularity;
+       const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
+       u16 y_alignment;
+
+       /* ADLP aligns the SU region to vdsc slice height in case dsc is enabled */
+       if (crtc_state->dsc.compression_enable &&
+           (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14))
+               y_alignment = vdsc_cfg->slice_height;
+       else
+               y_alignment = crtc_state->su_y_granularity;
 
        pipe_clip->y1 -= pipe_clip->y1 % y_alignment;
        if (pipe_clip->y2 % y_alignment)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e43bb0a911e91e789c2064cde9bc1dc681ecaa41..975ce5e0a890ae8f6d6192b7bdd40351c50986e3 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8346,6 +8346,11 @@ enum skl_power_gate {
 #define GEN12_CULLBIT2                 _MMIO(0x7030)
 #define GEN12_STATE_ACK_DEBUG          _MMIO(0x20BC)
 
+#define _MTL_CLKGATE_DIS_TRANS_A                       0x604E8
+#define _MTL_CLKGATE_DIS_TRANS_B                       0x614E8
+#define MTL_CLKGATE_DIS_TRANS(trans)                   _MMIO_TRANS2(trans, _MTL_CLKGATE_DIS_TRANS_A)
+#define  MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS                REG_BIT(7)
+
 #define MTL_LATENCY_LP0_LP1            _MMIO(0x45780)
 #define MTL_LATENCY_LP2_LP3            _MMIO(0x45784)
 #define MTL_LATENCY_LP4_LP5            _MMIO(0x45788)