arm64: dts: renesas: r8a779g0: Restore sort order

[ Upstream commit 8b93657c976a61726d7ffbe8d019b84b4abfb673 ]

Numerical by unit address, alphabetical by node name.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/f00ef274a73c8fd60f940a1649423a8927b9ae8a.1705324708.git.geert+renesas@glider.be
Stable-dep-of: 08e799f6bce8 ("arm64: dts: renesas: r8a779g0: Add missing SCIF_CLK2")
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index d3d25e077c5d50531baf7d0dc2925f35f2dbc4c1..3be1159982b204e9a72ee056e0f4e6267d46de13 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -161,11 +161,6 @@ L3_CA76_1: cache-controller-1 {
                };
        };
 
-       psci {
-               compatible = "arm,psci-1.0", "arm,psci-0.2";
-               method = "smc";
-       };
-
        extal_clk: extal {
                compatible = "fixed-clock";
                #clock-cells = <0>;
@@ -185,6 +180,11 @@ pmu_a76 {
                interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
        };
 
+       psci {
+               compatible = "arm,psci-1.0", "arm,psci-0.2";
+               method = "smc";
+       };
+
        /* External SCIF clock - to be overridden by boards that provide it */
        scif_clk: scif {
                compatible = "fixed-clock";
@@ -1777,6 +1777,37 @@ ssi0: ssi-0 {
                        };
                };
 
+               mmc0: mmc@ee140000 {
+                       compatible = "renesas,sdhi-r8a779g0",
+                                    "renesas,rcar-gen4-sdhi";
+                       reg = <0 0xee140000 0 0x2000>;
+                       interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 706>,
+                                <&cpg CPG_CORE R8A779G0_CLK_SD0H>;
+                       clock-names = "core", "clkh";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 706>;
+                       max-frequency = <200000000>;
+                       iommus = <&ipmmu_ds0 32>;
+                       status = "disabled";
+               };
+
+               rpc: spi@ee200000 {
+                       compatible = "renesas,r8a779g0-rpc-if",
+                                    "renesas,rcar-gen4-rpc-if";
+                       reg = <0 0xee200000 0 0x200>,
+                             <0 0x08000000 0 0x04000000>,
+                             <0 0xee208000 0 0x100>;
+                       reg-names = "regs", "dirmap", "wbuf";
+                       interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 629>;
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 629>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
                ipmmu_rt0: iommu@ee480000 {
                        compatible = "renesas,ipmmu-r8a779g0",
                                     "renesas,rcar-gen4-ipmmu-vmsa";
@@ -1886,37 +1917,6 @@ ipmmu_mm: iommu@eefc0000 {
                        #iommu-cells = <1>;
                };
 
-               mmc0: mmc@ee140000 {
-                       compatible = "renesas,sdhi-r8a779g0",
-                                    "renesas,rcar-gen4-sdhi";
-                       reg = <0 0xee140000 0 0x2000>;
-                       interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 706>,
-                                <&cpg CPG_CORE R8A779G0_CLK_SD0H>;
-                       clock-names = "core", "clkh";
-                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
-                       resets = <&cpg 706>;
-                       max-frequency = <200000000>;
-                       iommus = <&ipmmu_ds0 32>;
-                       status = "disabled";
-               };
-
-               rpc: spi@ee200000 {
-                       compatible = "renesas,r8a779g0-rpc-if",
-                                    "renesas,rcar-gen4-rpc-if";
-                       reg = <0 0xee200000 0 0x200>,
-                             <0 0x08000000 0 0x04000000>,
-                             <0 0xee208000 0 0x100>;
-                       reg-names = "regs", "dirmap", "wbuf";
-                       interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 629>;
-                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
-                       resets = <&cpg 629>;
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-                       status = "disabled";
-               };
-
                gic: interrupt-controller@f1000000 {
                        compatible = "arm,gic-v3";
                        #interrupt-cells = <3>;