drm/i915/display/adlp: Implement new step in the TC voltage swing prog sequence

TC voltage swing programming sequence was updated with a new step.

BSpec: 54956
Cc: stable@vger.kernel.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220113174826.50272-1-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6ee0f77b79274203513a92814f4205ebfeb0ca88..4e93eac926a565ba80e7484f383088d4abbee5e3 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1300,6 +1300,28 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
 
                intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port),
                             DKL_TX_DP20BITMODE, 0);
+
+               if (IS_ALDERLAKE_P(dev_priv)) {
+                       u32 val;
+
+                       if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+                               if (ln == 0) {
+                                       val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
+                                       val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2);
+                               } else {
+                                       val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3);
+                                       val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3);
+                               }
+                       } else {
+                               val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
+                               val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
+                       }
+
+                       intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port),
+                                    DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
+                                    DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
+                                    val);
+               }
        }
 }
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b3a05ed86734da6a7c05561744b075b8df4e4434..4424807c8decaed81c32f2fb9883a9b330113360 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9968,8 +9968,12 @@ enum skl_power_gate {
                                                     _DKL_PHY2_BASE) + \
                                                     _DKL_TX_DPCNTL1)
 
-#define _DKL_TX_DPCNTL2                                0x2C8
-#define  DKL_TX_DP20BITMODE                            (1 << 2)
+#define _DKL_TX_DPCNTL2                                        0x2C8
+#define  DKL_TX_DP20BITMODE                            REG_BIT(2)
+#define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK     REG_GENMASK(4, 3)
+#define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val)     REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val))
+#define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK     REG_GENMASK(6, 5)
+#define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val)     REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val))
 #define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
                                                     _DKL_PHY1_BASE, \
                                                     _DKL_PHY2_BASE) + \