reg = <1>;
};
- /* switch nodes are enabled by U-Boot if modules are present */
+ /*
+ * NOTE: switch nodes are enabled by U-Boot if modules are present
+ * DO NOT change this node name (switch0@10) even if it is not following
+ * conventions! Deployed U-Boot binaries are explicitly looking for
+ * this node in order to augment the device tree!
+ */
switch0@10 {
compatible = "marvell,mv88e6190";
reg = <0x10>;
#address-cells = <1>;
#size-cells = <0>;
- switch0phy1: switch0phy1@1 {
+ switch0phy1: ethernet-phy@1 {
reg = <0x1>;
};
- switch0phy2: switch0phy2@2 {
+ switch0phy2: ethernet-phy@2 {
reg = <0x2>;
};
- switch0phy3: switch0phy3@3 {
+ switch0phy3: ethernet-phy@3 {
reg = <0x3>;
};
- switch0phy4: switch0phy4@4 {
+ switch0phy4: ethernet-phy@4 {
reg = <0x4>;
};
- switch0phy5: switch0phy5@5 {
+ switch0phy5: ethernet-phy@5 {
reg = <0x5>;
};
- switch0phy6: switch0phy6@6 {
+ switch0phy6: ethernet-phy@6 {
reg = <0x6>;
};
- switch0phy7: switch0phy7@7 {
+ switch0phy7: ethernet-phy@7 {
reg = <0x7>;
};
- switch0phy8: switch0phy8@8 {
+ switch0phy8: ethernet-phy@8 {
reg = <0x8>;
};
};
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@1 {
+ ethernet-port@1 {
reg = <0x1>;
label = "lan1";
phy-handle = <&switch0phy1>;
};
- port@2 {
+ ethernet-port@2 {
reg = <0x2>;
label = "lan2";
phy-handle = <&switch0phy2>;
};
- port@3 {
+ ethernet-port@3 {
reg = <0x3>;
label = "lan3";
phy-handle = <&switch0phy3>;
};
- port@4 {
+ ethernet-port@4 {
reg = <0x4>;
label = "lan4";
phy-handle = <&switch0phy4>;
};
- port@5 {
+ ethernet-port@5 {
reg = <0x5>;
label = "lan5";
phy-handle = <&switch0phy5>;
};
- port@6 {
+ ethernet-port@6 {
reg = <0x6>;
label = "lan6";
phy-handle = <&switch0phy6>;
};
- port@7 {
+ ethernet-port@7 {
reg = <0x7>;
label = "lan7";
phy-handle = <&switch0phy7>;
};
- port@8 {
+ ethernet-port@8 {
reg = <0x8>;
label = "lan8";
phy-handle = <&switch0phy8>;
};
- port@9 {
+ ethernet-port@9 {
reg = <0x9>;
label = "cpu";
ethernet = <ð1>;
managed = "in-band-status";
};
- switch0port10: port@a {
+ switch0port10: ethernet-port@a {
reg = <0xa>;
label = "dsa";
phy-mode = "2500base-x";
};
};
- switch0@2 {
+ ethernet-switch@2 {
compatible = "marvell,mv88e6085";
reg = <0x2>;
dsa,member = <0 0>;
#address-cells = <1>;
#size-cells = <0>;
- switch0phy1_topaz: switch0phy1@11 {
+ switch0phy1_topaz: ethernet-phy@11 {
reg = <0x11>;
};
- switch0phy2_topaz: switch0phy2@12 {
+ switch0phy2_topaz: ethernet-phy@12 {
reg = <0x12>;
};
- switch0phy3_topaz: switch0phy3@13 {
+ switch0phy3_topaz: ethernet-phy@13 {
reg = <0x13>;
};
- switch0phy4_topaz: switch0phy4@14 {
+ switch0phy4_topaz: ethernet-phy@14 {
reg = <0x14>;
};
};
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@1 {
+ ethernet-port@1 {
reg = <0x1>;
label = "lan1";
phy-handle = <&switch0phy1_topaz>;
};
- port@2 {
+ ethernet-port@2 {
reg = <0x2>;
label = "lan2";
phy-handle = <&switch0phy2_topaz>;
};
- port@3 {
+ ethernet-port@3 {
reg = <0x3>;
label = "lan3";
phy-handle = <&switch0phy3_topaz>;
};
- port@4 {
+ ethernet-port@4 {
reg = <0x4>;
label = "lan4";
phy-handle = <&switch0phy4_topaz>;
};
- port@5 {
+ ethernet-port@5 {
reg = <0x5>;
label = "cpu";
phy-mode = "2500base-x";
};
};
- switch1@11 {
+ ethernet-switch@11 {
compatible = "marvell,mv88e6190";
reg = <0x11>;
dsa,member = <0 1>;
#address-cells = <1>;
#size-cells = <0>;
- switch1phy1: switch1phy1@1 {
+ switch1phy1: ethernet-phy@1 {
reg = <0x1>;
};
- switch1phy2: switch1phy2@2 {
+ switch1phy2: ethernet-phy@2 {
reg = <0x2>;
};
- switch1phy3: switch1phy3@3 {
+ switch1phy3: ethernet-phy@3 {
reg = <0x3>;
};
- switch1phy4: switch1phy4@4 {
+ switch1phy4: ethernet-phy@4 {
reg = <0x4>;
};
- switch1phy5: switch1phy5@5 {
+ switch1phy5: ethernet-phy@5 {
reg = <0x5>;
};
- switch1phy6: switch1phy6@6 {
+ switch1phy6: ethernet-phy@6 {
reg = <0x6>;
};
- switch1phy7: switch1phy7@7 {
+ switch1phy7: ethernet-phy@7 {
reg = <0x7>;
};
- switch1phy8: switch1phy8@8 {
+ switch1phy8: ethernet-phy@8 {
reg = <0x8>;
};
};
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@1 {
+ ethernet-port@1 {
reg = <0x1>;
label = "lan9";
phy-handle = <&switch1phy1>;
};
- port@2 {
+ ethernet-port@2 {
reg = <0x2>;
label = "lan10";
phy-handle = <&switch1phy2>;
};
- port@3 {
+ ethernet-port@3 {
reg = <0x3>;
label = "lan11";
phy-handle = <&switch1phy3>;
};
- port@4 {
+ ethernet-port@4 {
reg = <0x4>;
label = "lan12";
phy-handle = <&switch1phy4>;
};
- port@5 {
+ ethernet-port@5 {
reg = <0x5>;
label = "lan13";
phy-handle = <&switch1phy5>;
};
- port@6 {
+ ethernet-port@6 {
reg = <0x6>;
label = "lan14";
phy-handle = <&switch1phy6>;
};
- port@7 {
+ ethernet-port@7 {
reg = <0x7>;
label = "lan15";
phy-handle = <&switch1phy7>;
};
- port@8 {
+ ethernet-port@8 {
reg = <0x8>;
label = "lan16";
phy-handle = <&switch1phy8>;
};
- switch1port9: port@9 {
+ switch1port9: ethernet-port@9 {
reg = <0x9>;
label = "dsa";
phy-mode = "2500base-x";
link = <&switch0port10>;
};
- switch1port10: port@a {
+ switch1port10: ethernet-port@a {
reg = <0xa>;
label = "dsa";
phy-mode = "2500base-x";
};
};
- switch1@2 {
+ ethernet-switch@2 {
compatible = "marvell,mv88e6085";
reg = <0x2>;
dsa,member = <0 1>;
#address-cells = <1>;
#size-cells = <0>;
- switch1phy1_topaz: switch1phy1@11 {
+ switch1phy1_topaz: ethernet-phy@11 {
reg = <0x11>;
};
- switch1phy2_topaz: switch1phy2@12 {
+ switch1phy2_topaz: ethernet-phy@12 {
reg = <0x12>;
};
- switch1phy3_topaz: switch1phy3@13 {
+ switch1phy3_topaz: ethernet-phy@13 {
reg = <0x13>;
};
- switch1phy4_topaz: switch1phy4@14 {
+ switch1phy4_topaz: ethernet-phy@14 {
reg = <0x14>;
};
};
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@1 {
+ ethernet-port@1 {
reg = <0x1>;
label = "lan9";
phy-handle = <&switch1phy1_topaz>;
};
- port@2 {
+ ethernet-port@2 {
reg = <0x2>;
label = "lan10";
phy-handle = <&switch1phy2_topaz>;
};
- port@3 {
+ ethernet-port@3 {
reg = <0x3>;
label = "lan11";
phy-handle = <&switch1phy3_topaz>;
};
- port@4 {
+ ethernet-port@4 {
reg = <0x4>;
label = "lan12";
phy-handle = <&switch1phy4_topaz>;
};
- port@5 {
+ ethernet-port@5 {
reg = <0x5>;
label = "dsa";
phy-mode = "2500base-x";
};
};
- switch2@12 {
+ ethernet-switch@12 {
compatible = "marvell,mv88e6190";
reg = <0x12>;
dsa,member = <0 2>;
#address-cells = <1>;
#size-cells = <0>;
- switch2phy1: switch2phy1@1 {
+ switch2phy1: ethernet-phy@1 {
reg = <0x1>;
};
- switch2phy2: switch2phy2@2 {
+ switch2phy2: ethernet-phy@2 {
reg = <0x2>;
};
- switch2phy3: switch2phy3@3 {
+ switch2phy3: ethernet-phy@3 {
reg = <0x3>;
};
- switch2phy4: switch2phy4@4 {
+ switch2phy4: ethernet-phy@4 {
reg = <0x4>;
};
- switch2phy5: switch2phy5@5 {
+ switch2phy5: ethernet-phy@5 {
reg = <0x5>;
};
- switch2phy6: switch2phy6@6 {
+ switch2phy6: ethernet-phy@6 {
reg = <0x6>;
};
- switch2phy7: switch2phy7@7 {
+ switch2phy7: ethernet-phy@7 {
reg = <0x7>;
};
- switch2phy8: switch2phy8@8 {
+ switch2phy8: ethernet-phy@8 {
reg = <0x8>;
};
};
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@1 {
+ ethernet-port@1 {
reg = <0x1>;
label = "lan17";
phy-handle = <&switch2phy1>;
};
- port@2 {
+ ethernet-port@2 {
reg = <0x2>;
label = "lan18";
phy-handle = <&switch2phy2>;
};
- port@3 {
+ ethernet-port@3 {
reg = <0x3>;
label = "lan19";
phy-handle = <&switch2phy3>;
};
- port@4 {
+ ethernet-port@4 {
reg = <0x4>;
label = "lan20";
phy-handle = <&switch2phy4>;
};
- port@5 {
+ ethernet-port@5 {
reg = <0x5>;
label = "lan21";
phy-handle = <&switch2phy5>;
};
- port@6 {
+ ethernet-port@6 {
reg = <0x6>;
label = "lan22";
phy-handle = <&switch2phy6>;
};
- port@7 {
+ ethernet-port@7 {
reg = <0x7>;
label = "lan23";
phy-handle = <&switch2phy7>;
};
- port@8 {
+ ethernet-port@8 {
reg = <0x8>;
label = "lan24";
phy-handle = <&switch2phy8>;
};
- switch2port9: port@9 {
+ switch2port9: ethernet-port@9 {
reg = <0x9>;
label = "dsa";
phy-mode = "2500base-x";
};
};
- switch2@2 {
+ ethernet-switch@2 {
compatible = "marvell,mv88e6085";
reg = <0x2>;
dsa,member = <0 2>;
#address-cells = <1>;
#size-cells = <0>;
- switch2phy1_topaz: switch2phy1@11 {
+ switch2phy1_topaz: ethernet-phy@11 {
reg = <0x11>;
};
- switch2phy2_topaz: switch2phy2@12 {
+ switch2phy2_topaz: ethernet-phy@12 {
reg = <0x12>;
};
- switch2phy3_topaz: switch2phy3@13 {
+ switch2phy3_topaz: ethernet-phy@13 {
reg = <0x13>;
};
- switch2phy4_topaz: switch2phy4@14 {
+ switch2phy4_topaz: ethernet-phy@14 {
reg = <0x14>;
};
};
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@1 {
+ ethernet-port@1 {
reg = <0x1>;
label = "lan17";
phy-handle = <&switch2phy1_topaz>;
};
- port@2 {
+ ethernet-port@2 {
reg = <0x2>;
label = "lan18";
phy-handle = <&switch2phy2_topaz>;
};
- port@3 {
+ ethernet-port@3 {
reg = <0x3>;
label = "lan19";
phy-handle = <&switch2phy3_topaz>;
};
- port@4 {
+ ethernet-port@4 {
reg = <0x4>;
label = "lan20";
phy-handle = <&switch2phy4_topaz>;
};
- port@5 {
+ ethernet-port@5 {
reg = <0x5>;
label = "dsa";
phy-mode = "2500base-x";
reg = <0>;
};
- switch6: switch0@6 {
+ switch6: ethernet-switch@6 {
/* Actual device is MV88E6393X */
compatible = "marvell,mv88e6190";
- #address-cells = <1>;
- #size-cells = <0>;
reg = <6>;
interrupt-parent = <&cp0_gpio1>;
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
dsa,member = <0 0>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@1 {
+ ethernet-port@1 {
reg = <1>;
label = "p1";
phy-handle = <&switch0phy1>;
};
- port@2 {
+ ethernet-port@2 {
reg = <2>;
label = "p2";
phy-handle = <&switch0phy2>;
};
- port@3 {
+ ethernet-port@3 {
reg = <3>;
label = "p3";
phy-handle = <&switch0phy3>;
};
- port@4 {
+ ethernet-port@4 {
reg = <4>;
label = "p4";
phy-handle = <&switch0phy4>;
};
- port@5 {
+ ethernet-port@5 {
reg = <5>;
label = "p5";
phy-handle = <&switch0phy5>;
};
- port@6 {
+ ethernet-port@6 {
reg = <6>;
label = "p6";
phy-handle = <&switch0phy6>;
};
- port@7 {
+ ethernet-port@7 {
reg = <7>;
label = "p7";
phy-handle = <&switch0phy7>;
};
- port@8 {
+ ethernet-port@8 {
reg = <8>;
label = "p8";
phy-handle = <&switch0phy8>;
};
- port@9 {
+ ethernet-port@9 {
reg = <9>;
label = "p9";
phy-mode = "10gbase-r";
managed = "in-band-status";
};
- port@a {
+ ethernet-port@a {
reg = <10>;
ethernet = <&cp0_eth0>;
phy-mode = "10gbase-r";
#address-cells = <1>;
#size-cells = <0>;
- switch0phy1: switch0phy1@1 {
+ switch0phy1: ethernet-phy@1 {
reg = <0x1>;
};
- switch0phy2: switch0phy2@2 {
+ switch0phy2: ethernet-phy@2 {
reg = <0x2>;
};
- switch0phy3: switch0phy3@3 {
+ switch0phy3: ethernet-phy@3 {
reg = <0x3>;
};
- switch0phy4: switch0phy4@4 {
+ switch0phy4: ethernet-phy@4 {
reg = <0x4>;
};
- switch0phy5: switch0phy5@5 {
+ switch0phy5: ethernet-phy@5 {
reg = <0x5>;
};
- switch0phy6: switch0phy6@6 {
+ switch0phy6: ethernet-phy@6 {
reg = <0x6>;
};
- switch0phy7: switch0phy7@7 {
+ switch0phy7: ethernet-phy@7 {
reg = <0x7>;
};
- switch0phy8: switch0phy8@8 {
+ switch0phy8: ethernet-phy@8 {
reg = <0x8>;
};
};