arm64: dts: rockchip: fix rk3399 hdmi ports node

[ Upstream commit f051b6ace7ffcc48d6d1017191f167c0a85799f6 ]

Fix rk3399 hdmi ports node so that it matches the
rockchip,dw-hdmi.yaml binding.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/a6ab6f75-3b80-40b1-bd30-3113e14becdd@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 6e12c5a920caba018fbecb2ba10c64c4ee527020..fe818a2700aa7319c26d1e51b4dd2ccf829ca61c 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1956,6 +1956,7 @@ simple-audio-card,codec {
        hdmi: hdmi@ff940000 {
                compatible = "rockchip,rk3399-dw-hdmi";
                reg = <0x0 0xff940000 0x0 0x20000>;
+               reg-io-width = <4>;
                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
                clocks = <&cru PCLK_HDMI_CTRL>,
                         <&cru SCLK_HDMI_SFR>,
@@ -1964,13 +1965,16 @@ hdmi: hdmi@ff940000 {
                         <&cru PLL_VPLL>;
                clock-names = "iahb", "isfr", "cec", "grf", "ref";
                power-domains = <&power RK3399_PD_HDCP>;
-               reg-io-width = <4>;
                rockchip,grf = <&grf>;
                #sound-dai-cells = <0>;
                status = "disabled";
 
                ports {
-                       hdmi_in: port {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       hdmi_in: port@0 {
+                               reg = <0>;
                                #address-cells = <1>;
                                #size-cells = <0>;
 
@@ -1983,6 +1987,10 @@ hdmi_in_vopl: endpoint@1 {
                                        remote-endpoint = <&vopl_out_hdmi>;
                                };
                        };
+
+                       hdmi_out: port@1 {
+                               reg = <1>;
+                       };
                };
        };