arm64: dts: mediatek: mt8192-asurada: Add MFG0 domain supply

The mfg0 power domain encompasses the whole GPU and its surrounding
glue logic. This power domain has a separate power rail.

Add its power supply for Asurada.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
[wenst@chromium.org: fix subject prefix and add commit message]
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
[Angelo: Reordered commits to address DVFS stability issues]
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230301095523.428461-10-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 9f12257ab4e7a4c851fe606f652b4d70120c05c0..ec013d5ef157e17b239d9dac722b7b5465818457 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -380,6 +380,10 @@ &i2c7 {
        pinctrl-0 = <&i2c7_pins>;
 };
 
+&mfg0 {
+       domain-supply = <&mt6315_7_vbuck1>;
+};
+
 &mipi_tx0 {
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index a29cdff8a09593f384f26bd999bbeaadbc6c0880..f19d4a8ef3f6ff8ca6629031f43df1b8932270a6 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -497,7 +497,7 @@ power-domain@MT8192_POWER_DOMAIN_CONN {
                                        #power-domain-cells = <0>;
                                };
 
-                               power-domain@MT8192_POWER_DOMAIN_MFG0 {
+                               mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 {
                                        reg = <MT8192_POWER_DOMAIN_MFG0>;
                                        clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>,
                                                 <&topckgen CLK_TOP_MFG_REF_SEL>;