PCI: tegra194: Use FIELD_GET()/FIELD_PREP() with Link Width fields

Use FIELD_GET() to extract PCIe Negotiated Link Width field instead of
custom masking and shifting.

Similarly, change custom code that misleadingly used
PCI_EXP_LNKSTA_NLW_SHIFT to prepare value for PCI_EXP_LNKCAP write
to use FIELD_PREP() with correct field define (PCI_EXP_LNKCAP_MLW).

Link: https://lore.kernel.org/r/20230919125648.1920-5-ilpo.jarvinen@linux.intel.com
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 4bba31502ce1d65ca5320c78c8d79cebc67be82c..248cd9347e8fdd2a86792ffeb9f90b2e5eafc911 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -9,6 +9,7 @@
  * Author: Vidya Sagar <vidyas@nvidia.com>
  */
 
+#include <linux/bitfield.h>
 #include <linux/clk.h>
 #include <linux/debugfs.h>
 #include <linux/delay.h>
@@ -346,8 +347,7 @@ static void apply_bad_link_workaround(struct dw_pcie_rp *pp)
         */
        val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
        if (val & PCI_EXP_LNKSTA_LBMS) {
-               current_link_width = (val & PCI_EXP_LNKSTA_NLW) >>
-                                    PCI_EXP_LNKSTA_NLW_SHIFT;
+               current_link_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val);
                if (pcie->init_link_width > current_link_width) {
                        dev_warn(pci->dev, "PCIe link is bad, width reduced\n");
                        val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
@@ -760,8 +760,7 @@ static void tegra_pcie_enable_system_interrupts(struct dw_pcie_rp *pp)
 
        val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +
                                  PCI_EXP_LNKSTA);
-       pcie->init_link_width = (val_w & PCI_EXP_LNKSTA_NLW) >>
-                               PCI_EXP_LNKSTA_NLW_SHIFT;
+       pcie->init_link_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val_w);
 
        val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +
                                  PCI_EXP_LNKCTL);
@@ -920,7 +919,7 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
        /* Configure Max lane width from DT */
        val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP);
        val &= ~PCI_EXP_LNKCAP_MLW;
-       val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT);
+       val |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, pcie->num_lanes);
        dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val);
 
        /* Clear Slot Clock Configuration bit if SRNS configuration */