]> git.itanic.dy.fi Git - linux-stable/commitdiff
drm/amd/display: Removing assert statements for Linux
authorSaaem Rizvi <SyedSaaem.Rizvi@amd.com>
Mon, 20 Jun 2022 14:25:19 +0000 (10:25 -0400)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 15 Sep 2022 08:47:20 +0000 (10:47 +0200)
commit 149f6d1a6035a7aa6595ac6eeb9c8f566b2103cd upstream.

[WHY]
Assert statements causing several bugs on Linux DM

[HOW]
Removing assert statement for Linux DM
(ASSERT(result == VBIOSSMC_Result_OK)). Also adding
logging statements for setting dcfclk.

Bug: https://bugzilla.kernel.org/show_bug.cgi?id=216092
Fixes: c1b972a18d05 ("drm/amd/display: Insert pulling smu busy status before sending another request")
Reviewed-by: Gabe Teeger <Gabe.Teeger@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Saaem Rizvi <SyedSaaem.Rizvi@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

index 4137394a6ace9184d7f616d1d4114bc211bf5198..27fbe906682f9f8ebc1ac770d7981ea8c8e7a45f 100644 (file)
@@ -101,9 +101,9 @@ static int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
        uint32_t result;
 
        result = rn_smu_wait_for_response(clk_mgr, 10, 200000);
-       ASSERT(result == VBIOSSMC_Result_OK);
 
-       smu_print("SMU response after wait: %d\n", result);
+       if (result != VBIOSSMC_Result_OK)
+               smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result);
 
        if (result == VBIOSSMC_Status_BUSY) {
                return -1;
@@ -188,6 +188,10 @@ int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int reque
                        VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
                        khz_to_mhz_ceil(requested_dcfclk_khz));
 
+#ifdef DBG
+       smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000);
+#endif
+
        return actual_dcfclk_set_mhz * 1000;
 }
 
index d8f03328558b489a0fd55b21383e3ee84f1cac80..e4f96b6fd79d0189896d50f94ab5eb70297db7dc 100644 (file)
@@ -102,7 +102,8 @@ static int dcn301_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
 
        result = dcn301_smu_wait_for_response(clk_mgr, 10, 200000);
 
-       smu_print("SMU response after wait: %d\n", result);
+       if (result != VBIOSSMC_Result_OK)
+               smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result);
 
        if (result == VBIOSSMC_Status_BUSY) {
                return -1;
@@ -179,6 +180,10 @@ int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int request
                        VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
                        khz_to_mhz_ceil(requested_dcfclk_khz));
 
+#ifdef DBG
+       smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000);
+#endif
+
        return actual_dcfclk_set_mhz * 1000;
 }
 
index 6a17f7ed4d01e4f8fc75108c6ccd8b2bbf8e0ef4..090b2c02aee17a134455774dc23885b01c669ace 100644 (file)
@@ -108,9 +108,9 @@ static int dcn31_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
        uint32_t result;
 
        result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000);
-       ASSERT(result == VBIOSSMC_Result_OK);
 
-       smu_print("SMU response after wait: %d\n", result);
+       if (result != VBIOSSMC_Result_OK)
+               smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result);
 
        if (result == VBIOSSMC_Status_BUSY) {
                return -1;
@@ -202,6 +202,10 @@ int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requeste
                        VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
                        khz_to_mhz_ceil(requested_dcfclk_khz));
 
+#ifdef DBG
+       smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000);
+#endif
+
        return actual_dcfclk_set_mhz * 1000;
 }
 
index 74a78fda62fb04382e2ea6d6f6101ceb57fc374e..925d6e13620ec7141526dff363bb8fd2240b9c32 100644 (file)
@@ -136,9 +136,9 @@ static int dcn315_smu_send_msg_with_param(
        uint32_t result;
 
        result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000);
-       ASSERT(result == VBIOSSMC_Result_OK);
 
-       smu_print("SMU response after wait: %d\n", result);
+       if (result != VBIOSSMC_Result_OK)
+               smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result);
 
        if (result == VBIOSSMC_Status_BUSY) {
                return -1;
@@ -205,6 +205,10 @@ int dcn315_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int request
                        VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
                        khz_to_mhz_ceil(requested_dcfclk_khz));
 
+#ifdef DBG
+       smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000);
+#endif
+
        return actual_dcfclk_set_mhz * 1000;
 }
 
index b2d1f24cfb804794b0a356f265e41ca46f33d119..457a9254ae1c846ae97567473ccffdb1179e085d 100644 (file)
@@ -124,9 +124,9 @@ static int dcn316_smu_send_msg_with_param(
        uint32_t result;
 
        result = dcn316_smu_wait_for_response(clk_mgr, 10, 200000);
-       ASSERT(result == VBIOSSMC_Result_OK);
 
-       smu_print("SMU response after wait: %d\n", result);
+       if (result != VBIOSSMC_Result_OK)
+               smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result);
 
        if (result == VBIOSSMC_Status_BUSY) {
                return -1;
@@ -191,6 +191,10 @@ int dcn316_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int request
                        VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
                        khz_to_mhz_ceil(requested_dcfclk_khz));
 
+#ifdef DBG
+       smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000);
+#endif
+
        return actual_dcfclk_set_mhz * 1000;
 }