drm/amd/display: Refactor eDP PSR codes

[ Upstream commit bd829d5707730072fecc3267016a675a4789905b ]

We split out PSR config from "global" to "per-panel" config settings.

Tested-by: Mark Broadworth <mark.broadworth@amd.com>
Reviewed-by: Robin Chen <robin.chen@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Ian Chen <ian.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stable-dep-of: d893f39320e1 ("drm/amd/display: Lowering min Z8 residency time")
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 0598465fd1a1b597eb174d882f5874a1236f98b8..8757d7ff8ff62b10f489bbf3e3bf9dacd2b41077 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -764,7 +764,6 @@ struct dc_debug_options {
        bool disable_mem_low_power;
        bool pstate_enabled;
        bool disable_dmcu;
-       bool disable_psr;
        bool force_abm_enable;
        bool disable_stereo_support;
        bool vsr_support;

diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index caf0c7af2d0b9984c5d747d23a7919a2ff55d287..17f080f8af6cd9d48d8c825231055a39906705bd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -117,7 +117,7 @@ struct psr_settings {
  * Add a struct dc_panel_config under dc_link
  */
 struct dc_panel_config {
-       // extra panel power sequence parameters
+       /* extra panel power sequence parameters */
        struct pps {
                unsigned int extra_t3_ms;
                unsigned int extra_t7_ms;
@@ -127,13 +127,21 @@ struct dc_panel_config {
                unsigned int extra_t12_ms;
                unsigned int extra_post_OUI_ms;
        } pps;
-       // ABM
+       /* PSR */
+       struct psr {
+               bool disable_psr;
+               bool disallow_psrsu;
+               bool rc_disable;
+               bool rc_allow_static_screen;
+               bool rc_allow_fullscreen_VPB;
+       } psr;
+       /* ABM */
        struct varib {
                unsigned int varibright_feature_enable;
                unsigned int def_varibright_level;
                unsigned int abm_config_setting;
        } varib;
-       // edp DSC
+       /* edp DSC */
        struct dsc {
                bool disable_dsc_edp;
                unsigned int force_dsc_edp_policy;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 887081472c0d8e3a0927c51f142e5e48ccf0dc19..ce6c70e25703db5b3518e8a843671205e34fc2ec 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -671,12 +671,15 @@ static const struct dc_debug_options debug_defaults_diags = {
                .disable_pplib_wm_range = true,
                .disable_stutter = true,
                .disable_48mhz_pwrdwn = true,
-               .disable_psr = true,
                .enable_tri_buf = true,
                .use_max_lb = true
 };
 
 static const struct dc_panel_config panel_config_defaults = {
+               .psr = {
+                       .disable_psr = false,
+                       .disallow_psrsu = false,
+               },
                .ilr = {
                        .optimize_edp_link_rate = true,
                },

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index e958f838c80411a7a8b33aa75a5f448b17a566cf..5a8d1a05131493f23d6d97c86ac840510162ab38 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -723,7 +723,6 @@ static const struct dc_debug_options debug_defaults_drv = {
        .underflow_assert_delay_us = 0xFFFFFFFF,
        .dwb_fi_phase = -1, // -1 = disable,
        .dmub_command_table = true,
-       .disable_psr = false,
        .use_max_lb = true,
        .exit_idle_opt_for_cursor_updates = true
 };
@@ -742,11 +741,17 @@ static const struct dc_debug_options debug_defaults_diags = {
        .scl_reset_length10 = true,
        .dwb_fi_phase = -1, // -1 = disable
        .dmub_command_table = true,
-       .disable_psr = true,
        .enable_tri_buf = true,
        .use_max_lb = true
 };
 
+static const struct dc_panel_config panel_config_defaults = {
+       .psr = {
+               .disable_psr = false,
+               .disallow_psrsu = false,
+       },
+};
+
 static void dcn30_dpp_destroy(struct dpp **dpp)
 {
        kfree(TO_DCN20_DPP(*dpp));
@@ -2214,6 +2219,11 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
        }
 }
 
+static void dcn30_get_panel_config_defaults(struct dc_panel_config *panel_config)
+{
+       *panel_config = panel_config_defaults;
+}
+
 static const struct resource_funcs dcn30_res_pool_funcs = {
        .destroy = dcn30_destroy_resource_pool,
        .link_enc_create = dcn30_link_encoder_create,
@@ -2233,6 +2243,7 @@ static const struct resource_funcs dcn30_res_pool_funcs = {
        .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
        .update_bw_bounding_box = dcn30_update_bw_bounding_box,
        .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
+       .get_panel_config_defaults = dcn30_get_panel_config_defaults,
 };
 
 #define CTX ctx

diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index b925b6ddde5a34d6e5afc0efc8d448c9e211ace0..d3945876acedadc2175b8c43798b14adf2dd7464 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -112,10 +112,16 @@ static const struct dc_debug_options debug_defaults_diags = {
                .dwb_fi_phase = -1, // -1 = disable
                .dmub_command_table = true,
                .enable_tri_buf = true,
-               .disable_psr = true,
                .use_max_lb = true
 };
 
+static const struct dc_panel_config panel_config_defaults = {
+               .psr = {
+                       .disable_psr = false,
+                       .disallow_psrsu = false,
+               },
+};
+
 enum dcn302_clk_src_array_id {
        DCN302_CLK_SRC_PLL0,
        DCN302_CLK_SRC_PLL1,
@@ -1132,6 +1138,11 @@ void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
        DC_FP_END();
 }
 
+static void dcn302_get_panel_config_defaults(struct dc_panel_config *panel_config)
+{
+       *panel_config = panel_config_defaults;
+}
+
 static struct resource_funcs dcn302_res_pool_funcs = {
                .destroy = dcn302_destroy_resource_pool,
                .link_enc_create = dcn302_link_encoder_create,
@@ -1151,6 +1162,7 @@ static struct resource_funcs dcn302_res_pool_funcs = {
                .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
                .update_bw_bounding_box = dcn302_update_bw_bounding_box,
                .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
+               .get_panel_config_defaults = dcn302_get_panel_config_defaults,
 };
 
 static struct dc_cap_funcs cap_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
index 527d5c902878549b031d24fb9e17fc3bf4f3df12..7e7f18bef0986fb5b8ec8fa90689a1fc75090d39 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
@@ -96,7 +96,13 @@ static const struct dc_debug_options debug_defaults_diags = {
                .dwb_fi_phase = -1, // -1 = disable
                .dmub_command_table = true,
                .enable_tri_buf = true,
-               .disable_psr = true,
+};
+
+static const struct dc_panel_config panel_config_defaults = {
+               .psr = {
+                       .disable_psr = false,
+                       .disallow_psrsu = false,
+               },
 };
 
 enum dcn303_clk_src_array_id {
@@ -1055,6 +1061,10 @@ static void dcn303_destroy_resource_pool(struct resource_pool **pool)
        *pool = NULL;
 }
 
+static void dcn303_get_panel_config_defaults(struct dc_panel_config *panel_config)
+{
+       *panel_config = panel_config_defaults;
+}
 
 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
 {
@@ -1082,6 +1092,7 @@ static struct resource_funcs dcn303_res_pool_funcs = {
                .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
                .update_bw_bounding_box = dcn303_update_bw_bounding_box,
                .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
+               .get_panel_config_defaults = dcn303_get_panel_config_defaults,
 };
 
 static struct dc_cap_funcs cap_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index d825f11b4feaaf934d6fd9ca06f8a98eab4970b2..d3f76512841b4fe2be3d8c8b910ad39742fdb0b5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -911,6 +911,10 @@ static const struct dc_debug_options debug_defaults_diags = {
 };
 
 static const struct dc_panel_config panel_config_defaults = {
+       .psr = {
+               .disable_psr = false,
+               .disallow_psrsu = false,
+       },
        .ilr = {
                .optimize_edp_link_rate = true,
        },

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index ffaa4e5b3fca0c58b7bc894990ed1e2ba9070539..94a90c8f3abbe6563e4f0275ffb1cc630bd4aab1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -940,6 +940,10 @@ static const struct dc_debug_options debug_defaults_diags = {
 };
 
 static const struct dc_panel_config panel_config_defaults = {
+       .psr = {
+               .disable_psr = false,
+               .disallow_psrsu = false,
+       },
        .ilr = {
                .optimize_edp_link_rate = true,
        },

diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
index 58746c437554f5f2f10edaf399b8a587ba8d309a..31cbc5762eab3c082b52be7163ba26a1cfb39bc4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
@@ -907,6 +907,10 @@ static const struct dc_debug_options debug_defaults_diags = {
 };
 
 static const struct dc_panel_config panel_config_defaults = {
+       .psr = {
+               .disable_psr = false,
+               .disallow_psrsu = false,
+       },
        .ilr = {
                .optimize_edp_link_rate = true,
        },

diff --git a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
index 6b40a11ac83a92a8085eb64c05ded39f11bab205..af3eddc0cf32ebdb4838198588cca17332ab942f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
@@ -906,6 +906,10 @@ static const struct dc_debug_options debug_defaults_diags = {
 };
 
 static const struct dc_panel_config panel_config_defaults = {
+       .psr = {
+               .disable_psr = false,
+               .disallow_psrsu = false,
+       },
        .ilr = {
                .optimize_edp_link_rate = true,
        },

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index 45db40c41882ca03e7fe10e2dd7b625ef94ef817..602e885ed52c40aad92bd00e14a786234fbce119 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -989,7 +989,7 @@ static enum dcn_zstate_support_state  decide_zstate_support(struct dc *dc, struc
 
                if (context->bw_ctx.dml.vba.StutterPeriod > 5000.0 || optimized_min_dst_y_next_start_us > 5000)
                        return DCN_ZSTATE_SUPPORT_ALLOW;
-               else if (link->psr_settings.psr_version == DC_PSR_VERSION_1 && !dc->debug.disable_psr)
+               else if (link->psr_settings.psr_version == DC_PSR_VERSION_1 && !link->panel_config.psr.disable_psr)
                        return DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;
                else
                        return DCN_ZSTATE_SUPPORT_DISALLOW;