clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks

[ Upstream commit abb3fa662b8f8eaed1590b0e7a4e19eda467cdd3 ]

According to the R-Car V4H Series Hardware User’s Manual Rev.1.00, the
parent clock of the Pin Function (PFC/GPIO) module clocks is the CP
clock.

Fix this by adding the missing CP clock, and correcting the PFC parents.

Fixes: f2afa78d5a0c0b0b ("dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions")
Fixes: 36ff366033f0dde1 ("clk: renesas: r8a779g0: Add PFC/GPIO clocks")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/5401fccd204dc90b44f0013e7f53b9eff8df8214.1706197297.git.geert+renesas@glider.be
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 31b13c997a057dafd62cc49c7e5be2310b4f30cb..c4b1938db76b35f4932e2b04103f0773be151909 100644 (file)
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -22,7 +22,7 @@
 
 enum clk_ids {
        /* Core Clock Outputs exported to DT */
-       LAST_DT_CORE_CLK = R8A779G0_CLK_R,
+       LAST_DT_CORE_CLK = R8A779G0_CLK_CP,
 
        /* External Input Clocks */
        CLK_EXTAL,
@@ -141,6 +141,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
        DEF_FIXED("svd2_vip",   R8A779G0_CLK_SVD2_VIP,  CLK_SV_VIP,     2, 1),
        DEF_FIXED("cbfusa",     R8A779G0_CLK_CBFUSA,    CLK_EXTAL,      2, 1),
        DEF_FIXED("cpex",       R8A779G0_CLK_CPEX,      CLK_EXTAL,      2, 1),
+       DEF_FIXED("cp",         R8A779G0_CLK_CP,        CLK_EXTAL,      2, 1),
        DEF_FIXED("viobus",     R8A779G0_CLK_VIOBUS,    CLK_VIO,        1, 1),
        DEF_FIXED("viobusd2",   R8A779G0_CLK_VIOBUSD2,  CLK_VIO,        2, 1),
        DEF_FIXED("vcbus",      R8A779G0_CLK_VCBUS,     CLK_VC,         1, 1),
@@ -232,10 +233,10 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
        DEF_MOD("cmt1",         911,    R8A779G0_CLK_R),
        DEF_MOD("cmt2",         912,    R8A779G0_CLK_R),
        DEF_MOD("cmt3",         913,    R8A779G0_CLK_R),
-       DEF_MOD("pfc0",         915,    R8A779G0_CLK_CL16M),
-       DEF_MOD("pfc1",         916,    R8A779G0_CLK_CL16M),
-       DEF_MOD("pfc2",         917,    R8A779G0_CLK_CL16M),
-       DEF_MOD("pfc3",         918,    R8A779G0_CLK_CL16M),
+       DEF_MOD("pfc0",         915,    R8A779G0_CLK_CP),
+       DEF_MOD("pfc1",         916,    R8A779G0_CLK_CP),
+       DEF_MOD("pfc2",         917,    R8A779G0_CLK_CP),
+       DEF_MOD("pfc3",         918,    R8A779G0_CLK_CP),
        DEF_MOD("tsc",          919,    R8A779G0_CLK_CL16M),
        DEF_MOD("tsn",          2723,   R8A779G0_CLK_S0D4_HSC),
        DEF_MOD("ssiu",         2926,   R8A779G0_CLK_S0D6_PER),

diff --git a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
index 754c54a6eb06a46dafeeb030df71dc6b96c16866..7850cdc62e2854939627552c8c34be6ff8625563 100644 (file)
--- a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
@@ -86,5 +86,6 @@
 #define R8A779G0_CLK_CPEX              74
 #define R8A779G0_CLK_CBFUSA            75
 #define R8A779G0_CLK_R                 76
+#define R8A779G0_CLK_CP                        77
 
 #endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */