if (flags & NO_CHIP_ERASE)
nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
- if (flags & SPI_NOR_RWW && nor->info->n_banks > 1 &&
+ if (flags & SPI_NOR_RWW && nor->params->n_banks > 1 &&
!nor->controller_ops)
nor->flags |= SNOR_F_RWW;
}
if (nor->flags & SNOR_F_HAS_LOCK && !nor->params->locking_ops)
spi_nor_init_default_locking_ops(nor);
- if (nor->info->n_banks > 1)
- params->bank_size = div64_u64(params->size, nor->info->n_banks);
+ if (params->n_banks > 1)
+ params->bank_size = div64_u64(params->size, params->n_banks);
return 0;
}
params->size = info->size;
params->bank_size = params->size;
params->page_size = info->page_size ?: SPI_NOR_DEFAULT_PAGE_SIZE;
+ params->n_banks = info->n_banks;
if (!(info->flags & SPI_NOR_NO_FR)) {
/* Default to Fast Read for DT and non-DT platform devices. */
* in octal DTR mode.
* @rdsr_addr_nbytes: dummy address bytes needed for Read Status Register
* command in octal DTR mode.
+ * @n_banks: number of banks.
* @n_dice: number of dice in the flash memory.
* @vreg_offset: volatile register offset for each die.
* @hwcaps: describes the read and page program hardware
u8 addr_mode_nbytes;
u8 rdsr_dummy;
u8 rdsr_addr_nbytes;
+ u8 n_banks;
u8 n_dice;
u32 *vreg_offset;