drm/msm/dpu: Add INTF_5 interrupts

[ Upstream commit 148e852f290fe8be9fa69953bee2f958befd65d4 ]

SC8180x has the eDP controller wired up to INTF_5, so add the interrupt
register block for this interface to the list.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220215043353.1256754-1-bjorn.andersson@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Stable-dep-of: e9d9ce5462fe ("drm/msm/dpu: Move non-MDP_TOP INTF_INTR offsets out of hwio header")
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index 2e816f232e859ec2347e7b1abff1833c5a1101d7..996011e356f7b72f130c204786f46a014a61c00c 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -20,6 +20,7 @@
 #define MDP_INTF_2_OFF                 0x6B000
 #define MDP_INTF_3_OFF                 0x6B800
 #define MDP_INTF_4_OFF                 0x6C000
+#define MDP_INTF_5_OFF                 0x6C800
 #define MDP_AD4_0_OFF                  0x7C000
 #define MDP_AD4_1_OFF                  0x7D000
 #define MDP_AD4_INTR_EN_OFF            0x41c
@@ -87,6 +88,11 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
                MDP_INTF_4_OFF+INTF_INTR_EN,
                MDP_INTF_4_OFF+INTF_INTR_STATUS
        },
+       {
+               MDP_INTF_5_OFF+INTF_INTR_CLEAR,
+               MDP_INTF_5_OFF+INTF_INTR_EN,
+               MDP_INTF_5_OFF+INTF_INTR_STATUS
+       },
        {
                MDP_AD4_0_OFF + MDP_AD4_INTR_CLEAR_OFF,
                MDP_AD4_0_OFF + MDP_AD4_INTR_EN_OFF,

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
index ac83c1159815f137461e8525b1e2e5ea353baf86..d90dac77c26fea4f60e529ba0d51b182eefb0de3 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
@@ -22,6 +22,7 @@ enum dpu_hw_intr_reg {
        MDP_INTF2_INTR,
        MDP_INTF3_INTR,
        MDP_INTF4_INTR,
+       MDP_INTF5_INTR,
        MDP_AD4_0_INTR,
        MDP_AD4_1_INTR,
        MDP_INTF0_7xxx_INTR,