arm64: dts: mediatek: mt8195: add DSI and MIPI DPHY nodes

Add the two DSI controller node and the associated DPHY nodes.
Individual boards have to enable them in the board device tree.

Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 10bde950c222e9f6b6b18067389d0256f08edd7d..97f0c6d38f4a0ee4ef1b8b6700f90aed248f66a1 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1714,6 +1714,26 @@ u2port3: usb-phy@0 {
                        };
                };
 
+               mipi_tx0: dsi-phy@11c80000 {
+                       compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
+                       reg = <0 0x11c80000 0 0x1000>;
+                       clocks = <&clk26m>;
+                       clock-output-names = "mipi_tx0_pll";
+                       #clock-cells = <0>;
+                       #phy-cells = <0>;
+                       status = "disabled";
+               };
+
+               mipi_tx1: dsi-phy@11c90000 {
+                       compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
+                       reg = <0 0x11c90000 0 0x1000>;
+                       clocks = <&clk26m>;
+                       clock-output-names = "mipi_tx1_pll";
+                       #clock-cells = <0>;
+                       #phy-cells = <0>;
+                       status = "disabled";
+               };
+
                i2c5: i2c@11d00000 {
                        compatible = "mediatek,mt8195-i2c",
                                     "mediatek,mt8192-i2c";
@@ -3129,6 +3149,20 @@ dither0: dither@1c007000 {
                        mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
                };
 
+               dsi0: dsi@1c008000 {
+                       compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
+                       reg = <0 0x1c008000 0 0x1000>;
+                       interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
+                       power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+                       clocks = <&vdosys0 CLK_VDO0_DSI0>,
+                                <&vdosys0 CLK_VDO0_DSI0_DSI>,
+                                <&mipi_tx0>;
+                       clock-names = "engine", "digital", "hs";
+                       phys = <&mipi_tx0>;
+                       phy-names = "dphy";
+                       status = "disabled";
+               };
+
                dsc0: dsc@1c009000 {
                        compatible = "mediatek,mt8195-disp-dsc";
                        reg = <0 0x1c009000 0 0x1000>;
@@ -3138,6 +3172,20 @@ dsc0: dsc@1c009000 {
                        mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
                };
 
+               dsi1: dsi@1c012000 {
+                       compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
+                       reg = <0 0x1c012000 0 0x1000>;
+                       interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>;
+                       power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+                       clocks = <&vdosys0 CLK_VDO0_DSI1>,
+                                <&vdosys0 CLK_VDO0_DSI1_DSI>,
+                                <&mipi_tx1>;
+                       clock-names = "engine", "digital", "hs";
+                       phys = <&mipi_tx1>;
+                       phy-names = "dphy";
+                       status = "disabled";
+               };
+
                merge0: merge@1c014000 {
                        compatible = "mediatek,mt8195-disp-merge";
                        reg = <0 0x1c014000 0 0x1000>;