drm/xe: Set default MOCS value for copy cs instructions

copy cs instructions that dont have a explict MOCS field will use this
default MOCS value.

v2:
- move to xe_hw_engine.c
- remove BLIT_CCTL auxiliary macros
- removed MASKED_REG

v3:
- rebased

v4:
- process workaround in hwe->reg_lrc

v5:
- add a new function and call it from xe_gt_record_default_lrcs()
because hwe->reg_lrc is initialized later

BSpec: 45807
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index 717d560626cecc92ae8a03a30a9915b3507ec74c..79873bf64e8dd833631f9e5c9a8446fe2eb78e3d 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -58,6 +58,12 @@
 
 #define RING_BBADDR(base)                      XE_REG((base) + 0x140)
 #define RING_BBADDR_UDW(base)                  XE_REG((base) + 0x168)
+
+/* Handling MOCS value in BLIT_CCTL like it was done CMD_CCTL */
+#define BLIT_CCTL(base)                                XE_REG((base) + 0x204)
+#define   BLIT_CCTL_DST_MOCS_MASK              REG_GENMASK(14, 9)
+#define   BLIT_CCTL_SRC_MOCS_MASK              REG_GENMASK(6, 1)
+
 #define RING_EXECLIST_STATUS_LO(base)          XE_REG((base) + 0x234)
 #define RING_EXECLIST_STATUS_HI(base)          XE_REG((base) + 0x234 + 4)
 

diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 603bb3ae3e370dded6e6e0dfd439af08a9df78a5..3afca3dd9657dc758ebbcba85490508dbca7ece0 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -225,6 +225,7 @@ int xe_gt_record_default_lrcs(struct xe_gt *gt)
 
                xe_reg_sr_init(&hwe->reg_lrc, hwe->name, xe);
                xe_wa_process_lrc(hwe);
+               xe_hw_engine_setup_default_lrc_state(hwe);
                xe_tuning_process_lrc(hwe);
 
                default_lrc = drmm_kzalloc(&xe->drm,

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 04ec276cfcf537fc0d0fc398bc241db9c8cb7e27..a9adac0624f695a4f7ae06bb0480a8c8862152eb 100644 (file)
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -268,6 +268,35 @@ void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
        hw_engine_mmio_read32(hwe, RING_MI_MODE(0).reg);
 }
 
+void
+xe_hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)
+{
+       struct xe_gt *gt = hwe->gt;
+       const u8 mocs_write_idx = gt->mocs.uc_index;
+       const u8 mocs_read_idx = gt->mocs.uc_index;
+       u32 blit_cctl_val = REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, mocs_write_idx) |
+                           REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, mocs_read_idx);
+       const struct xe_rtp_entry lrc_was[] = {
+               /*
+                * Some blitter commands do not have a field for MOCS, those
+                * commands will use MOCS index pointed by BLIT_CCTL.
+                * BLIT_CCTL registers are needed to be programmed to un-cached.
+                */
+               { XE_RTP_NAME("BLIT_CCTL_default_MOCS"),
+                 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED),
+                              ENGINE_CLASS(COPY)),
+                 XE_RTP_ACTIONS(FIELD_SET(BLIT_CCTL(0),
+                                BLIT_CCTL_DST_MOCS_MASK |
+                                BLIT_CCTL_SRC_MOCS_MASK,
+                                blit_cctl_val,
+                                XE_RTP_ACTION_FLAG(ENGINE_BASE)))
+               },
+               {}
+       };
+
+       xe_rtp_process(lrc_was, &hwe->reg_lrc, gt, hwe);
+}
+
 static void
 hw_engine_setup_default_state(struct xe_hw_engine *hwe)
 {

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.h b/drivers/gpu/drm/xe/xe_hw_engine.h
index ceab6539725687c4b0cddf54e80960b2e2561cd2..013efcd6d8c5b7e4960e894497752f520d329106 100644 (file)
--- a/drivers/gpu/drm/xe/xe_hw_engine.h
+++ b/drivers/gpu/drm/xe/xe_hw_engine.h
@@ -17,6 +17,7 @@ void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe);
 void xe_hw_engine_print_state(struct xe_hw_engine *hwe, struct drm_printer *p);
 u32 xe_hw_engine_mask_per_class(struct xe_gt *gt,
                                enum xe_engine_class engine_class);
+void xe_hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe);
 
 bool xe_hw_engine_is_reserved(struct xe_hw_engine *hwe);
 static inline bool xe_hw_engine_is_valid(struct xe_hw_engine *hwe)